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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cc2d3216 | 2 | /* |
d7276b80 | 3 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 | 4 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
cc2d3216 MZ |
5 | */ |
6 | ||
3f010cf1 | 7 | #include <linux/acpi.h> |
8d3554b8 | 8 | #include <linux/acpi_iort.h> |
ffedbf0c | 9 | #include <linux/bitfield.h> |
cc2d3216 MZ |
10 | #include <linux/bitmap.h> |
11 | #include <linux/cpu.h> | |
c6e2ccb6 | 12 | #include <linux/crash_dump.h> |
cc2d3216 | 13 | #include <linux/delay.h> |
3fb68fae | 14 | #include <linux/efi.h> |
cc2d3216 | 15 | #include <linux/interrupt.h> |
fa49364c | 16 | #include <linux/iommu.h> |
96806229 | 17 | #include <linux/iopoll.h> |
3f010cf1 | 18 | #include <linux/irqdomain.h> |
880cb3cd | 19 | #include <linux/list.h> |
cc2d3216 | 20 | #include <linux/log2.h> |
5e2c9f9a | 21 | #include <linux/memblock.h> |
cc2d3216 MZ |
22 | #include <linux/mm.h> |
23 | #include <linux/msi.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
dba0bc7b | 31 | #include <linux/syscore_ops.h> |
cc2d3216 | 32 | |
41a83e06 | 33 | #include <linux/irqchip.h> |
cc2d3216 | 34 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 35 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 36 | |
cc2d3216 MZ |
37 | #include <asm/cputype.h> |
38 | #include <asm/exception.h> | |
39 | ||
67510cca RR |
40 | #include "irq-gic-common.h" |
41 | ||
94100970 RR |
42 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
43 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 44 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
a8707f55 | 45 | #define ITS_FLAGS_FORCE_NON_SHAREABLE (1ULL << 3) |
cc2d3216 | 46 | |
c48ed51c | 47 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
c440a9d9 | 48 | #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) |
a8707f55 | 49 | #define RDIST_FLAGS_FORCE_NON_SHAREABLE (1 << 2) |
c48ed51c | 50 | |
c0cdc890 | 51 | #define RD_LOCAL_LPI_ENABLED BIT(0) |
d23bc2bc VS |
52 | #define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1) |
53 | #define RD_LOCAL_MEMRESERVE_DONE BIT(2) | |
c0cdc890 | 54 | |
a13b0404 MZ |
55 | static u32 lpi_id_bits; |
56 | ||
57 | /* | |
58 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
59 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
60 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
61 | */ | |
62 | #define LPI_NRBITS lpi_id_bits | |
63 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
64 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
65 | ||
2130b789 | 66 | #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI |
a13b0404 | 67 | |
cc2d3216 MZ |
68 | /* |
69 | * Collection structure - just an ID, and a redistributor address to | |
70 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
71 | * CPU. | |
72 | */ | |
73 | struct its_collection { | |
74 | u64 target_address; | |
75 | u16 col_id; | |
76 | }; | |
77 | ||
466b7d16 | 78 | /* |
9347359a SD |
79 | * The ITS_BASER structure - contains memory information, cached |
80 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
81 | */ |
82 | struct its_baser { | |
83 | void *base; | |
84 | u64 val; | |
85 | u32 order; | |
9347359a | 86 | u32 psz; |
466b7d16 SD |
87 | }; |
88 | ||
558b0165 AB |
89 | struct its_device; |
90 | ||
cc2d3216 MZ |
91 | /* |
92 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
93 | * top-level MSI domain, the command queue, the collections, and the |
94 | * list of devices writing to it. | |
9791ec7d MZ |
95 | * |
96 | * dev_alloc_lock has to be taken for device allocations, while the | |
97 | * spinlock must be taken to parse data structures such as the device | |
98 | * list. | |
cc2d3216 MZ |
99 | */ |
100 | struct its_node { | |
101 | raw_spinlock_t lock; | |
9791ec7d | 102 | struct mutex dev_alloc_lock; |
cc2d3216 | 103 | struct list_head entry; |
cc2d3216 | 104 | void __iomem *base; |
5e46a484 | 105 | void __iomem *sgir_base; |
db40f0a7 | 106 | phys_addr_t phys_base; |
cc2d3216 MZ |
107 | struct its_cmd_block *cmd_base; |
108 | struct its_cmd_block *cmd_write; | |
466b7d16 | 109 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 110 | struct its_collection *collections; |
558b0165 AB |
111 | struct fwnode_handle *fwnode_handle; |
112 | u64 (*get_msi_base)(struct its_device *its_dev); | |
0dd57fed | 113 | u64 typer; |
dba0bc7b DB |
114 | u64 cbaser_save; |
115 | u32 ctlr_save; | |
5e516846 | 116 | u32 mpidr; |
cc2d3216 MZ |
117 | struct list_head its_device_list; |
118 | u64 flags; | |
debf6d02 | 119 | unsigned long list_nr; |
fbf8f40e | 120 | int numa_node; |
558b0165 AB |
121 | unsigned int msi_domain_flags; |
122 | u32 pre_its_base; /* for Socionext Synquacer */ | |
5c9a882e | 123 | int vlpi_redist_offset; |
cc2d3216 MZ |
124 | }; |
125 | ||
0dd57fed | 126 | #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) |
5e516846 | 127 | #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) |
576a8342 | 128 | #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) |
0dd57fed | 129 | |
cc2d3216 MZ |
130 | #define ITS_ITT_ALIGN SZ_256 |
131 | ||
32bd44dc | 132 | /* The maximum number of VPEID bits supported by VLPI commands */ |
f2d83409 MZ |
133 | #define ITS_MAX_VPEID_BITS \ |
134 | ({ \ | |
135 | int nvpeid = 16; \ | |
136 | if (gic_rdists->has_rvpeid && \ | |
137 | gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ | |
138 | nvpeid = 1 + (gic_rdists->gicd_typer2 & \ | |
139 | GICD_TYPER2_VID); \ | |
140 | \ | |
141 | nvpeid; \ | |
142 | }) | |
32bd44dc SD |
143 | #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS)) |
144 | ||
2eca0d6c SD |
145 | /* Convert page order to size in bytes */ |
146 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
147 | ||
591e5bec MZ |
148 | struct event_lpi_map { |
149 | unsigned long *lpi_map; | |
150 | u16 *col_map; | |
151 | irq_hw_number_t lpi_base; | |
152 | int nr_lpis; | |
11635fa2 | 153 | raw_spinlock_t vlpi_lock; |
d011e4e6 MZ |
154 | struct its_vm *vm; |
155 | struct its_vlpi_map *vlpi_maps; | |
156 | int nr_vlpis; | |
591e5bec MZ |
157 | }; |
158 | ||
cc2d3216 | 159 | /* |
d011e4e6 MZ |
160 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
161 | * translation table, and a list of interrupts. If it some of its | |
162 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
163 | * indicates which one. | |
cc2d3216 MZ |
164 | */ |
165 | struct its_device { | |
166 | struct list_head entry; | |
167 | struct its_node *its; | |
591e5bec | 168 | struct event_lpi_map event_map; |
cc2d3216 | 169 | void *itt; |
cc2d3216 MZ |
170 | u32 nr_ites; |
171 | u32 device_id; | |
9791ec7d | 172 | bool shared; |
cc2d3216 MZ |
173 | }; |
174 | ||
20b3d54e MZ |
175 | static struct { |
176 | raw_spinlock_t lock; | |
177 | struct its_device *dev; | |
178 | struct its_vpe **vpes; | |
179 | int next_victim; | |
180 | } vpe_proxy; | |
181 | ||
2f13ff1d MZ |
182 | struct cpu_lpi_count { |
183 | atomic_t managed; | |
184 | atomic_t unmanaged; | |
185 | }; | |
186 | ||
187 | static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count); | |
188 | ||
1ac19ca6 | 189 | static LIST_HEAD(its_nodes); |
a8db7456 | 190 | static DEFINE_RAW_SPINLOCK(its_lock); |
1ac19ca6 | 191 | static struct rdists *gic_rdists; |
db40f0a7 | 192 | static struct irq_domain *its_parent; |
1ac19ca6 | 193 | |
3dfa576b | 194 | static unsigned long its_list_map; |
3171a47a MZ |
195 | static u16 vmovp_seq_num; |
196 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
197 | ||
7d75bbb4 | 198 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 199 | |
1ac19ca6 | 200 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
11e37d35 | 201 | #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu)) |
1ac19ca6 | 202 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) |
e643d803 | 203 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 204 | |
009384b3 MZ |
205 | /* |
206 | * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we | |
207 | * always have vSGIs mapped. | |
208 | */ | |
209 | static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) | |
210 | { | |
211 | return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); | |
212 | } | |
213 | ||
84243125 ZY |
214 | static u16 get_its_list(struct its_vm *vm) |
215 | { | |
216 | struct its_node *its; | |
217 | unsigned long its_list = 0; | |
218 | ||
219 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 220 | if (!is_v4(its)) |
84243125 ZY |
221 | continue; |
222 | ||
009384b3 | 223 | if (require_its_list_vmovp(vm, its)) |
84243125 ZY |
224 | __set_bit(its->list_nr, &its_list); |
225 | } | |
226 | ||
227 | return (u16)its_list; | |
228 | } | |
229 | ||
425c09be MZ |
230 | static inline u32 its_get_event_id(struct irq_data *d) |
231 | { | |
232 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
233 | return d->hwirq - its_dev->event_map.lpi_base; | |
234 | } | |
235 | ||
591e5bec MZ |
236 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
237 | u32 event) | |
238 | { | |
239 | struct its_node *its = its_dev->its; | |
240 | ||
241 | return its->collections + its_dev->event_map.col_map[event]; | |
242 | } | |
243 | ||
c1d4d5cd MZ |
244 | static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev, |
245 | u32 event) | |
246 | { | |
247 | if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) | |
248 | return NULL; | |
249 | ||
250 | return &its_dev->event_map.vlpi_maps[event]; | |
251 | } | |
252 | ||
f4a81f5a MZ |
253 | static struct its_vlpi_map *get_vlpi_map(struct irq_data *d) |
254 | { | |
255 | if (irqd_is_forwarded_to_vcpu(d)) { | |
256 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
257 | u32 event = its_get_event_id(d); | |
258 | ||
259 | return dev_event_to_vlpi_map(its_dev, event); | |
260 | } | |
261 | ||
262 | return NULL; | |
263 | } | |
264 | ||
f3a05921 MZ |
265 | static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags) |
266 | { | |
267 | raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); | |
268 | return vpe->col_idx; | |
269 | } | |
270 | ||
271 | static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags) | |
272 | { | |
273 | raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); | |
274 | } | |
275 | ||
276 | static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags) | |
425c09be | 277 | { |
f4a81f5a | 278 | struct its_vlpi_map *map = get_vlpi_map(d); |
f3a05921 | 279 | int cpu; |
f4a81f5a | 280 | |
f3a05921 MZ |
281 | if (map) { |
282 | cpu = vpe_to_cpuid_lock(map->vpe, flags); | |
283 | } else { | |
284 | /* Physical LPIs are already locked via the irq_desc lock */ | |
285 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
286 | cpu = its_dev->event_map.col_map[its_get_event_id(d)]; | |
287 | /* Keep GCC quiet... */ | |
288 | *flags = 0; | |
289 | } | |
425c09be | 290 | |
f3a05921 MZ |
291 | return cpu; |
292 | } | |
293 | ||
294 | static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags) | |
425c09be | 295 | { |
f4a81f5a MZ |
296 | struct its_vlpi_map *map = get_vlpi_map(d); |
297 | ||
298 | if (map) | |
f3a05921 | 299 | vpe_to_cpuid_unlock(map->vpe, flags); |
425c09be MZ |
300 | } |
301 | ||
83559b47 MZ |
302 | static struct its_collection *valid_col(struct its_collection *col) |
303 | { | |
20faba84 | 304 | if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) |
83559b47 MZ |
305 | return NULL; |
306 | ||
307 | return col; | |
308 | } | |
309 | ||
205e065d MZ |
310 | static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) |
311 | { | |
312 | if (valid_col(its->collections + vpe->col_idx)) | |
313 | return vpe; | |
314 | ||
315 | return NULL; | |
316 | } | |
317 | ||
cc2d3216 MZ |
318 | /* |
319 | * ITS command descriptors - parameters to be encoded in a command | |
320 | * block. | |
321 | */ | |
322 | struct its_cmd_desc { | |
323 | union { | |
324 | struct { | |
325 | struct its_device *dev; | |
326 | u32 event_id; | |
327 | } its_inv_cmd; | |
328 | ||
8d85dced MZ |
329 | struct { |
330 | struct its_device *dev; | |
331 | u32 event_id; | |
332 | } its_clear_cmd; | |
333 | ||
cc2d3216 MZ |
334 | struct { |
335 | struct its_device *dev; | |
336 | u32 event_id; | |
337 | } its_int_cmd; | |
338 | ||
339 | struct { | |
340 | struct its_device *dev; | |
341 | int valid; | |
342 | } its_mapd_cmd; | |
343 | ||
344 | struct { | |
345 | struct its_collection *col; | |
346 | int valid; | |
347 | } its_mapc_cmd; | |
348 | ||
349 | struct { | |
350 | struct its_device *dev; | |
351 | u32 phys_id; | |
352 | u32 event_id; | |
6a25ad3a | 353 | } its_mapti_cmd; |
cc2d3216 MZ |
354 | |
355 | struct { | |
356 | struct its_device *dev; | |
357 | struct its_collection *col; | |
591e5bec | 358 | u32 event_id; |
cc2d3216 MZ |
359 | } its_movi_cmd; |
360 | ||
361 | struct { | |
362 | struct its_device *dev; | |
363 | u32 event_id; | |
364 | } its_discard_cmd; | |
365 | ||
366 | struct { | |
367 | struct its_collection *col; | |
368 | } its_invall_cmd; | |
d011e4e6 | 369 | |
eb78192b MZ |
370 | struct { |
371 | struct its_vpe *vpe; | |
372 | } its_vinvall_cmd; | |
373 | ||
374 | struct { | |
375 | struct its_vpe *vpe; | |
376 | struct its_collection *col; | |
377 | bool valid; | |
378 | } its_vmapp_cmd; | |
379 | ||
d011e4e6 MZ |
380 | struct { |
381 | struct its_vpe *vpe; | |
382 | struct its_device *dev; | |
383 | u32 virt_id; | |
384 | u32 event_id; | |
385 | bool db_enabled; | |
386 | } its_vmapti_cmd; | |
387 | ||
388 | struct { | |
389 | struct its_vpe *vpe; | |
390 | struct its_device *dev; | |
391 | u32 event_id; | |
392 | bool db_enabled; | |
393 | } its_vmovi_cmd; | |
3171a47a MZ |
394 | |
395 | struct { | |
396 | struct its_vpe *vpe; | |
397 | struct its_collection *col; | |
398 | u16 seq_num; | |
399 | u16 its_list; | |
400 | } its_vmovp_cmd; | |
d97c97ba MZ |
401 | |
402 | struct { | |
403 | struct its_vpe *vpe; | |
404 | } its_invdb_cmd; | |
e252cf8a MZ |
405 | |
406 | struct { | |
407 | struct its_vpe *vpe; | |
408 | u8 sgi; | |
409 | u8 priority; | |
410 | bool enable; | |
411 | bool group; | |
412 | bool clear; | |
413 | } its_vsgi_cmd; | |
cc2d3216 MZ |
414 | }; |
415 | }; | |
416 | ||
417 | /* | |
418 | * The ITS command block, which is what the ITS actually parses. | |
419 | */ | |
420 | struct its_cmd_block { | |
2bbdfcc5 BDC |
421 | union { |
422 | u64 raw_cmd[4]; | |
423 | __le64 raw_cmd_le[4]; | |
424 | }; | |
cc2d3216 MZ |
425 | }; |
426 | ||
427 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
428 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
429 | ||
67047f90 MZ |
430 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *, |
431 | struct its_cmd_block *, | |
cc2d3216 MZ |
432 | struct its_cmd_desc *); |
433 | ||
67047f90 MZ |
434 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *, |
435 | struct its_cmd_block *, | |
d011e4e6 MZ |
436 | struct its_cmd_desc *); |
437 | ||
4d36f136 MZ |
438 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
439 | { | |
440 | u64 mask = GENMASK_ULL(h, l); | |
441 | *raw_cmd &= ~mask; | |
442 | *raw_cmd |= (val << l) & mask; | |
443 | } | |
444 | ||
cc2d3216 MZ |
445 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
446 | { | |
4d36f136 | 447 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
448 | } |
449 | ||
450 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
451 | { | |
4d36f136 | 452 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
453 | } |
454 | ||
455 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
456 | { | |
4d36f136 | 457 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
458 | } |
459 | ||
460 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
461 | { | |
4d36f136 | 462 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
463 | } |
464 | ||
465 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
466 | { | |
4d36f136 | 467 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
468 | } |
469 | ||
470 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
471 | { | |
30ae9610 | 472 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); |
cc2d3216 MZ |
473 | } |
474 | ||
475 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
476 | { | |
4d36f136 | 477 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
478 | } |
479 | ||
480 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
481 | { | |
30ae9610 | 482 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); |
cc2d3216 MZ |
483 | } |
484 | ||
485 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
486 | { | |
4d36f136 | 487 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
488 | } |
489 | ||
d011e4e6 MZ |
490 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
491 | { | |
492 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
493 | } | |
494 | ||
495 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
496 | { | |
497 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
498 | } | |
499 | ||
500 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
501 | { | |
502 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
503 | } | |
504 | ||
505 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
506 | { | |
507 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
508 | } | |
509 | ||
3171a47a MZ |
510 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
511 | { | |
512 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
513 | } | |
514 | ||
515 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
516 | { | |
517 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
518 | } | |
519 | ||
eb78192b MZ |
520 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
521 | { | |
30ae9610 | 522 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); |
eb78192b MZ |
523 | } |
524 | ||
525 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
526 | { | |
527 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
528 | } | |
529 | ||
64edfaa9 MZ |
530 | static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa) |
531 | { | |
532 | its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); | |
533 | } | |
534 | ||
535 | static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc) | |
536 | { | |
537 | its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); | |
538 | } | |
539 | ||
540 | static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz) | |
541 | { | |
542 | its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); | |
543 | } | |
544 | ||
545 | static void its_encode_vmapp_default_db(struct its_cmd_block *cmd, | |
546 | u32 vpe_db_lpi) | |
547 | { | |
548 | its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); | |
549 | } | |
550 | ||
dd3f050a MZ |
551 | static void its_encode_vmovp_default_db(struct its_cmd_block *cmd, |
552 | u32 vpe_db_lpi) | |
553 | { | |
554 | its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); | |
555 | } | |
556 | ||
557 | static void its_encode_db(struct its_cmd_block *cmd, bool db) | |
558 | { | |
559 | its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); | |
560 | } | |
561 | ||
e252cf8a MZ |
562 | static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi) |
563 | { | |
564 | its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); | |
565 | } | |
566 | ||
567 | static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio) | |
568 | { | |
569 | its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); | |
570 | } | |
571 | ||
572 | static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp) | |
573 | { | |
574 | its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); | |
575 | } | |
576 | ||
577 | static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr) | |
578 | { | |
579 | its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); | |
580 | } | |
581 | ||
582 | static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en) | |
583 | { | |
584 | its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); | |
585 | } | |
586 | ||
cc2d3216 MZ |
587 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
588 | { | |
589 | /* Let's fixup BE commands */ | |
2bbdfcc5 BDC |
590 | cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); |
591 | cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
592 | cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
593 | cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
cc2d3216 MZ |
594 | } |
595 | ||
67047f90 MZ |
596 | static struct its_collection *its_build_mapd_cmd(struct its_node *its, |
597 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
598 | struct its_cmd_desc *desc) |
599 | { | |
600 | unsigned long itt_addr; | |
c8481267 | 601 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
602 | |
603 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
604 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
605 | ||
606 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
607 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
608 | its_encode_size(cmd, size - 1); | |
609 | its_encode_itt(cmd, itt_addr); | |
610 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
611 | ||
612 | its_fixup_cmd(cmd); | |
613 | ||
591e5bec | 614 | return NULL; |
cc2d3216 MZ |
615 | } |
616 | ||
67047f90 MZ |
617 | static struct its_collection *its_build_mapc_cmd(struct its_node *its, |
618 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
619 | struct its_cmd_desc *desc) |
620 | { | |
621 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
622 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
623 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
624 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
625 | ||
626 | its_fixup_cmd(cmd); | |
627 | ||
628 | return desc->its_mapc_cmd.col; | |
629 | } | |
630 | ||
67047f90 MZ |
631 | static struct its_collection *its_build_mapti_cmd(struct its_node *its, |
632 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
633 | struct its_cmd_desc *desc) |
634 | { | |
591e5bec MZ |
635 | struct its_collection *col; |
636 | ||
6a25ad3a MZ |
637 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
638 | desc->its_mapti_cmd.event_id); | |
591e5bec | 639 | |
6a25ad3a MZ |
640 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
641 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
642 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
643 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 644 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
645 | |
646 | its_fixup_cmd(cmd); | |
647 | ||
83559b47 | 648 | return valid_col(col); |
cc2d3216 MZ |
649 | } |
650 | ||
67047f90 MZ |
651 | static struct its_collection *its_build_movi_cmd(struct its_node *its, |
652 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
653 | struct its_cmd_desc *desc) |
654 | { | |
591e5bec MZ |
655 | struct its_collection *col; |
656 | ||
657 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
658 | desc->its_movi_cmd.event_id); | |
659 | ||
cc2d3216 MZ |
660 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
661 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 662 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
663 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
664 | ||
665 | its_fixup_cmd(cmd); | |
666 | ||
83559b47 | 667 | return valid_col(col); |
cc2d3216 MZ |
668 | } |
669 | ||
67047f90 MZ |
670 | static struct its_collection *its_build_discard_cmd(struct its_node *its, |
671 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
672 | struct its_cmd_desc *desc) |
673 | { | |
591e5bec MZ |
674 | struct its_collection *col; |
675 | ||
676 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
677 | desc->its_discard_cmd.event_id); | |
678 | ||
cc2d3216 MZ |
679 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
680 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
681 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
682 | ||
683 | its_fixup_cmd(cmd); | |
684 | ||
83559b47 | 685 | return valid_col(col); |
cc2d3216 MZ |
686 | } |
687 | ||
67047f90 MZ |
688 | static struct its_collection *its_build_inv_cmd(struct its_node *its, |
689 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
690 | struct its_cmd_desc *desc) |
691 | { | |
591e5bec MZ |
692 | struct its_collection *col; |
693 | ||
694 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
695 | desc->its_inv_cmd.event_id); | |
696 | ||
cc2d3216 MZ |
697 | its_encode_cmd(cmd, GITS_CMD_INV); |
698 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
699 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
700 | ||
701 | its_fixup_cmd(cmd); | |
702 | ||
83559b47 | 703 | return valid_col(col); |
cc2d3216 MZ |
704 | } |
705 | ||
67047f90 MZ |
706 | static struct its_collection *its_build_int_cmd(struct its_node *its, |
707 | struct its_cmd_block *cmd, | |
8d85dced MZ |
708 | struct its_cmd_desc *desc) |
709 | { | |
710 | struct its_collection *col; | |
711 | ||
712 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
713 | desc->its_int_cmd.event_id); | |
714 | ||
715 | its_encode_cmd(cmd, GITS_CMD_INT); | |
716 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
717 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
718 | ||
719 | its_fixup_cmd(cmd); | |
720 | ||
83559b47 | 721 | return valid_col(col); |
8d85dced MZ |
722 | } |
723 | ||
67047f90 MZ |
724 | static struct its_collection *its_build_clear_cmd(struct its_node *its, |
725 | struct its_cmd_block *cmd, | |
8d85dced MZ |
726 | struct its_cmd_desc *desc) |
727 | { | |
728 | struct its_collection *col; | |
729 | ||
730 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
731 | desc->its_clear_cmd.event_id); | |
732 | ||
733 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
734 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
735 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
736 | ||
737 | its_fixup_cmd(cmd); | |
738 | ||
83559b47 | 739 | return valid_col(col); |
8d85dced MZ |
740 | } |
741 | ||
67047f90 MZ |
742 | static struct its_collection *its_build_invall_cmd(struct its_node *its, |
743 | struct its_cmd_block *cmd, | |
cc2d3216 MZ |
744 | struct its_cmd_desc *desc) |
745 | { | |
746 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
10794522 | 747 | its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); |
cc2d3216 MZ |
748 | |
749 | its_fixup_cmd(cmd); | |
750 | ||
b383a42c | 751 | return desc->its_invall_cmd.col; |
cc2d3216 MZ |
752 | } |
753 | ||
67047f90 MZ |
754 | static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, |
755 | struct its_cmd_block *cmd, | |
eb78192b MZ |
756 | struct its_cmd_desc *desc) |
757 | { | |
758 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
759 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
760 | ||
761 | its_fixup_cmd(cmd); | |
762 | ||
205e065d | 763 | return valid_vpe(its, desc->its_vinvall_cmd.vpe); |
eb78192b MZ |
764 | } |
765 | ||
67047f90 MZ |
766 | static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, |
767 | struct its_cmd_block *cmd, | |
eb78192b MZ |
768 | struct its_cmd_desc *desc) |
769 | { | |
64edfaa9 | 770 | unsigned long vpt_addr, vconf_addr; |
5c9a882e | 771 | u64 target; |
64edfaa9 | 772 | bool alloc; |
eb78192b MZ |
773 | |
774 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
775 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
776 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
64edfaa9 MZ |
777 | |
778 | if (!desc->its_vmapp_cmd.valid) { | |
779 | if (is_v4_1(its)) { | |
780 | alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); | |
781 | its_encode_alloc(cmd, alloc); | |
782 | } | |
783 | ||
784 | goto out; | |
785 | } | |
786 | ||
787 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
788 | target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; | |
789 | ||
5c9a882e | 790 | its_encode_target(cmd, target); |
eb78192b MZ |
791 | its_encode_vpt_addr(cmd, vpt_addr); |
792 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
793 | ||
64edfaa9 MZ |
794 | if (!is_v4_1(its)) |
795 | goto out; | |
796 | ||
797 | vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); | |
798 | ||
799 | alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); | |
800 | ||
801 | its_encode_alloc(cmd, alloc); | |
802 | ||
c21bc068 SL |
803 | /* |
804 | * GICv4.1 provides a way to get the VLPI state, which needs the vPE | |
805 | * to be unmapped first, and in this case, we may remap the vPE | |
806 | * back while the VPT is not empty. So we can't assume that the | |
807 | * VPT is empty on map. This is why we never advertise PTZ. | |
808 | */ | |
809 | its_encode_ptz(cmd, false); | |
64edfaa9 MZ |
810 | its_encode_vconf_addr(cmd, vconf_addr); |
811 | its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); | |
812 | ||
813 | out: | |
eb78192b MZ |
814 | its_fixup_cmd(cmd); |
815 | ||
205e065d | 816 | return valid_vpe(its, desc->its_vmapp_cmd.vpe); |
eb78192b MZ |
817 | } |
818 | ||
67047f90 MZ |
819 | static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, |
820 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
821 | struct its_cmd_desc *desc) |
822 | { | |
823 | u32 db; | |
824 | ||
3858d4df | 825 | if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) |
d011e4e6 MZ |
826 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; |
827 | else | |
828 | db = 1023; | |
829 | ||
830 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
831 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
832 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
833 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
834 | its_encode_db_phys_id(cmd, db); | |
835 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
836 | ||
837 | its_fixup_cmd(cmd); | |
838 | ||
205e065d | 839 | return valid_vpe(its, desc->its_vmapti_cmd.vpe); |
d011e4e6 MZ |
840 | } |
841 | ||
67047f90 MZ |
842 | static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, |
843 | struct its_cmd_block *cmd, | |
d011e4e6 MZ |
844 | struct its_cmd_desc *desc) |
845 | { | |
846 | u32 db; | |
847 | ||
3858d4df | 848 | if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) |
d011e4e6 MZ |
849 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; |
850 | else | |
851 | db = 1023; | |
852 | ||
853 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
854 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
855 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
856 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
857 | its_encode_db_phys_id(cmd, db); | |
858 | its_encode_db_valid(cmd, true); | |
859 | ||
860 | its_fixup_cmd(cmd); | |
861 | ||
205e065d | 862 | return valid_vpe(its, desc->its_vmovi_cmd.vpe); |
d011e4e6 MZ |
863 | } |
864 | ||
67047f90 MZ |
865 | static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, |
866 | struct its_cmd_block *cmd, | |
3171a47a MZ |
867 | struct its_cmd_desc *desc) |
868 | { | |
5c9a882e MZ |
869 | u64 target; |
870 | ||
871 | target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; | |
3171a47a MZ |
872 | its_encode_cmd(cmd, GITS_CMD_VMOVP); |
873 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
874 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
875 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
5c9a882e | 876 | its_encode_target(cmd, target); |
3171a47a | 877 | |
dd3f050a MZ |
878 | if (is_v4_1(its)) { |
879 | its_encode_db(cmd, true); | |
880 | its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); | |
881 | } | |
882 | ||
3171a47a MZ |
883 | its_fixup_cmd(cmd); |
884 | ||
205e065d | 885 | return valid_vpe(its, desc->its_vmovp_cmd.vpe); |
3171a47a MZ |
886 | } |
887 | ||
28614696 MZ |
888 | static struct its_vpe *its_build_vinv_cmd(struct its_node *its, |
889 | struct its_cmd_block *cmd, | |
890 | struct its_cmd_desc *desc) | |
891 | { | |
892 | struct its_vlpi_map *map; | |
893 | ||
894 | map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, | |
895 | desc->its_inv_cmd.event_id); | |
896 | ||
897 | its_encode_cmd(cmd, GITS_CMD_INV); | |
898 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
899 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
900 | ||
901 | its_fixup_cmd(cmd); | |
902 | ||
903 | return valid_vpe(its, map->vpe); | |
904 | } | |
905 | ||
ed0e4aa9 MZ |
906 | static struct its_vpe *its_build_vint_cmd(struct its_node *its, |
907 | struct its_cmd_block *cmd, | |
908 | struct its_cmd_desc *desc) | |
909 | { | |
910 | struct its_vlpi_map *map; | |
911 | ||
912 | map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, | |
913 | desc->its_int_cmd.event_id); | |
914 | ||
915 | its_encode_cmd(cmd, GITS_CMD_INT); | |
916 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
917 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
918 | ||
919 | its_fixup_cmd(cmd); | |
920 | ||
921 | return valid_vpe(its, map->vpe); | |
922 | } | |
923 | ||
924 | static struct its_vpe *its_build_vclear_cmd(struct its_node *its, | |
925 | struct its_cmd_block *cmd, | |
926 | struct its_cmd_desc *desc) | |
927 | { | |
928 | struct its_vlpi_map *map; | |
929 | ||
930 | map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, | |
931 | desc->its_clear_cmd.event_id); | |
932 | ||
933 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
934 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
935 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
936 | ||
937 | its_fixup_cmd(cmd); | |
938 | ||
939 | return valid_vpe(its, map->vpe); | |
940 | } | |
941 | ||
d97c97ba MZ |
942 | static struct its_vpe *its_build_invdb_cmd(struct its_node *its, |
943 | struct its_cmd_block *cmd, | |
944 | struct its_cmd_desc *desc) | |
945 | { | |
946 | if (WARN_ON(!is_v4_1(its))) | |
947 | return NULL; | |
948 | ||
949 | its_encode_cmd(cmd, GITS_CMD_INVDB); | |
950 | its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); | |
951 | ||
952 | its_fixup_cmd(cmd); | |
953 | ||
954 | return valid_vpe(its, desc->its_invdb_cmd.vpe); | |
955 | } | |
956 | ||
e252cf8a MZ |
957 | static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, |
958 | struct its_cmd_block *cmd, | |
959 | struct its_cmd_desc *desc) | |
960 | { | |
961 | if (WARN_ON(!is_v4_1(its))) | |
962 | return NULL; | |
963 | ||
964 | its_encode_cmd(cmd, GITS_CMD_VSGI); | |
965 | its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); | |
966 | its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); | |
967 | its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); | |
968 | its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); | |
969 | its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); | |
970 | its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); | |
971 | ||
972 | its_fixup_cmd(cmd); | |
973 | ||
974 | return valid_vpe(its, desc->its_vsgi_cmd.vpe); | |
975 | } | |
976 | ||
cc2d3216 MZ |
977 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
978 | struct its_cmd_block *ptr) | |
979 | { | |
980 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
981 | } | |
982 | ||
983 | static int its_queue_full(struct its_node *its) | |
984 | { | |
985 | int widx; | |
986 | int ridx; | |
987 | ||
988 | widx = its->cmd_write - its->cmd_base; | |
989 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
990 | ||
991 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
992 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
993 | return 1; | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
999 | { | |
1000 | struct its_cmd_block *cmd; | |
1001 | u32 count = 1000000; /* 1s! */ | |
1002 | ||
1003 | while (its_queue_full(its)) { | |
1004 | count--; | |
1005 | if (!count) { | |
1006 | pr_err_ratelimited("ITS queue not draining\n"); | |
1007 | return NULL; | |
1008 | } | |
1009 | cpu_relax(); | |
1010 | udelay(1); | |
1011 | } | |
1012 | ||
1013 | cmd = its->cmd_write++; | |
1014 | ||
1015 | /* Handle queue wrapping */ | |
1016 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
1017 | its->cmd_write = its->cmd_base; | |
1018 | ||
34d677a9 MZ |
1019 | /* Clear command */ |
1020 | cmd->raw_cmd[0] = 0; | |
1021 | cmd->raw_cmd[1] = 0; | |
1022 | cmd->raw_cmd[2] = 0; | |
1023 | cmd->raw_cmd[3] = 0; | |
1024 | ||
cc2d3216 MZ |
1025 | return cmd; |
1026 | } | |
1027 | ||
1028 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
1029 | { | |
1030 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
1031 | ||
1032 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
1033 | ||
1034 | return its->cmd_write; | |
1035 | } | |
1036 | ||
1037 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
1038 | { | |
1039 | /* | |
1040 | * Make sure the commands written to memory are observable by | |
1041 | * the ITS. | |
1042 | */ | |
1043 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 1044 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
1045 | else |
1046 | dsb(ishst); | |
1047 | } | |
1048 | ||
a19b462f | 1049 | static int its_wait_for_range_completion(struct its_node *its, |
a050fa54 | 1050 | u64 prev_idx, |
a19b462f | 1051 | struct its_cmd_block *to) |
cc2d3216 | 1052 | { |
a050fa54 | 1053 | u64 rd_idx, to_idx, linear_idx; |
cc2d3216 MZ |
1054 | u32 count = 1000000; /* 1s! */ |
1055 | ||
a050fa54 | 1056 | /* Linearize to_idx if the command set has wrapped around */ |
cc2d3216 | 1057 | to_idx = its_cmd_ptr_to_offset(its, to); |
a050fa54 HG |
1058 | if (to_idx < prev_idx) |
1059 | to_idx += ITS_CMD_QUEUE_SZ; | |
1060 | ||
1061 | linear_idx = prev_idx; | |
cc2d3216 MZ |
1062 | |
1063 | while (1) { | |
a050fa54 HG |
1064 | s64 delta; |
1065 | ||
cc2d3216 | 1066 | rd_idx = readl_relaxed(its->base + GITS_CREADR); |
9bdd8b1c | 1067 | |
a050fa54 HG |
1068 | /* |
1069 | * Compute the read pointer progress, taking the | |
1070 | * potential wrap-around into account. | |
1071 | */ | |
1072 | delta = rd_idx - prev_idx; | |
1073 | if (rd_idx < prev_idx) | |
1074 | delta += ITS_CMD_QUEUE_SZ; | |
9bdd8b1c | 1075 | |
a050fa54 HG |
1076 | linear_idx += delta; |
1077 | if (linear_idx >= to_idx) | |
cc2d3216 MZ |
1078 | break; |
1079 | ||
1080 | count--; | |
1081 | if (!count) { | |
a050fa54 HG |
1082 | pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", |
1083 | to_idx, linear_idx); | |
a19b462f | 1084 | return -1; |
cc2d3216 | 1085 | } |
a050fa54 | 1086 | prev_idx = rd_idx; |
cc2d3216 MZ |
1087 | cpu_relax(); |
1088 | udelay(1); | |
1089 | } | |
a19b462f MZ |
1090 | |
1091 | return 0; | |
cc2d3216 MZ |
1092 | } |
1093 | ||
e4f9094b MZ |
1094 | /* Warning, macro hell follows */ |
1095 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
1096 | void name(struct its_node *its, \ | |
1097 | buildtype builder, \ | |
1098 | struct its_cmd_desc *desc) \ | |
1099 | { \ | |
1100 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
1101 | synctype *sync_obj; \ | |
1102 | unsigned long flags; \ | |
a050fa54 | 1103 | u64 rd_idx; \ |
e4f9094b MZ |
1104 | \ |
1105 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
1106 | \ | |
1107 | cmd = its_allocate_entry(its); \ | |
1108 | if (!cmd) { /* We're soooooo screewed... */ \ | |
1109 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
1110 | return; \ | |
1111 | } \ | |
67047f90 | 1112 | sync_obj = builder(its, cmd, desc); \ |
e4f9094b MZ |
1113 | its_flush_cmd(its, cmd); \ |
1114 | \ | |
1115 | if (sync_obj) { \ | |
1116 | sync_cmd = its_allocate_entry(its); \ | |
1117 | if (!sync_cmd) \ | |
1118 | goto post; \ | |
1119 | \ | |
67047f90 | 1120 | buildfn(its, sync_cmd, sync_obj); \ |
e4f9094b MZ |
1121 | its_flush_cmd(its, sync_cmd); \ |
1122 | } \ | |
1123 | \ | |
1124 | post: \ | |
a050fa54 | 1125 | rd_idx = readl_relaxed(its->base + GITS_CREADR); \ |
e4f9094b MZ |
1126 | next_cmd = its_post_commands(its); \ |
1127 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
1128 | \ | |
a050fa54 | 1129 | if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \ |
a19b462f | 1130 | pr_err_ratelimited("ITS cmd %ps failed\n", builder); \ |
e4f9094b | 1131 | } |
cc2d3216 | 1132 | |
67047f90 MZ |
1133 | static void its_build_sync_cmd(struct its_node *its, |
1134 | struct its_cmd_block *sync_cmd, | |
e4f9094b MZ |
1135 | struct its_collection *sync_col) |
1136 | { | |
1137 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
1138 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 1139 | |
e4f9094b | 1140 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
1141 | } |
1142 | ||
e4f9094b MZ |
1143 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
1144 | struct its_collection, its_build_sync_cmd) | |
1145 | ||
67047f90 MZ |
1146 | static void its_build_vsync_cmd(struct its_node *its, |
1147 | struct its_cmd_block *sync_cmd, | |
d011e4e6 MZ |
1148 | struct its_vpe *sync_vpe) |
1149 | { | |
1150 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
1151 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
1152 | ||
1153 | its_fixup_cmd(sync_cmd); | |
1154 | } | |
1155 | ||
1156 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
1157 | struct its_vpe, its_build_vsync_cmd) | |
1158 | ||
8d85dced | 1159 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 1160 | { |
8d85dced | 1161 | struct its_cmd_desc desc; |
cc2d3216 | 1162 | |
8d85dced MZ |
1163 | desc.its_int_cmd.dev = dev; |
1164 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 1165 | |
8d85dced MZ |
1166 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
1167 | } | |
cc2d3216 | 1168 | |
8d85dced MZ |
1169 | static void its_send_clear(struct its_device *dev, u32 event_id) |
1170 | { | |
1171 | struct its_cmd_desc desc; | |
cc2d3216 | 1172 | |
8d85dced MZ |
1173 | desc.its_clear_cmd.dev = dev; |
1174 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 1175 | |
8d85dced | 1176 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
1177 | } |
1178 | ||
1179 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
1180 | { | |
1181 | struct its_cmd_desc desc; | |
1182 | ||
1183 | desc.its_inv_cmd.dev = dev; | |
1184 | desc.its_inv_cmd.event_id = event_id; | |
1185 | ||
1186 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
1187 | } | |
1188 | ||
1189 | static void its_send_mapd(struct its_device *dev, int valid) | |
1190 | { | |
1191 | struct its_cmd_desc desc; | |
1192 | ||
1193 | desc.its_mapd_cmd.dev = dev; | |
1194 | desc.its_mapd_cmd.valid = !!valid; | |
1195 | ||
1196 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
1197 | } | |
1198 | ||
1199 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
1200 | int valid) | |
1201 | { | |
1202 | struct its_cmd_desc desc; | |
1203 | ||
1204 | desc.its_mapc_cmd.col = col; | |
1205 | desc.its_mapc_cmd.valid = !!valid; | |
1206 | ||
1207 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
1208 | } | |
1209 | ||
6a25ad3a | 1210 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
1211 | { |
1212 | struct its_cmd_desc desc; | |
1213 | ||
6a25ad3a MZ |
1214 | desc.its_mapti_cmd.dev = dev; |
1215 | desc.its_mapti_cmd.phys_id = irq_id; | |
1216 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 1217 | |
6a25ad3a | 1218 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
1219 | } |
1220 | ||
1221 | static void its_send_movi(struct its_device *dev, | |
1222 | struct its_collection *col, u32 id) | |
1223 | { | |
1224 | struct its_cmd_desc desc; | |
1225 | ||
1226 | desc.its_movi_cmd.dev = dev; | |
1227 | desc.its_movi_cmd.col = col; | |
591e5bec | 1228 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
1229 | |
1230 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
1231 | } | |
1232 | ||
1233 | static void its_send_discard(struct its_device *dev, u32 id) | |
1234 | { | |
1235 | struct its_cmd_desc desc; | |
1236 | ||
1237 | desc.its_discard_cmd.dev = dev; | |
1238 | desc.its_discard_cmd.event_id = id; | |
1239 | ||
1240 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
1241 | } | |
1242 | ||
1243 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
1244 | { | |
1245 | struct its_cmd_desc desc; | |
1246 | ||
1247 | desc.its_invall_cmd.col = col; | |
1248 | ||
1249 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
1250 | } | |
c48ed51c | 1251 | |
d011e4e6 MZ |
1252 | static void its_send_vmapti(struct its_device *dev, u32 id) |
1253 | { | |
c1d4d5cd | 1254 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1255 | struct its_cmd_desc desc; |
1256 | ||
1257 | desc.its_vmapti_cmd.vpe = map->vpe; | |
1258 | desc.its_vmapti_cmd.dev = dev; | |
1259 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
1260 | desc.its_vmapti_cmd.event_id = id; | |
1261 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
1262 | ||
1263 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
1264 | } | |
1265 | ||
1266 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
1267 | { | |
c1d4d5cd | 1268 | struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id); |
d011e4e6 MZ |
1269 | struct its_cmd_desc desc; |
1270 | ||
1271 | desc.its_vmovi_cmd.vpe = map->vpe; | |
1272 | desc.its_vmovi_cmd.dev = dev; | |
1273 | desc.its_vmovi_cmd.event_id = id; | |
1274 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
1275 | ||
1276 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
1277 | } | |
1278 | ||
75fd951b MZ |
1279 | static void its_send_vmapp(struct its_node *its, |
1280 | struct its_vpe *vpe, bool valid) | |
eb78192b MZ |
1281 | { |
1282 | struct its_cmd_desc desc; | |
eb78192b MZ |
1283 | |
1284 | desc.its_vmapp_cmd.vpe = vpe; | |
1285 | desc.its_vmapp_cmd.valid = valid; | |
75fd951b | 1286 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; |
eb78192b | 1287 | |
75fd951b | 1288 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); |
eb78192b MZ |
1289 | } |
1290 | ||
3171a47a MZ |
1291 | static void its_send_vmovp(struct its_vpe *vpe) |
1292 | { | |
84243125 | 1293 | struct its_cmd_desc desc = {}; |
3171a47a MZ |
1294 | struct its_node *its; |
1295 | unsigned long flags; | |
1296 | int col_id = vpe->col_idx; | |
1297 | ||
1298 | desc.its_vmovp_cmd.vpe = vpe; | |
3171a47a MZ |
1299 | |
1300 | if (!its_list_map) { | |
1301 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
3171a47a MZ |
1302 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1303 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1304 | return; | |
1305 | } | |
1306 | ||
1307 | /* | |
1308 | * Yet another marvel of the architecture. If using the | |
1309 | * its_list "feature", we need to make sure that all ITSs | |
1310 | * receive all VMOVP commands in the same order. The only way | |
1311 | * to guarantee this is to make vmovp a serialization point. | |
1312 | * | |
1313 | * Wall <-- Head. | |
1314 | */ | |
1315 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1316 | ||
1317 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
84243125 | 1318 | desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); |
3171a47a MZ |
1319 | |
1320 | /* Emit VMOVPs */ | |
1321 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 1322 | if (!is_v4(its)) |
3171a47a MZ |
1323 | continue; |
1324 | ||
009384b3 | 1325 | if (!require_its_list_vmovp(vpe->its_vm, its)) |
2247e1bf MZ |
1326 | continue; |
1327 | ||
3171a47a MZ |
1328 | desc.its_vmovp_cmd.col = &its->collections[col_id]; |
1329 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
1330 | } | |
1331 | ||
1332 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1333 | } | |
1334 | ||
40619a2e | 1335 | static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) |
eb78192b MZ |
1336 | { |
1337 | struct its_cmd_desc desc; | |
eb78192b MZ |
1338 | |
1339 | desc.its_vinvall_cmd.vpe = vpe; | |
40619a2e | 1340 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); |
eb78192b MZ |
1341 | } |
1342 | ||
28614696 MZ |
1343 | static void its_send_vinv(struct its_device *dev, u32 event_id) |
1344 | { | |
1345 | struct its_cmd_desc desc; | |
1346 | ||
1347 | /* | |
1348 | * There is no real VINV command. This is just a normal INV, | |
1349 | * with a VSYNC instead of a SYNC. | |
1350 | */ | |
1351 | desc.its_inv_cmd.dev = dev; | |
1352 | desc.its_inv_cmd.event_id = event_id; | |
1353 | ||
1354 | its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); | |
1355 | } | |
1356 | ||
ed0e4aa9 MZ |
1357 | static void its_send_vint(struct its_device *dev, u32 event_id) |
1358 | { | |
1359 | struct its_cmd_desc desc; | |
1360 | ||
1361 | /* | |
1362 | * There is no real VINT command. This is just a normal INT, | |
1363 | * with a VSYNC instead of a SYNC. | |
1364 | */ | |
1365 | desc.its_int_cmd.dev = dev; | |
1366 | desc.its_int_cmd.event_id = event_id; | |
1367 | ||
1368 | its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); | |
1369 | } | |
1370 | ||
1371 | static void its_send_vclear(struct its_device *dev, u32 event_id) | |
1372 | { | |
1373 | struct its_cmd_desc desc; | |
1374 | ||
1375 | /* | |
1376 | * There is no real VCLEAR command. This is just a normal CLEAR, | |
1377 | * with a VSYNC instead of a SYNC. | |
1378 | */ | |
1379 | desc.its_clear_cmd.dev = dev; | |
1380 | desc.its_clear_cmd.event_id = event_id; | |
1381 | ||
1382 | its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); | |
1383 | } | |
1384 | ||
d97c97ba MZ |
1385 | static void its_send_invdb(struct its_node *its, struct its_vpe *vpe) |
1386 | { | |
1387 | struct its_cmd_desc desc; | |
1388 | ||
1389 | desc.its_invdb_cmd.vpe = vpe; | |
1390 | its_send_single_vcommand(its, its_build_invdb_cmd, &desc); | |
1391 | } | |
1392 | ||
c48ed51c MZ |
1393 | /* |
1394 | * irqchip functions - assumes MSI, mostly. | |
1395 | */ | |
015ec038 | 1396 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 1397 | { |
c1d4d5cd | 1398 | struct its_vlpi_map *map = get_vlpi_map(d); |
015ec038 | 1399 | irq_hw_number_t hwirq; |
e1a2e201 | 1400 | void *va; |
adcdb94e | 1401 | u8 *cfg; |
c48ed51c | 1402 | |
c1d4d5cd MZ |
1403 | if (map) { |
1404 | va = page_address(map->vm->vprop_page); | |
d4d7b4ad MZ |
1405 | hwirq = map->vintid; |
1406 | ||
1407 | /* Remember the updated property */ | |
1408 | map->properties &= ~clr; | |
1409 | map->properties |= set | LPI_PROP_GROUP1; | |
015ec038 | 1410 | } else { |
e1a2e201 | 1411 | va = gic_rdists->prop_table_va; |
015ec038 MZ |
1412 | hwirq = d->hwirq; |
1413 | } | |
adcdb94e | 1414 | |
e1a2e201 | 1415 | cfg = va + hwirq - 8192; |
adcdb94e | 1416 | *cfg &= ~clr; |
015ec038 | 1417 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1418 | |
1419 | /* | |
1420 | * Make the above write visible to the redistributors. | |
1421 | * And yes, we're flushing exactly: One. Single. Byte. | |
1422 | * Humpf... | |
1423 | */ | |
1424 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1425 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1426 | else |
1427 | dsb(ishst); | |
015ec038 MZ |
1428 | } |
1429 | ||
2f4f064b MZ |
1430 | static void wait_for_syncr(void __iomem *rdbase) |
1431 | { | |
04d80dbe | 1432 | while (readl_relaxed(rdbase + GICR_SYNCR) & 1) |
2f4f064b MZ |
1433 | cpu_relax(); |
1434 | } | |
1435 | ||
425c09be MZ |
1436 | static void direct_lpi_inv(struct irq_data *d) |
1437 | { | |
f4a81f5a | 1438 | struct its_vlpi_map *map = get_vlpi_map(d); |
425c09be | 1439 | void __iomem *rdbase; |
f3a05921 | 1440 | unsigned long flags; |
f4a81f5a | 1441 | u64 val; |
f3a05921 | 1442 | int cpu; |
f4a81f5a MZ |
1443 | |
1444 | if (map) { | |
1445 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1446 | ||
1447 | WARN_ON(!is_v4_1(its_dev->its)); | |
1448 | ||
1449 | val = GICR_INVLPIR_V; | |
1450 | val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); | |
1451 | val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); | |
1452 | } else { | |
1453 | val = d->hwirq; | |
1454 | } | |
425c09be MZ |
1455 | |
1456 | /* Target the redistributor this LPI is currently routed to */ | |
f3a05921 | 1457 | cpu = irq_to_cpuid_lock(d, &flags); |
9058a4e9 | 1458 | raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); |
f3a05921 | 1459 | rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; |
f4a81f5a | 1460 | gic_write_lpir(val, rdbase + GICR_INVLPIR); |
425c09be MZ |
1461 | |
1462 | wait_for_syncr(rdbase); | |
9058a4e9 | 1463 | raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); |
f3a05921 | 1464 | irq_to_cpuid_unlock(d, flags); |
425c09be MZ |
1465 | } |
1466 | ||
015ec038 MZ |
1467 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) |
1468 | { | |
1469 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1470 | ||
1471 | lpi_write_config(d, clr, set); | |
f4a81f5a MZ |
1472 | if (gic_rdists->has_direct_lpi && |
1473 | (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) | |
425c09be | 1474 | direct_lpi_inv(d); |
28614696 | 1475 | else if (!irqd_is_forwarded_to_vcpu(d)) |
425c09be | 1476 | its_send_inv(its_dev, its_get_event_id(d)); |
28614696 MZ |
1477 | else |
1478 | its_send_vinv(its_dev, its_get_event_id(d)); | |
c48ed51c MZ |
1479 | } |
1480 | ||
015ec038 MZ |
1481 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1482 | { | |
1483 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1484 | u32 event = its_get_event_id(d); | |
c1d4d5cd | 1485 | struct its_vlpi_map *map; |
015ec038 | 1486 | |
3858d4df MZ |
1487 | /* |
1488 | * GICv4.1 does away with the per-LPI nonsense, nothing to do | |
1489 | * here. | |
1490 | */ | |
1491 | if (is_v4_1(its_dev->its)) | |
1492 | return; | |
1493 | ||
c1d4d5cd MZ |
1494 | map = dev_event_to_vlpi_map(its_dev, event); |
1495 | ||
1496 | if (map->db_enabled == enable) | |
015ec038 MZ |
1497 | return; |
1498 | ||
c1d4d5cd | 1499 | map->db_enabled = enable; |
015ec038 MZ |
1500 | |
1501 | /* | |
1502 | * More fun with the architecture: | |
1503 | * | |
1504 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1505 | * value or to 1023, depending on the enable bit. But that | |
a359f757 | 1506 | * would be issuing a mapping for an /existing/ DevID+EventID |
015ec038 MZ |
1507 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI |
1508 | * to the /same/ vPE, using this opportunity to adjust the | |
1509 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1510 | */ | |
1511 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1512 | } |
1513 | ||
1514 | static void its_mask_irq(struct irq_data *d) | |
1515 | { | |
015ec038 MZ |
1516 | if (irqd_is_forwarded_to_vcpu(d)) |
1517 | its_vlpi_set_doorbell(d, false); | |
1518 | ||
adcdb94e | 1519 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1520 | } |
1521 | ||
1522 | static void its_unmask_irq(struct irq_data *d) | |
1523 | { | |
015ec038 MZ |
1524 | if (irqd_is_forwarded_to_vcpu(d)) |
1525 | its_vlpi_set_doorbell(d, true); | |
1526 | ||
adcdb94e | 1527 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1528 | } |
1529 | ||
2f13ff1d MZ |
1530 | static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu) |
1531 | { | |
1532 | if (irqd_affinity_is_managed(d)) | |
1533 | return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1534 | ||
1535 | return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1536 | } | |
1537 | ||
1538 | static void its_inc_lpi_count(struct irq_data *d, int cpu) | |
1539 | { | |
1540 | if (irqd_affinity_is_managed(d)) | |
1541 | atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1542 | else | |
1543 | atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1544 | } | |
1545 | ||
1546 | static void its_dec_lpi_count(struct irq_data *d, int cpu) | |
1547 | { | |
1548 | if (irqd_affinity_is_managed(d)) | |
1549 | atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); | |
1550 | else | |
1551 | atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); | |
1552 | } | |
1553 | ||
c5d6082d MZ |
1554 | static unsigned int cpumask_pick_least_loaded(struct irq_data *d, |
1555 | const struct cpumask *cpu_mask) | |
1556 | { | |
1557 | unsigned int cpu = nr_cpu_ids, tmp; | |
1558 | int count = S32_MAX; | |
1559 | ||
1560 | for_each_cpu(tmp, cpu_mask) { | |
1561 | int this_count = its_read_lpi_count(d, tmp); | |
1562 | if (this_count < count) { | |
1563 | cpu = tmp; | |
1564 | count = this_count; | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | return cpu; | |
1569 | } | |
1570 | ||
1571 | /* | |
1572 | * As suggested by Thomas Gleixner in: | |
1573 | * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de | |
1574 | */ | |
1575 | static int its_select_cpu(struct irq_data *d, | |
1576 | const struct cpumask *aff_mask) | |
1577 | { | |
1578 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
f55a9b59 PG |
1579 | static DEFINE_RAW_SPINLOCK(tmpmask_lock); |
1580 | static struct cpumask __tmpmask; | |
1581 | struct cpumask *tmpmask; | |
1582 | unsigned long flags; | |
c5d6082d | 1583 | int cpu, node; |
c5d6082d | 1584 | node = its_dev->its->numa_node; |
f55a9b59 PG |
1585 | tmpmask = &__tmpmask; |
1586 | ||
1587 | raw_spin_lock_irqsave(&tmpmask_lock, flags); | |
c5d6082d MZ |
1588 | |
1589 | if (!irqd_affinity_is_managed(d)) { | |
1590 | /* First try the NUMA node */ | |
1591 | if (node != NUMA_NO_NODE) { | |
1592 | /* | |
1593 | * Try the intersection of the affinity mask and the | |
1594 | * node mask (and the online mask, just to be safe). | |
1595 | */ | |
1596 | cpumask_and(tmpmask, cpumask_of_node(node), aff_mask); | |
1597 | cpumask_and(tmpmask, tmpmask, cpu_online_mask); | |
1598 | ||
1599 | /* | |
1600 | * Ideally, we would check if the mask is empty, and | |
1601 | * try again on the full node here. | |
1602 | * | |
1603 | * But it turns out that the way ACPI describes the | |
1604 | * affinity for ITSs only deals about memory, and | |
1605 | * not target CPUs, so it cannot describe a single | |
1606 | * ITS placed next to two NUMA nodes. | |
1607 | * | |
1608 | * Instead, just fallback on the online mask. This | |
1609 | * diverges from Thomas' suggestion above. | |
1610 | */ | |
1611 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1612 | if (cpu < nr_cpu_ids) | |
1613 | goto out; | |
1614 | ||
1615 | /* If we can't cross sockets, give up */ | |
1616 | if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) | |
1617 | goto out; | |
1618 | ||
1619 | /* If the above failed, expand the search */ | |
1620 | } | |
1621 | ||
1622 | /* Try the intersection of the affinity and online masks */ | |
1623 | cpumask_and(tmpmask, aff_mask, cpu_online_mask); | |
1624 | ||
1625 | /* If that doesn't fly, the online mask is the last resort */ | |
1626 | if (cpumask_empty(tmpmask)) | |
1627 | cpumask_copy(tmpmask, cpu_online_mask); | |
1628 | ||
1629 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1630 | } else { | |
3f893a59 | 1631 | cpumask_copy(tmpmask, aff_mask); |
c5d6082d MZ |
1632 | |
1633 | /* If we cannot cross sockets, limit the search to that node */ | |
1634 | if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && | |
1635 | node != NUMA_NO_NODE) | |
1636 | cpumask_and(tmpmask, tmpmask, cpumask_of_node(node)); | |
1637 | ||
1638 | cpu = cpumask_pick_least_loaded(d, tmpmask); | |
1639 | } | |
1640 | out: | |
f55a9b59 | 1641 | raw_spin_unlock_irqrestore(&tmpmask_lock, flags); |
c5d6082d MZ |
1642 | |
1643 | pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); | |
1644 | return cpu; | |
1645 | } | |
1646 | ||
c48ed51c MZ |
1647 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1648 | bool force) | |
1649 | { | |
c48ed51c MZ |
1650 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1651 | struct its_collection *target_col; | |
1652 | u32 id = its_get_event_id(d); | |
c5d6082d | 1653 | int cpu, prev_cpu; |
c48ed51c | 1654 | |
015ec038 MZ |
1655 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1656 | if (irqd_is_forwarded_to_vcpu(d)) | |
1657 | return -EINVAL; | |
1658 | ||
2f13ff1d MZ |
1659 | prev_cpu = its_dev->event_map.col_map[id]; |
1660 | its_dec_lpi_count(d, prev_cpu); | |
1661 | ||
c5d6082d MZ |
1662 | if (!force) |
1663 | cpu = its_select_cpu(d, mask_val); | |
1664 | else | |
1665 | cpu = cpumask_pick_least_loaded(d, mask_val); | |
fbf8f40e | 1666 | |
c5d6082d | 1667 | if (cpu < 0 || cpu >= nr_cpu_ids) |
2f13ff1d | 1668 | goto err; |
c48ed51c | 1669 | |
8b8d94a7 | 1670 | /* don't set the affinity when the target cpu is same as current one */ |
2f13ff1d | 1671 | if (cpu != prev_cpu) { |
8b8d94a7 M |
1672 | target_col = &its_dev->its->collections[cpu]; |
1673 | its_send_movi(its_dev, target_col, id); | |
1674 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1675 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1676 | } |
c48ed51c | 1677 | |
2f13ff1d MZ |
1678 | its_inc_lpi_count(d, cpu); |
1679 | ||
c48ed51c | 1680 | return IRQ_SET_MASK_OK_DONE; |
2f13ff1d MZ |
1681 | |
1682 | err: | |
1683 | its_inc_lpi_count(d, prev_cpu); | |
1684 | return -EINVAL; | |
c48ed51c MZ |
1685 | } |
1686 | ||
558b0165 AB |
1687 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1688 | { | |
1689 | struct its_node *its = its_dev->its; | |
1690 | ||
1691 | return its->phys_base + GITS_TRANSLATER; | |
1692 | } | |
1693 | ||
b48ac83d MZ |
1694 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1695 | { | |
1696 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1697 | struct its_node *its; | |
1698 | u64 addr; | |
1699 | ||
1700 | its = its_dev->its; | |
558b0165 | 1701 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1702 | |
b11283eb VM |
1703 | msg->address_lo = lower_32_bits(addr); |
1704 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1705 | msg->data = its_get_event_id(d); |
44bb7e24 | 1706 | |
35ae7df2 | 1707 | iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); |
b48ac83d MZ |
1708 | } |
1709 | ||
8d85dced MZ |
1710 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1711 | enum irqchip_irq_state which, | |
1712 | bool state) | |
1713 | { | |
1714 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1715 | u32 event = its_get_event_id(d); | |
1716 | ||
1717 | if (which != IRQCHIP_STATE_PENDING) | |
1718 | return -EINVAL; | |
1719 | ||
ed0e4aa9 MZ |
1720 | if (irqd_is_forwarded_to_vcpu(d)) { |
1721 | if (state) | |
1722 | its_send_vint(its_dev, event); | |
1723 | else | |
1724 | its_send_vclear(its_dev, event); | |
1725 | } else { | |
1726 | if (state) | |
1727 | its_send_int(its_dev, event); | |
1728 | else | |
1729 | its_send_clear(its_dev, event); | |
1730 | } | |
8d85dced MZ |
1731 | |
1732 | return 0; | |
1733 | } | |
1734 | ||
5f774f5e MZ |
1735 | static int its_irq_retrigger(struct irq_data *d) |
1736 | { | |
1737 | return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true); | |
1738 | } | |
1739 | ||
009384b3 MZ |
1740 | /* |
1741 | * Two favourable cases: | |
1742 | * | |
1743 | * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times | |
1744 | * for vSGI delivery | |
1745 | * | |
1746 | * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough | |
1747 | * and we're better off mapping all VPEs always | |
1748 | * | |
1749 | * If neither (a) nor (b) is true, then we map vPEs on demand. | |
1750 | * | |
1751 | */ | |
1752 | static bool gic_requires_eager_mapping(void) | |
1753 | { | |
1754 | if (!its_list_map || gic_rdists->has_rvpeid) | |
1755 | return true; | |
1756 | ||
1757 | return false; | |
1758 | } | |
1759 | ||
2247e1bf MZ |
1760 | static void its_map_vm(struct its_node *its, struct its_vm *vm) |
1761 | { | |
1762 | unsigned long flags; | |
1763 | ||
009384b3 | 1764 | if (gic_requires_eager_mapping()) |
2247e1bf MZ |
1765 | return; |
1766 | ||
1767 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1768 | ||
1769 | /* | |
1770 | * If the VM wasn't mapped yet, iterate over the vpes and get | |
1771 | * them mapped now. | |
1772 | */ | |
1773 | vm->vlpi_count[its->list_nr]++; | |
1774 | ||
1775 | if (vm->vlpi_count[its->list_nr] == 1) { | |
1776 | int i; | |
1777 | ||
1778 | for (i = 0; i < vm->nr_vpes; i++) { | |
1779 | struct its_vpe *vpe = vm->vpes[i]; | |
44c4c25e | 1780 | struct irq_data *d = irq_get_irq_data(vpe->irq); |
2247e1bf MZ |
1781 | |
1782 | /* Map the VPE to the first possible CPU */ | |
1783 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
1784 | its_send_vmapp(its, vpe, true); | |
1785 | its_send_vinvall(its, vpe); | |
44c4c25e | 1786 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
2247e1bf MZ |
1787 | } |
1788 | } | |
1789 | ||
1790 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1791 | } | |
1792 | ||
1793 | static void its_unmap_vm(struct its_node *its, struct its_vm *vm) | |
1794 | { | |
1795 | unsigned long flags; | |
1796 | ||
1797 | /* Not using the ITS list? Everything is always mapped. */ | |
009384b3 | 1798 | if (gic_requires_eager_mapping()) |
2247e1bf MZ |
1799 | return; |
1800 | ||
1801 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
1802 | ||
1803 | if (!--vm->vlpi_count[its->list_nr]) { | |
1804 | int i; | |
1805 | ||
1806 | for (i = 0; i < vm->nr_vpes; i++) | |
1807 | its_send_vmapp(its, vm->vpes[i], false); | |
1808 | } | |
1809 | ||
1810 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
1811 | } | |
1812 | ||
d011e4e6 MZ |
1813 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1814 | { | |
1815 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1816 | u32 event = its_get_event_id(d); | |
1817 | int ret = 0; | |
1818 | ||
1819 | if (!info->map) | |
1820 | return -EINVAL; | |
1821 | ||
11635fa2 | 1822 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1823 | |
1824 | if (!its_dev->event_map.vm) { | |
1825 | struct its_vlpi_map *maps; | |
1826 | ||
6396bb22 | 1827 | maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), |
11635fa2 | 1828 | GFP_ATOMIC); |
d011e4e6 MZ |
1829 | if (!maps) { |
1830 | ret = -ENOMEM; | |
1831 | goto out; | |
1832 | } | |
1833 | ||
1834 | its_dev->event_map.vm = info->map->vm; | |
1835 | its_dev->event_map.vlpi_maps = maps; | |
1836 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1837 | ret = -EINVAL; | |
1838 | goto out; | |
1839 | } | |
1840 | ||
1841 | /* Get our private copy of the mapping information */ | |
1842 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1843 | ||
1844 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1845 | /* Already mapped, move it around */ | |
1846 | its_send_vmovi(its_dev, event); | |
1847 | } else { | |
2247e1bf MZ |
1848 | /* Ensure all the VPEs are mapped on this ITS */ |
1849 | its_map_vm(its_dev->its, info->map->vm); | |
1850 | ||
d4d7b4ad MZ |
1851 | /* |
1852 | * Flag the interrupt as forwarded so that we can | |
1853 | * start poking the virtual property table. | |
1854 | */ | |
1855 | irqd_set_forwarded_to_vcpu(d); | |
1856 | ||
1857 | /* Write out the property to the prop table */ | |
1858 | lpi_write_config(d, 0xff, info->map->properties); | |
1859 | ||
d011e4e6 MZ |
1860 | /* Drop the physical mapping */ |
1861 | its_send_discard(its_dev, event); | |
1862 | ||
1863 | /* and install the virtual one */ | |
1864 | its_send_vmapti(its_dev, event); | |
d011e4e6 MZ |
1865 | |
1866 | /* Increment the number of VLPIs */ | |
1867 | its_dev->event_map.nr_vlpis++; | |
1868 | } | |
1869 | ||
1870 | out: | |
11635fa2 | 1871 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1872 | return ret; |
1873 | } | |
1874 | ||
1875 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1876 | { | |
1877 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
046b5054 | 1878 | struct its_vlpi_map *map; |
d011e4e6 MZ |
1879 | int ret = 0; |
1880 | ||
11635fa2 | 1881 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 | 1882 | |
046b5054 MZ |
1883 | map = get_vlpi_map(d); |
1884 | ||
1885 | if (!its_dev->event_map.vm || !map) { | |
d011e4e6 MZ |
1886 | ret = -EINVAL; |
1887 | goto out; | |
1888 | } | |
1889 | ||
1890 | /* Copy our mapping information to the incoming request */ | |
c1d4d5cd | 1891 | *info->map = *map; |
d011e4e6 MZ |
1892 | |
1893 | out: | |
11635fa2 | 1894 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1895 | return ret; |
1896 | } | |
1897 | ||
1898 | static int its_vlpi_unmap(struct irq_data *d) | |
1899 | { | |
1900 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1901 | u32 event = its_get_event_id(d); | |
1902 | int ret = 0; | |
1903 | ||
11635fa2 | 1904 | raw_spin_lock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1905 | |
1906 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1907 | ret = -EINVAL; | |
1908 | goto out; | |
1909 | } | |
1910 | ||
1911 | /* Drop the virtual mapping */ | |
1912 | its_send_discard(its_dev, event); | |
1913 | ||
1914 | /* and restore the physical one */ | |
1915 | irqd_clr_forwarded_to_vcpu(d); | |
1916 | its_send_mapti(its_dev, d->hwirq, event); | |
1917 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1918 | LPI_PROP_ENABLED | | |
1919 | LPI_PROP_GROUP1)); | |
1920 | ||
2247e1bf MZ |
1921 | /* Potentially unmap the VM from this ITS */ |
1922 | its_unmap_vm(its_dev->its, its_dev->event_map.vm); | |
1923 | ||
d011e4e6 MZ |
1924 | /* |
1925 | * Drop the refcount and make the device available again if | |
1926 | * this was the last VLPI. | |
1927 | */ | |
1928 | if (!--its_dev->event_map.nr_vlpis) { | |
1929 | its_dev->event_map.vm = NULL; | |
1930 | kfree(its_dev->event_map.vlpi_maps); | |
1931 | } | |
1932 | ||
1933 | out: | |
11635fa2 | 1934 | raw_spin_unlock(&its_dev->event_map.vlpi_lock); |
d011e4e6 MZ |
1935 | return ret; |
1936 | } | |
1937 | ||
015ec038 MZ |
1938 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1939 | { | |
1940 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1941 | ||
1942 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1943 | return -EINVAL; | |
1944 | ||
1945 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1946 | lpi_update_config(d, 0xff, info->config); | |
1947 | else | |
1948 | lpi_write_config(d, 0xff, info->config); | |
1949 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1950 | ||
1951 | return 0; | |
1952 | } | |
1953 | ||
c808eea8 MZ |
1954 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1955 | { | |
1956 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1957 | struct its_cmd_info *info = vcpu_info; | |
1958 | ||
1959 | /* Need a v4 ITS */ | |
0dd57fed | 1960 | if (!is_v4(its_dev->its)) |
c808eea8 MZ |
1961 | return -EINVAL; |
1962 | ||
d011e4e6 MZ |
1963 | /* Unmap request? */ |
1964 | if (!info) | |
1965 | return its_vlpi_unmap(d); | |
1966 | ||
c808eea8 MZ |
1967 | switch (info->cmd_type) { |
1968 | case MAP_VLPI: | |
d011e4e6 | 1969 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1970 | |
1971 | case GET_VLPI: | |
d011e4e6 | 1972 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1973 | |
1974 | case PROP_UPDATE_VLPI: | |
1975 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1976 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1977 | |
1978 | default: | |
1979 | return -EINVAL; | |
1980 | } | |
1981 | } | |
1982 | ||
c48ed51c MZ |
1983 | static struct irq_chip its_irq_chip = { |
1984 | .name = "ITS", | |
1985 | .irq_mask = its_mask_irq, | |
1986 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1987 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1988 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1989 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1990 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
5f774f5e | 1991 | .irq_retrigger = its_irq_retrigger, |
c808eea8 | 1992 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1993 | }; |
1994 | ||
880cb3cd | 1995 | |
bf9529f8 MZ |
1996 | /* |
1997 | * How we allocate LPIs: | |
1998 | * | |
880cb3cd MZ |
1999 | * lpi_range_list contains ranges of LPIs that are to available to |
2000 | * allocate from. To allocate LPIs, just pick the first range that | |
2001 | * fits the required allocation, and reduce it by the required | |
2002 | * amount. Once empty, remove the range from the list. | |
2003 | * | |
2004 | * To free a range of LPIs, add a free range to the list, sort it and | |
2005 | * merge the result if the new range happens to be adjacent to an | |
2006 | * already free block. | |
bf9529f8 | 2007 | * |
880cb3cd MZ |
2008 | * The consequence of the above is that allocation is cost is low, but |
2009 | * freeing is expensive. We assumes that freeing rarely occurs. | |
2010 | */ | |
4cb205c0 | 2011 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
880cb3cd | 2012 | |
880cb3cd MZ |
2013 | static DEFINE_MUTEX(lpi_range_lock); |
2014 | static LIST_HEAD(lpi_range_list); | |
2015 | ||
2016 | struct lpi_range { | |
2017 | struct list_head entry; | |
2018 | u32 base_id; | |
2019 | u32 span; | |
2020 | }; | |
bf9529f8 | 2021 | |
880cb3cd | 2022 | static struct lpi_range *mk_lpi_range(u32 base, u32 span) |
bf9529f8 | 2023 | { |
880cb3cd MZ |
2024 | struct lpi_range *range; |
2025 | ||
1c73fac5 | 2026 | range = kmalloc(sizeof(*range), GFP_KERNEL); |
880cb3cd | 2027 | if (range) { |
880cb3cd MZ |
2028 | range->base_id = base; |
2029 | range->span = span; | |
2030 | } | |
2031 | ||
2032 | return range; | |
bf9529f8 MZ |
2033 | } |
2034 | ||
880cb3cd MZ |
2035 | static int alloc_lpi_range(u32 nr_lpis, u32 *base) |
2036 | { | |
2037 | struct lpi_range *range, *tmp; | |
2038 | int err = -ENOSPC; | |
2039 | ||
2040 | mutex_lock(&lpi_range_lock); | |
2041 | ||
2042 | list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) { | |
2043 | if (range->span >= nr_lpis) { | |
2044 | *base = range->base_id; | |
2045 | range->base_id += nr_lpis; | |
2046 | range->span -= nr_lpis; | |
2047 | ||
2048 | if (range->span == 0) { | |
2049 | list_del(&range->entry); | |
2050 | kfree(range); | |
2051 | } | |
2052 | ||
2053 | err = 0; | |
2054 | break; | |
2055 | } | |
2056 | } | |
2057 | ||
2058 | mutex_unlock(&lpi_range_lock); | |
2059 | ||
2060 | pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); | |
2061 | return err; | |
bf9529f8 MZ |
2062 | } |
2063 | ||
12eade12 RV |
2064 | static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b) |
2065 | { | |
2066 | if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) | |
2067 | return; | |
2068 | if (a->base_id + a->span != b->base_id) | |
2069 | return; | |
2070 | b->base_id = a->base_id; | |
2071 | b->span += a->span; | |
2072 | list_del(&a->entry); | |
2073 | kfree(a); | |
2074 | } | |
2075 | ||
880cb3cd | 2076 | static int free_lpi_range(u32 base, u32 nr_lpis) |
bf9529f8 | 2077 | { |
12eade12 | 2078 | struct lpi_range *new, *old; |
880cb3cd MZ |
2079 | |
2080 | new = mk_lpi_range(base, nr_lpis); | |
b31a3838 RV |
2081 | if (!new) |
2082 | return -ENOMEM; | |
880cb3cd MZ |
2083 | |
2084 | mutex_lock(&lpi_range_lock); | |
2085 | ||
12eade12 RV |
2086 | list_for_each_entry_reverse(old, &lpi_range_list, entry) { |
2087 | if (old->base_id < base) | |
2088 | break; | |
880cb3cd | 2089 | } |
12eade12 RV |
2090 | /* |
2091 | * old is the last element with ->base_id smaller than base, | |
2092 | * so new goes right after it. If there are no elements with | |
2093 | * ->base_id smaller than base, &old->entry ends up pointing | |
2094 | * at the head of the list, and inserting new it the start of | |
2095 | * the list is the right thing to do in that case as well. | |
2096 | */ | |
2097 | list_add(&new->entry, &old->entry); | |
2098 | /* | |
2099 | * Now check if we can merge with the preceding and/or | |
2100 | * following ranges. | |
2101 | */ | |
2102 | merge_lpi_ranges(old, new); | |
2103 | merge_lpi_ranges(new, list_next_entry(new, entry)); | |
880cb3cd | 2104 | |
880cb3cd | 2105 | mutex_unlock(&lpi_range_lock); |
b31a3838 | 2106 | return 0; |
880cb3cd MZ |
2107 | } |
2108 | ||
2109 | static int __init its_lpi_init(u32 id_bits) | |
2110 | { | |
2111 | u32 lpis = (1UL << id_bits) - 8192; | |
12b2905a | 2112 | u32 numlpis; |
880cb3cd MZ |
2113 | int err; |
2114 | ||
12b2905a MZ |
2115 | numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); |
2116 | ||
2117 | if (numlpis > 2 && !WARN_ON(numlpis > lpis)) { | |
2118 | lpis = numlpis; | |
2119 | pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", | |
2120 | lpis); | |
2121 | } | |
2122 | ||
880cb3cd MZ |
2123 | /* |
2124 | * Initializing the allocator is just the same as freeing the | |
2125 | * full range of LPIs. | |
2126 | */ | |
2127 | err = free_lpi_range(8192, lpis); | |
2128 | pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); | |
2129 | return err; | |
2130 | } | |
bf9529f8 | 2131 | |
38dd7c49 | 2132 | static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids) |
880cb3cd MZ |
2133 | { |
2134 | unsigned long *bitmap = NULL; | |
2135 | int err = 0; | |
bf9529f8 MZ |
2136 | |
2137 | do { | |
38dd7c49 | 2138 | err = alloc_lpi_range(nr_irqs, base); |
880cb3cd | 2139 | if (!err) |
bf9529f8 MZ |
2140 | break; |
2141 | ||
38dd7c49 MZ |
2142 | nr_irqs /= 2; |
2143 | } while (nr_irqs > 0); | |
bf9529f8 | 2144 | |
45725e0f MZ |
2145 | if (!nr_irqs) |
2146 | err = -ENOSPC; | |
2147 | ||
880cb3cd | 2148 | if (err) |
bf9529f8 MZ |
2149 | goto out; |
2150 | ||
ff5fe886 | 2151 | bitmap = bitmap_zalloc(nr_irqs, GFP_ATOMIC); |
bf9529f8 MZ |
2152 | if (!bitmap) |
2153 | goto out; | |
2154 | ||
38dd7c49 | 2155 | *nr_ids = nr_irqs; |
bf9529f8 MZ |
2156 | |
2157 | out: | |
c8415b94 MZ |
2158 | if (!bitmap) |
2159 | *base = *nr_ids = 0; | |
2160 | ||
bf9529f8 MZ |
2161 | return bitmap; |
2162 | } | |
2163 | ||
38dd7c49 | 2164 | static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids) |
bf9529f8 | 2165 | { |
880cb3cd | 2166 | WARN_ON(free_lpi_range(base, nr_ids)); |
ff5fe886 | 2167 | bitmap_free(bitmap); |
bf9529f8 | 2168 | } |
1ac19ca6 | 2169 | |
053be485 MZ |
2170 | static void gic_reset_prop_table(void *va) |
2171 | { | |
2172 | /* Priority 0xa0, Group-1, disabled */ | |
2173 | memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ); | |
2174 | ||
2175 | /* Make sure the GIC will observe the written configuration */ | |
2176 | gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ); | |
2177 | } | |
2178 | ||
0e5ccf91 MZ |
2179 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
2180 | { | |
2181 | struct page *prop_page; | |
1ac19ca6 | 2182 | |
0e5ccf91 MZ |
2183 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
2184 | if (!prop_page) | |
2185 | return NULL; | |
2186 | ||
053be485 | 2187 | gic_reset_prop_table(page_address(prop_page)); |
0e5ccf91 MZ |
2188 | |
2189 | return prop_page; | |
2190 | } | |
2191 | ||
7d75bbb4 MZ |
2192 | static void its_free_prop_table(struct page *prop_page) |
2193 | { | |
2194 | free_pages((unsigned long)page_address(prop_page), | |
2195 | get_order(LPI_PROPBASE_SZ)); | |
2196 | } | |
1ac19ca6 | 2197 | |
5e2c9f9a MZ |
2198 | static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size) |
2199 | { | |
2200 | phys_addr_t start, end, addr_end; | |
2201 | u64 i; | |
2202 | ||
2203 | /* | |
2204 | * We don't bother checking for a kdump kernel as by | |
2205 | * construction, the LPI tables are out of this kernel's | |
2206 | * memory map. | |
2207 | */ | |
2208 | if (is_kdump_kernel()) | |
2209 | return true; | |
2210 | ||
2211 | addr_end = addr + size - 1; | |
2212 | ||
9f3d5eaa | 2213 | for_each_reserved_mem_range(i, &start, &end) { |
5e2c9f9a MZ |
2214 | if (addr >= start && addr_end <= end) |
2215 | return true; | |
2216 | } | |
2217 | ||
2218 | /* Not found, not a good sign... */ | |
2219 | pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n", | |
2220 | &addr, &addr_end); | |
2221 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
2222 | return false; | |
2223 | } | |
2224 | ||
3fb68fae MZ |
2225 | static int gic_reserve_range(phys_addr_t addr, unsigned long size) |
2226 | { | |
2227 | if (efi_enabled(EFI_CONFIG_TABLES)) | |
2228 | return efi_mem_reserve_persistent(addr, size); | |
2229 | ||
2230 | return 0; | |
2231 | } | |
2232 | ||
11e37d35 | 2233 | static int __init its_setup_lpi_prop_table(void) |
1ac19ca6 | 2234 | { |
c440a9d9 MZ |
2235 | if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { |
2236 | u64 val; | |
1ac19ca6 | 2237 | |
c440a9d9 MZ |
2238 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); |
2239 | lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1; | |
1ac19ca6 | 2240 | |
c440a9d9 MZ |
2241 | gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); |
2242 | gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, | |
2243 | LPI_PROPBASE_SZ, | |
2244 | MEMREMAP_WB); | |
2245 | gic_reset_prop_table(gic_rdists->prop_table_va); | |
2246 | } else { | |
2247 | struct page *page; | |
2248 | ||
2249 | lpi_id_bits = min_t(u32, | |
2250 | GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), | |
2251 | ITS_MAX_LPI_NRBITS); | |
2252 | page = its_allocate_prop_table(GFP_NOWAIT); | |
2253 | if (!page) { | |
2254 | pr_err("Failed to allocate PROPBASE\n"); | |
2255 | return -ENOMEM; | |
2256 | } | |
2257 | ||
2258 | gic_rdists->prop_table_pa = page_to_phys(page); | |
2259 | gic_rdists->prop_table_va = page_address(page); | |
3fb68fae MZ |
2260 | WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, |
2261 | LPI_PROPBASE_SZ)); | |
c440a9d9 | 2262 | } |
e1a2e201 MZ |
2263 | |
2264 | pr_info("GICv3: using LPI property table @%pa\n", | |
2265 | &gic_rdists->prop_table_pa); | |
1ac19ca6 | 2266 | |
6c31e123 | 2267 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
2268 | } |
2269 | ||
2270 | static const char *its_base_type_string[] = { | |
2271 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
2272 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 2273 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
2274 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
2275 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
2276 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
2277 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
2278 | }; | |
2279 | ||
2d81d425 SD |
2280 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
2281 | { | |
2282 | u32 idx = baser - its->tables; | |
2283 | ||
0968a619 | 2284 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
2285 | } |
2286 | ||
2287 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
2288 | u64 val) | |
2289 | { | |
2290 | u32 idx = baser - its->tables; | |
2291 | ||
0968a619 | 2292 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
2293 | baser->val = its_read_baser(its, baser); |
2294 | } | |
2295 | ||
9347359a | 2296 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
d5df9dc9 | 2297 | u64 cache, u64 shr, u32 order, bool indirect) |
9347359a SD |
2298 | { |
2299 | u64 val = its_read_baser(its, baser); | |
2300 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
2301 | u64 type = GITS_BASER_TYPE(val); | |
30ae9610 | 2302 | u64 baser_phys, tmp; |
d5df9dc9 | 2303 | u32 alloc_pages, psz; |
539d3782 | 2304 | struct page *page; |
9347359a | 2305 | void *base; |
9347359a | 2306 | |
d5df9dc9 | 2307 | psz = baser->psz; |
9347359a SD |
2308 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); |
2309 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
2310 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
2311 | &its->phys_base, its_base_type_string[type], | |
2312 | alloc_pages, GITS_BASER_PAGES_MAX); | |
2313 | alloc_pages = GITS_BASER_PAGES_MAX; | |
2314 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
2315 | } | |
2316 | ||
539d3782 SD |
2317 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); |
2318 | if (!page) | |
9347359a SD |
2319 | return -ENOMEM; |
2320 | ||
539d3782 | 2321 | base = (void *)page_address(page); |
30ae9610 SD |
2322 | baser_phys = virt_to_phys(base); |
2323 | ||
2324 | /* Check if the physical address of the memory is above 48bits */ | |
2325 | if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) { | |
2326 | ||
2327 | /* 52bit PA is supported only when PageSize=64K */ | |
2328 | if (psz != SZ_64K) { | |
2329 | pr_err("ITS: no 52bit PA support when psz=%d\n", psz); | |
2330 | free_pages((unsigned long)base, order); | |
2331 | return -ENXIO; | |
2332 | } | |
2333 | ||
2334 | /* Convert 52bit PA to 48bit field */ | |
2335 | baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys); | |
2336 | } | |
2337 | ||
9347359a | 2338 | retry_baser: |
30ae9610 | 2339 | val = (baser_phys | |
9347359a SD |
2340 | (type << GITS_BASER_TYPE_SHIFT) | |
2341 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
2342 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
2343 | cache | | |
2344 | shr | | |
2345 | GITS_BASER_VALID); | |
2346 | ||
3faf24ea SD |
2347 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
2348 | ||
9347359a SD |
2349 | switch (psz) { |
2350 | case SZ_4K: | |
2351 | val |= GITS_BASER_PAGE_SIZE_4K; | |
2352 | break; | |
2353 | case SZ_16K: | |
2354 | val |= GITS_BASER_PAGE_SIZE_16K; | |
2355 | break; | |
2356 | case SZ_64K: | |
2357 | val |= GITS_BASER_PAGE_SIZE_64K; | |
2358 | break; | |
2359 | } | |
2360 | ||
2361 | its_write_baser(its, baser, val); | |
2362 | tmp = baser->val; | |
2363 | ||
a8707f55 SR |
2364 | if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) |
2365 | tmp &= ~GITS_BASER_SHAREABILITY_MASK; | |
2366 | ||
9347359a SD |
2367 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { |
2368 | /* | |
2369 | * Shareability didn't stick. Just use | |
2370 | * whatever the read reported, which is likely | |
2371 | * to be the only thing this redistributor | |
2372 | * supports. If that's zero, make it | |
2373 | * non-cacheable as well. | |
2374 | */ | |
2375 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
2376 | if (!shr) { | |
2377 | cache = GITS_BASER_nC; | |
328191c0 | 2378 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
2379 | } |
2380 | goto retry_baser; | |
2381 | } | |
2382 | ||
9347359a | 2383 | if (val != tmp) { |
b11283eb | 2384 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 2385 | &its->phys_base, its_base_type_string[type], |
b11283eb | 2386 | val, tmp); |
9347359a SD |
2387 | free_pages((unsigned long)base, order); |
2388 | return -ENXIO; | |
2389 | } | |
2390 | ||
2391 | baser->order = order; | |
2392 | baser->base = base; | |
2393 | baser->psz = psz; | |
3faf24ea | 2394 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 2395 | |
3faf24ea | 2396 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 2397 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
2398 | its_base_type_string[type], |
2399 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 2400 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
2401 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
2402 | ||
2403 | return 0; | |
2404 | } | |
2405 | ||
4cacac57 MZ |
2406 | static bool its_parse_indirect_baser(struct its_node *its, |
2407 | struct its_baser *baser, | |
d5df9dc9 | 2408 | u32 *order, u32 ids) |
4b75c459 | 2409 | { |
4cacac57 MZ |
2410 | u64 tmp = its_read_baser(its, baser); |
2411 | u64 type = GITS_BASER_TYPE(tmp); | |
2412 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 2413 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 | 2414 | u32 new_order = *order; |
d5df9dc9 | 2415 | u32 psz = baser->psz; |
3faf24ea SD |
2416 | bool indirect = false; |
2417 | ||
2418 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
2419 | if ((esz << ids) > (psz * 2)) { | |
2420 | /* | |
2421 | * Find out whether hw supports a single or two-level table by | |
2422 | * table by reading bit at offset '62' after writing '1' to it. | |
2423 | */ | |
2424 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
2425 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
2426 | ||
2427 | if (indirect) { | |
2428 | /* | |
2429 | * The size of the lvl2 table is equal to ITS page size | |
2430 | * which is 'psz'. For computing lvl1 table size, | |
2431 | * subtract ID bits that sparse lvl2 table from 'ids' | |
2432 | * which is reported by ITS hardware times lvl1 table | |
2433 | * entry size. | |
2434 | */ | |
d524eaa2 | 2435 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
2436 | esz = GITS_LVL1_ENTRY_SIZE; |
2437 | } | |
2438 | } | |
4b75c459 SD |
2439 | |
2440 | /* | |
2441 | * Allocate as many entries as required to fit the | |
2442 | * range of device IDs that the ITS can grok... The ID | |
2443 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
2444 | * massive waste of memory if two-level device table |
2445 | * feature is not supported by hardware. | |
4b75c459 SD |
2446 | */ |
2447 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
23baf831 KS |
2448 | if (new_order > MAX_ORDER) { |
2449 | new_order = MAX_ORDER; | |
d524eaa2 | 2450 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
576a8342 | 2451 | pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", |
4cacac57 | 2452 | &its->phys_base, its_base_type_string[type], |
576a8342 | 2453 | device_ids(its), ids); |
4b75c459 SD |
2454 | } |
2455 | ||
2456 | *order = new_order; | |
3faf24ea SD |
2457 | |
2458 | return indirect; | |
4b75c459 SD |
2459 | } |
2460 | ||
5e516846 MZ |
2461 | static u32 compute_common_aff(u64 val) |
2462 | { | |
2463 | u32 aff, clpiaff; | |
2464 | ||
2465 | aff = FIELD_GET(GICR_TYPER_AFFINITY, val); | |
2466 | clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val); | |
2467 | ||
2468 | return aff & ~(GENMASK(31, 0) >> (clpiaff * 8)); | |
2469 | } | |
2470 | ||
2471 | static u32 compute_its_aff(struct its_node *its) | |
2472 | { | |
2473 | u64 val; | |
2474 | u32 svpet; | |
2475 | ||
2476 | /* | |
2477 | * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute | |
2478 | * the resulting affinity. We then use that to see if this match | |
2479 | * our own affinity. | |
2480 | */ | |
2481 | svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); | |
2482 | val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet); | |
2483 | val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); | |
2484 | return compute_common_aff(val); | |
2485 | } | |
2486 | ||
2487 | static struct its_node *find_sibling_its(struct its_node *cur_its) | |
2488 | { | |
2489 | struct its_node *its; | |
2490 | u32 aff; | |
2491 | ||
2492 | if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) | |
2493 | return NULL; | |
2494 | ||
2495 | aff = compute_its_aff(cur_its); | |
2496 | ||
2497 | list_for_each_entry(its, &its_nodes, entry) { | |
2498 | u64 baser; | |
2499 | ||
2500 | if (!is_v4_1(its) || its == cur_its) | |
2501 | continue; | |
2502 | ||
2503 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2504 | continue; | |
2505 | ||
2506 | if (aff != compute_its_aff(its)) | |
2507 | continue; | |
2508 | ||
2509 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2510 | baser = its->tables[2].val; | |
2511 | if (!(baser & GITS_BASER_VALID)) | |
2512 | continue; | |
2513 | ||
2514 | return its; | |
2515 | } | |
2516 | ||
2517 | return NULL; | |
2518 | } | |
2519 | ||
1ac19ca6 MZ |
2520 | static void its_free_tables(struct its_node *its) |
2521 | { | |
2522 | int i; | |
2523 | ||
2524 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
2525 | if (its->tables[i].base) { |
2526 | free_pages((unsigned long)its->tables[i].base, | |
2527 | its->tables[i].order); | |
2528 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
2529 | } |
2530 | } | |
2531 | } | |
2532 | ||
d5df9dc9 MZ |
2533 | static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) |
2534 | { | |
2535 | u64 psz = SZ_64K; | |
2536 | ||
2537 | while (psz) { | |
2538 | u64 val, gpsz; | |
2539 | ||
2540 | val = its_read_baser(its, baser); | |
2541 | val &= ~GITS_BASER_PAGE_SIZE_MASK; | |
2542 | ||
2543 | switch (psz) { | |
2544 | case SZ_64K: | |
2545 | gpsz = GITS_BASER_PAGE_SIZE_64K; | |
2546 | break; | |
2547 | case SZ_16K: | |
2548 | gpsz = GITS_BASER_PAGE_SIZE_16K; | |
2549 | break; | |
2550 | case SZ_4K: | |
2551 | default: | |
2552 | gpsz = GITS_BASER_PAGE_SIZE_4K; | |
2553 | break; | |
2554 | } | |
2555 | ||
2556 | gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT; | |
2557 | ||
2558 | val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz); | |
2559 | its_write_baser(its, baser, val); | |
2560 | ||
2561 | if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) | |
2562 | break; | |
2563 | ||
2564 | switch (psz) { | |
2565 | case SZ_64K: | |
2566 | psz = SZ_16K; | |
2567 | break; | |
2568 | case SZ_16K: | |
2569 | psz = SZ_4K; | |
2570 | break; | |
2571 | case SZ_4K: | |
2572 | default: | |
2573 | return -1; | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | baser->psz = psz; | |
2578 | return 0; | |
2579 | } | |
2580 | ||
0e0b0f69 | 2581 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 2582 | { |
1ac19ca6 | 2583 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 2584 | u64 cache = GITS_BASER_RaWaWb; |
9347359a | 2585 | int err, i; |
94100970 | 2586 | |
fa150019 AB |
2587 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
2588 | /* erratum 24313: ignore memory access type */ | |
2589 | cache = GITS_BASER_nCnB; | |
466b7d16 | 2590 | |
1ac19ca6 | 2591 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
2592 | struct its_baser *baser = its->tables + i; |
2593 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 2594 | u64 type = GITS_BASER_TYPE(val); |
3faf24ea | 2595 | bool indirect = false; |
d5df9dc9 | 2596 | u32 order; |
1ac19ca6 | 2597 | |
d5df9dc9 | 2598 | if (type == GITS_BASER_TYPE_NONE) |
1ac19ca6 MZ |
2599 | continue; |
2600 | ||
d5df9dc9 MZ |
2601 | if (its_probe_baser_psz(its, baser)) { |
2602 | its_free_tables(its); | |
2603 | return -ENXIO; | |
2604 | } | |
2605 | ||
2606 | order = get_order(baser->psz); | |
2607 | ||
2608 | switch (type) { | |
4cacac57 | 2609 | case GITS_BASER_TYPE_DEVICE: |
d5df9dc9 | 2610 | indirect = its_parse_indirect_baser(its, baser, &order, |
576a8342 | 2611 | device_ids(its)); |
8d565748 ZY |
2612 | break; |
2613 | ||
4cacac57 | 2614 | case GITS_BASER_TYPE_VCPU: |
5e516846 MZ |
2615 | if (is_v4_1(its)) { |
2616 | struct its_node *sibling; | |
2617 | ||
2618 | WARN_ON(i != 2); | |
2619 | if ((sibling = find_sibling_its(its))) { | |
2620 | *baser = sibling->tables[2]; | |
2621 | its_write_baser(its, baser, baser->val); | |
2622 | continue; | |
2623 | } | |
2624 | } | |
2625 | ||
d5df9dc9 | 2626 | indirect = its_parse_indirect_baser(its, baser, &order, |
32bd44dc | 2627 | ITS_MAX_VPEID_BITS); |
4cacac57 MZ |
2628 | break; |
2629 | } | |
f54b97ed | 2630 | |
d5df9dc9 | 2631 | err = its_setup_baser(its, baser, cache, shr, order, indirect); |
9347359a SD |
2632 | if (err < 0) { |
2633 | its_free_tables(its); | |
2634 | return err; | |
1ac19ca6 MZ |
2635 | } |
2636 | ||
9347359a | 2637 | /* Update settings which will be used for next BASERn */ |
9347359a SD |
2638 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; |
2639 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
2640 | } |
2641 | ||
2642 | return 0; | |
1ac19ca6 MZ |
2643 | } |
2644 | ||
5e516846 MZ |
2645 | static u64 inherit_vpe_l1_table_from_its(void) |
2646 | { | |
2647 | struct its_node *its; | |
2648 | u64 val; | |
2649 | u32 aff; | |
2650 | ||
2651 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2652 | aff = compute_common_aff(val); | |
2653 | ||
2654 | list_for_each_entry(its, &its_nodes, entry) { | |
2655 | u64 baser, addr; | |
2656 | ||
2657 | if (!is_v4_1(its)) | |
2658 | continue; | |
2659 | ||
2660 | if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) | |
2661 | continue; | |
2662 | ||
2663 | if (aff != compute_its_aff(its)) | |
2664 | continue; | |
2665 | ||
2666 | /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ | |
2667 | baser = its->tables[2].val; | |
2668 | if (!(baser & GITS_BASER_VALID)) | |
2669 | continue; | |
2670 | ||
2671 | /* We have a winner! */ | |
8b718d40 ZY |
2672 | gic_data_rdist()->vpe_l1_base = its->tables[2].base; |
2673 | ||
5e516846 MZ |
2674 | val = GICR_VPROPBASER_4_1_VALID; |
2675 | if (baser & GITS_BASER_INDIRECT) | |
2676 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2677 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, | |
2678 | FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)); | |
2679 | switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) { | |
2680 | case GIC_PAGE_SIZE_64K: | |
2681 | addr = GITS_BASER_ADDR_48_to_52(baser); | |
2682 | break; | |
2683 | default: | |
2684 | addr = baser & GENMASK_ULL(47, 12); | |
2685 | break; | |
2686 | } | |
2687 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12); | |
2688 | val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK, | |
2689 | FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser)); | |
2690 | val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK, | |
2691 | FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser)); | |
2692 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); | |
2693 | ||
2694 | return val; | |
2695 | } | |
2696 | ||
2697 | return 0; | |
2698 | } | |
2699 | ||
2700 | static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask) | |
2701 | { | |
2702 | u32 aff; | |
2703 | u64 val; | |
2704 | int cpu; | |
2705 | ||
2706 | val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
2707 | aff = compute_common_aff(val); | |
2708 | ||
2709 | for_each_possible_cpu(cpu) { | |
2710 | void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; | |
5e516846 MZ |
2711 | |
2712 | if (!base || cpu == smp_processor_id()) | |
2713 | continue; | |
2714 | ||
2715 | val = gic_read_typer(base + GICR_TYPER); | |
4bccf1d7 | 2716 | if (aff != compute_common_aff(val)) |
5e516846 MZ |
2717 | continue; |
2718 | ||
2719 | /* | |
2720 | * At this point, we have a victim. This particular CPU | |
2721 | * has already booted, and has an affinity that matches | |
2722 | * ours wrt CommonLPIAff. Let's use its own VPROPBASER. | |
2723 | * Make sure we don't write the Z bit in that case. | |
2724 | */ | |
5186a6cc | 2725 | val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); |
5e516846 MZ |
2726 | val &= ~GICR_VPROPBASER_4_1_Z; |
2727 | ||
8b718d40 | 2728 | gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; |
5e516846 MZ |
2729 | *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; |
2730 | ||
2731 | return val; | |
2732 | } | |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | ||
4e6437f1 ZY |
2737 | static bool allocate_vpe_l2_table(int cpu, u32 id) |
2738 | { | |
2739 | void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; | |
490d332e MZ |
2740 | unsigned int psz, esz, idx, npg, gpsz; |
2741 | u64 val; | |
4e6437f1 ZY |
2742 | struct page *page; |
2743 | __le64 *table; | |
2744 | ||
2745 | if (!gic_rdists->has_rvpeid) | |
2746 | return true; | |
2747 | ||
28d160de MZ |
2748 | /* Skip non-present CPUs */ |
2749 | if (!base) | |
2750 | return true; | |
2751 | ||
5186a6cc | 2752 | val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); |
4e6437f1 ZY |
2753 | |
2754 | esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; | |
2755 | gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); | |
2756 | npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1; | |
2757 | ||
2758 | switch (gpsz) { | |
2759 | default: | |
2760 | WARN_ON(1); | |
df561f66 | 2761 | fallthrough; |
4e6437f1 ZY |
2762 | case GIC_PAGE_SIZE_4K: |
2763 | psz = SZ_4K; | |
2764 | break; | |
2765 | case GIC_PAGE_SIZE_16K: | |
2766 | psz = SZ_16K; | |
2767 | break; | |
2768 | case GIC_PAGE_SIZE_64K: | |
2769 | psz = SZ_64K; | |
2770 | break; | |
2771 | } | |
2772 | ||
2773 | /* Don't allow vpe_id that exceeds single, flat table limit */ | |
2774 | if (!(val & GICR_VPROPBASER_4_1_INDIRECT)) | |
2775 | return (id < (npg * psz / (esz * SZ_8))); | |
2776 | ||
2777 | /* Compute 1st level table index & check if that exceeds table limit */ | |
2778 | idx = id >> ilog2(psz / (esz * SZ_8)); | |
2779 | if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE)) | |
2780 | return false; | |
2781 | ||
2782 | table = gic_data_rdist_cpu(cpu)->vpe_l1_base; | |
2783 | ||
2784 | /* Allocate memory for 2nd level table */ | |
2785 | if (!table[idx]) { | |
2786 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz)); | |
2787 | if (!page) | |
2788 | return false; | |
2789 | ||
2790 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
2791 | if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK)) | |
2792 | gic_flush_dcache_to_poc(page_address(page), psz); | |
2793 | ||
2794 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
2795 | ||
2796 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
2797 | if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK)) | |
2798 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); | |
2799 | ||
2800 | /* Ensure updated table contents are visible to RD hardware */ | |
2801 | dsb(sy); | |
2802 | } | |
2803 | ||
2804 | return true; | |
2805 | } | |
2806 | ||
5e516846 MZ |
2807 | static int allocate_vpe_l1_table(void) |
2808 | { | |
2809 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
2810 | u64 val, gpsz, npg, pa; | |
2811 | unsigned int psz = SZ_64K; | |
2812 | unsigned int np, epp, esz; | |
2813 | struct page *page; | |
2814 | ||
2815 | if (!gic_rdists->has_rvpeid) | |
2816 | return 0; | |
2817 | ||
2818 | /* | |
2819 | * if VPENDBASER.Valid is set, disable any previously programmed | |
2820 | * VPE by setting PendingLast while clearing Valid. This has the | |
2821 | * effect of making sure no doorbell will be generated and we can | |
2822 | * then safely clear VPROPBASER.Valid. | |
2823 | */ | |
5186a6cc ZY |
2824 | if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid) |
2825 | gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast, | |
5e516846 MZ |
2826 | vlpi_base + GICR_VPENDBASER); |
2827 | ||
2828 | /* | |
2829 | * If we can inherit the configuration from another RD, let's do | |
2830 | * so. Otherwise, we have to go through the allocation process. We | |
2831 | * assume that all RDs have the exact same requirements, as | |
2832 | * nothing will work otherwise. | |
2833 | */ | |
2834 | val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); | |
2835 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2836 | goto out; | |
2837 | ||
d1bd7e0b | 2838 | gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC); |
5e516846 MZ |
2839 | if (!gic_data_rdist()->vpe_table_mask) |
2840 | return -ENOMEM; | |
2841 | ||
2842 | val = inherit_vpe_l1_table_from_its(); | |
2843 | if (val & GICR_VPROPBASER_4_1_VALID) | |
2844 | goto out; | |
2845 | ||
2846 | /* First probe the page size */ | |
2847 | val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K); | |
5186a6cc ZY |
2848 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
2849 | val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER); | |
5e516846 MZ |
2850 | gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); |
2851 | esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val); | |
2852 | ||
2853 | switch (gpsz) { | |
2854 | default: | |
2855 | gpsz = GIC_PAGE_SIZE_4K; | |
df561f66 | 2856 | fallthrough; |
5e516846 MZ |
2857 | case GIC_PAGE_SIZE_4K: |
2858 | psz = SZ_4K; | |
2859 | break; | |
2860 | case GIC_PAGE_SIZE_16K: | |
2861 | psz = SZ_16K; | |
2862 | break; | |
2863 | case GIC_PAGE_SIZE_64K: | |
2864 | psz = SZ_64K; | |
2865 | break; | |
2866 | } | |
2867 | ||
2868 | /* | |
2869 | * Start populating the register from scratch, including RO fields | |
2870 | * (which we want to print in debug cases...) | |
2871 | */ | |
2872 | val = 0; | |
2873 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz); | |
2874 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz); | |
2875 | ||
2876 | /* How many entries per GIC page? */ | |
2877 | esz++; | |
2878 | epp = psz / (esz * SZ_8); | |
2879 | ||
2880 | /* | |
2881 | * If we need more than just a single L1 page, flag the table | |
2882 | * as indirect and compute the number of required L1 pages. | |
2883 | */ | |
2884 | if (epp < ITS_MAX_VPEID) { | |
2885 | int nl2; | |
2886 | ||
2887 | val |= GICR_VPROPBASER_4_1_INDIRECT; | |
2888 | ||
2889 | /* Number of L2 pages required to cover the VPEID space */ | |
2890 | nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp); | |
2891 | ||
2892 | /* Number of L1 pages to point to the L2 pages */ | |
2893 | npg = DIV_ROUND_UP(nl2 * SZ_8, psz); | |
2894 | } else { | |
2895 | npg = 1; | |
2896 | } | |
2897 | ||
e88bd316 | 2898 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); |
5e516846 MZ |
2899 | |
2900 | /* Right, that's the number of CPU pages we need for L1 */ | |
2901 | np = DIV_ROUND_UP(npg * psz, PAGE_SIZE); | |
2902 | ||
2903 | pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n", | |
2904 | np, npg, psz, epp, esz); | |
d1bd7e0b | 2905 | page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE)); |
5e516846 MZ |
2906 | if (!page) |
2907 | return -ENOMEM; | |
2908 | ||
8b718d40 | 2909 | gic_data_rdist()->vpe_l1_base = page_address(page); |
5e516846 MZ |
2910 | pa = virt_to_phys(page_address(page)); |
2911 | WARN_ON(!IS_ALIGNED(pa, psz)); | |
2912 | ||
2913 | val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12); | |
2914 | val |= GICR_VPROPBASER_RaWb; | |
2915 | val |= GICR_VPROPBASER_InnerShareable; | |
2916 | val |= GICR_VPROPBASER_4_1_Z; | |
2917 | val |= GICR_VPROPBASER_4_1_VALID; | |
2918 | ||
2919 | out: | |
5186a6cc | 2920 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
5e516846 MZ |
2921 | cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); |
2922 | ||
2923 | pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n", | |
2924 | smp_processor_id(), val, | |
2925 | cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); | |
2926 | ||
2927 | return 0; | |
2928 | } | |
2929 | ||
1ac19ca6 MZ |
2930 | static int its_alloc_collections(struct its_node *its) |
2931 | { | |
83559b47 MZ |
2932 | int i; |
2933 | ||
6396bb22 | 2934 | its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), |
1ac19ca6 MZ |
2935 | GFP_KERNEL); |
2936 | if (!its->collections) | |
2937 | return -ENOMEM; | |
2938 | ||
83559b47 MZ |
2939 | for (i = 0; i < nr_cpu_ids; i++) |
2940 | its->collections[i].target_address = ~0ULL; | |
2941 | ||
1ac19ca6 MZ |
2942 | return 0; |
2943 | } | |
2944 | ||
7c297a2d MZ |
2945 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
2946 | { | |
2947 | struct page *pend_page; | |
adaab500 | 2948 | |
7c297a2d | 2949 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, |
adaab500 | 2950 | get_order(LPI_PENDBASE_SZ)); |
7c297a2d MZ |
2951 | if (!pend_page) |
2952 | return NULL; | |
2953 | ||
2954 | /* Make sure the GIC will observe the zero-ed page */ | |
2955 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
2956 | ||
2957 | return pend_page; | |
2958 | } | |
2959 | ||
7d75bbb4 MZ |
2960 | static void its_free_pending_table(struct page *pt) |
2961 | { | |
adaab500 | 2962 | free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ)); |
7d75bbb4 MZ |
2963 | } |
2964 | ||
c6e2ccb6 | 2965 | /* |
5e2c9f9a MZ |
2966 | * Booting with kdump and LPIs enabled is generally fine. Any other |
2967 | * case is wrong in the absence of firmware/EFI support. | |
c6e2ccb6 | 2968 | */ |
c440a9d9 MZ |
2969 | static bool enabled_lpis_allowed(void) |
2970 | { | |
5e2c9f9a MZ |
2971 | phys_addr_t addr; |
2972 | u64 val; | |
c6e2ccb6 | 2973 | |
5e2c9f9a MZ |
2974 | /* Check whether the property table is in a reserved region */ |
2975 | val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER); | |
2976 | addr = val & GENMASK_ULL(51, 12); | |
2977 | ||
2978 | return gic_check_reserved_range(addr, LPI_PROPBASE_SZ); | |
c440a9d9 MZ |
2979 | } |
2980 | ||
11e37d35 | 2981 | static int __init allocate_lpi_tables(void) |
1ac19ca6 | 2982 | { |
c440a9d9 | 2983 | u64 val; |
11e37d35 | 2984 | int err, cpu; |
1ac19ca6 | 2985 | |
c440a9d9 MZ |
2986 | /* |
2987 | * If LPIs are enabled while we run this from the boot CPU, | |
2988 | * flag the RD tables as pre-allocated if the stars do align. | |
2989 | */ | |
2990 | val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); | |
2991 | if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) { | |
2992 | gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | | |
2993 | RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING); | |
2994 | pr_info("GICv3: Using preallocated redistributor tables\n"); | |
2995 | } | |
2996 | ||
11e37d35 MZ |
2997 | err = its_setup_lpi_prop_table(); |
2998 | if (err) | |
2999 | return err; | |
3000 | ||
3001 | /* | |
3002 | * We allocate all the pending tables anyway, as we may have a | |
3003 | * mix of RDs that have had LPIs enabled, and some that | |
3004 | * don't. We'll free the unused ones as each CPU comes online. | |
3005 | */ | |
3006 | for_each_possible_cpu(cpu) { | |
3007 | struct page *pend_page; | |
7c297a2d MZ |
3008 | |
3009 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 | 3010 | if (!pend_page) { |
11e37d35 MZ |
3011 | pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu); |
3012 | return -ENOMEM; | |
1ac19ca6 MZ |
3013 | } |
3014 | ||
11e37d35 | 3015 | gic_data_rdist_cpu(cpu)->pend_page = pend_page; |
1ac19ca6 MZ |
3016 | } |
3017 | ||
11e37d35 MZ |
3018 | return 0; |
3019 | } | |
3020 | ||
af27e416 | 3021 | static u64 read_vpend_dirty_clear(void __iomem *vlpi_base) |
6479450f HG |
3022 | { |
3023 | u32 count = 1000000; /* 1s! */ | |
3024 | bool clean; | |
3025 | u64 val; | |
3026 | ||
6479450f | 3027 | do { |
5186a6cc | 3028 | val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER); |
6479450f HG |
3029 | clean = !(val & GICR_VPENDBASER_Dirty); |
3030 | if (!clean) { | |
3031 | count--; | |
3032 | cpu_relax(); | |
3033 | udelay(1); | |
3034 | } | |
3035 | } while (!clean && count); | |
3036 | ||
af27e416 | 3037 | if (unlikely(!clean)) |
e64fab1a | 3038 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); |
af27e416 MZ |
3039 | |
3040 | return val; | |
3041 | } | |
3042 | ||
3043 | static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set) | |
3044 | { | |
3045 | u64 val; | |
3046 | ||
3047 | /* Make sure we wait until the RD is done with the initial scan */ | |
3048 | val = read_vpend_dirty_clear(vlpi_base); | |
3049 | val &= ~GICR_VPENDBASER_Valid; | |
3050 | val &= ~clr; | |
3051 | val |= set; | |
3052 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
3053 | ||
3054 | val = read_vpend_dirty_clear(vlpi_base); | |
3055 | if (unlikely(val & GICR_VPENDBASER_Dirty)) | |
e64fab1a | 3056 | val |= GICR_VPENDBASER_PendingLast; |
e64fab1a | 3057 | |
6479450f HG |
3058 | return val; |
3059 | } | |
3060 | ||
11e37d35 MZ |
3061 | static void its_cpu_init_lpis(void) |
3062 | { | |
3063 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
3064 | struct page *pend_page; | |
3065 | phys_addr_t paddr; | |
3066 | u64 val, tmp; | |
3067 | ||
c0cdc890 | 3068 | if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) |
11e37d35 MZ |
3069 | return; |
3070 | ||
c440a9d9 MZ |
3071 | val = readl_relaxed(rbase + GICR_CTLR); |
3072 | if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && | |
3073 | (val & GICR_CTLR_ENABLE_LPIS)) { | |
f842ca8e MZ |
3074 | /* |
3075 | * Check that we get the same property table on all | |
3076 | * RDs. If we don't, this is hopeless. | |
3077 | */ | |
3078 | paddr = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
3079 | paddr &= GENMASK_ULL(51, 12); | |
3080 | if (WARN_ON(gic_rdists->prop_table_pa != paddr)) | |
3081 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
3082 | ||
c440a9d9 MZ |
3083 | paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER); |
3084 | paddr &= GENMASK_ULL(51, 16); | |
3085 | ||
5e2c9f9a | 3086 | WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ)); |
d23bc2bc | 3087 | gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED; |
c440a9d9 MZ |
3088 | |
3089 | goto out; | |
3090 | } | |
3091 | ||
11e37d35 MZ |
3092 | pend_page = gic_data_rdist()->pend_page; |
3093 | paddr = page_to_phys(pend_page); | |
3094 | ||
1ac19ca6 | 3095 | /* set PROPBASE */ |
e1a2e201 | 3096 | val = (gic_rdists->prop_table_pa | |
1ac19ca6 | 3097 | GICR_PROPBASER_InnerShareable | |
2fd632a0 | 3098 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
3099 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
3100 | ||
0968a619 VM |
3101 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
3102 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 | 3103 | |
a8707f55 SR |
3104 | if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) |
3105 | tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; | |
3106 | ||
1ac19ca6 | 3107 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { |
241a386c MZ |
3108 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
3109 | /* | |
3110 | * The HW reports non-shareable, we must | |
3111 | * remove the cacheability attributes as | |
3112 | * well. | |
3113 | */ | |
3114 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
3115 | GICR_PROPBASER_CACHEABILITY_MASK); | |
3116 | val |= GICR_PROPBASER_nC; | |
0968a619 | 3117 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 3118 | } |
1ac19ca6 MZ |
3119 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
3120 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
3121 | } | |
3122 | ||
3123 | /* set PENDBASE */ | |
3124 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 3125 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 3126 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 3127 | |
0968a619 VM |
3128 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
3129 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c | 3130 | |
a8707f55 SR |
3131 | if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) |
3132 | tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; | |
3133 | ||
241a386c MZ |
3134 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { |
3135 | /* | |
3136 | * The HW reports non-shareable, we must remove the | |
3137 | * cacheability attributes as well. | |
3138 | */ | |
3139 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
3140 | GICR_PENDBASER_CACHEABILITY_MASK); | |
3141 | val |= GICR_PENDBASER_nC; | |
0968a619 | 3142 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 3143 | } |
1ac19ca6 MZ |
3144 | |
3145 | /* Enable LPIs */ | |
3146 | val = readl_relaxed(rbase + GICR_CTLR); | |
3147 | val |= GICR_CTLR_ENABLE_LPIS; | |
3148 | writel_relaxed(val, rbase + GICR_CTLR); | |
3149 | ||
5e516846 | 3150 | if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { |
6479450f HG |
3151 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
3152 | ||
3153 | /* | |
3154 | * It's possible for CPU to receive VLPIs before it is | |
a359f757 | 3155 | * scheduled as a vPE, especially for the first CPU, and the |
6479450f HG |
3156 | * VLPI with INTID larger than 2^(IDbits+1) will be considered |
3157 | * as out of range and dropped by GIC. | |
3158 | * So we initialize IDbits to known value to avoid VLPI drop. | |
3159 | */ | |
3160 | val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
3161 | pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n", | |
3162 | smp_processor_id(), val); | |
5186a6cc | 3163 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
6479450f HG |
3164 | |
3165 | /* | |
3166 | * Also clear Valid bit of GICR_VPENDBASER, in case some | |
3167 | * ancient programming gets left in and has possibility of | |
3168 | * corrupting memory. | |
3169 | */ | |
e64fab1a | 3170 | val = its_clear_vpend_valid(vlpi_base, 0, 0); |
6479450f HG |
3171 | } |
3172 | ||
5e516846 MZ |
3173 | if (allocate_vpe_l1_table()) { |
3174 | /* | |
3175 | * If the allocation has failed, we're in massive trouble. | |
3176 | * Disable direct injection, and pray that no VM was | |
3177 | * already running... | |
3178 | */ | |
3179 | gic_rdists->has_rvpeid = false; | |
3180 | gic_rdists->has_vlpis = false; | |
3181 | } | |
3182 | ||
1ac19ca6 MZ |
3183 | /* Make sure the GIC has seen the above */ |
3184 | dsb(sy); | |
c440a9d9 | 3185 | out: |
c0cdc890 | 3186 | gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED; |
c440a9d9 | 3187 | pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n", |
11e37d35 | 3188 | smp_processor_id(), |
d23bc2bc VS |
3189 | gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ? |
3190 | "reserved" : "allocated", | |
11e37d35 | 3191 | &paddr); |
1ac19ca6 MZ |
3192 | } |
3193 | ||
920181ce | 3194 | static void its_cpu_init_collection(struct its_node *its) |
1ac19ca6 | 3195 | { |
920181ce DB |
3196 | int cpu = smp_processor_id(); |
3197 | u64 target; | |
1ac19ca6 | 3198 | |
920181ce DB |
3199 | /* avoid cross node collections and its mapping */ |
3200 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
3201 | struct device_node *cpu_node; | |
fbf8f40e | 3202 | |
920181ce DB |
3203 | cpu_node = of_get_cpu_node(cpu, NULL); |
3204 | if (its->numa_node != NUMA_NO_NODE && | |
3205 | its->numa_node != of_node_to_nid(cpu_node)) | |
3206 | return; | |
3207 | } | |
fbf8f40e | 3208 | |
920181ce DB |
3209 | /* |
3210 | * We now have to bind each collection to its target | |
3211 | * redistributor. | |
3212 | */ | |
3213 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { | |
1ac19ca6 | 3214 | /* |
920181ce | 3215 | * This ITS wants the physical address of the |
1ac19ca6 MZ |
3216 | * redistributor. |
3217 | */ | |
920181ce DB |
3218 | target = gic_data_rdist()->phys_base; |
3219 | } else { | |
3220 | /* This ITS wants a linear CPU number. */ | |
3221 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); | |
3222 | target = GICR_TYPER_CPU_NUMBER(target) << 16; | |
3223 | } | |
1ac19ca6 | 3224 | |
920181ce DB |
3225 | /* Perform collection mapping */ |
3226 | its->collections[cpu].target_address = target; | |
3227 | its->collections[cpu].col_id = cpu; | |
1ac19ca6 | 3228 | |
920181ce DB |
3229 | its_send_mapc(its, &its->collections[cpu], 1); |
3230 | its_send_invall(its, &its->collections[cpu]); | |
3231 | } | |
3232 | ||
3233 | static void its_cpu_init_collections(void) | |
3234 | { | |
3235 | struct its_node *its; | |
3236 | ||
a8db7456 | 3237 | raw_spin_lock(&its_lock); |
920181ce DB |
3238 | |
3239 | list_for_each_entry(its, &its_nodes, entry) | |
3240 | its_cpu_init_collection(its); | |
1ac19ca6 | 3241 | |
a8db7456 | 3242 | raw_spin_unlock(&its_lock); |
1ac19ca6 | 3243 | } |
84a6a2e7 MZ |
3244 | |
3245 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
3246 | { | |
3247 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 3248 | unsigned long flags; |
84a6a2e7 | 3249 | |
3e39e8f5 | 3250 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
3251 | |
3252 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
3253 | if (tmp->device_id == dev_id) { | |
3254 | its_dev = tmp; | |
3255 | break; | |
3256 | } | |
3257 | } | |
3258 | ||
3e39e8f5 | 3259 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
3260 | |
3261 | return its_dev; | |
3262 | } | |
3263 | ||
466b7d16 SD |
3264 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
3265 | { | |
3266 | int i; | |
3267 | ||
3268 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
3269 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
3270 | return &its->tables[i]; | |
3271 | } | |
3272 | ||
3273 | return NULL; | |
3274 | } | |
3275 | ||
539d3782 SD |
3276 | static bool its_alloc_table_entry(struct its_node *its, |
3277 | struct its_baser *baser, u32 id) | |
3faf24ea | 3278 | { |
3faf24ea SD |
3279 | struct page *page; |
3280 | u32 esz, idx; | |
3281 | __le64 *table; | |
3282 | ||
3faf24ea SD |
3283 | /* Don't allow device id that exceeds single, flat table limit */ |
3284 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
3285 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 3286 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
3287 | |
3288 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 3289 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
3290 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
3291 | return false; | |
3292 | ||
3293 | table = baser->base; | |
3294 | ||
3295 | /* Allocate memory for 2nd level table */ | |
3296 | if (!table[idx]) { | |
539d3782 SD |
3297 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
3298 | get_order(baser->psz)); | |
3faf24ea SD |
3299 | if (!page) |
3300 | return false; | |
3301 | ||
3302 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
3303 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 3304 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
3305 | |
3306 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
3307 | ||
3308 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
3309 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 3310 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
3311 | |
3312 | /* Ensure updated table contents are visible to ITS hardware */ | |
3313 | dsb(sy); | |
3314 | } | |
3315 | ||
3316 | return true; | |
3317 | } | |
3318 | ||
70cc81ed MZ |
3319 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
3320 | { | |
3321 | struct its_baser *baser; | |
3322 | ||
3323 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
3324 | ||
3325 | /* Don't allow device id that exceeds ITS hardware limit */ | |
3326 | if (!baser) | |
576a8342 | 3327 | return (ilog2(dev_id) < device_ids(its)); |
70cc81ed | 3328 | |
539d3782 | 3329 | return its_alloc_table_entry(its, baser, dev_id); |
70cc81ed MZ |
3330 | } |
3331 | ||
7d75bbb4 MZ |
3332 | static bool its_alloc_vpe_table(u32 vpe_id) |
3333 | { | |
3334 | struct its_node *its; | |
4e6437f1 | 3335 | int cpu; |
7d75bbb4 MZ |
3336 | |
3337 | /* | |
3338 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
3339 | * could try and only do it on ITSs corresponding to devices | |
3340 | * that have interrupts targeted at this VPE, but the | |
3341 | * complexity becomes crazy (and you have tons of memory | |
3342 | * anyway, right?). | |
3343 | */ | |
3344 | list_for_each_entry(its, &its_nodes, entry) { | |
3345 | struct its_baser *baser; | |
3346 | ||
0dd57fed | 3347 | if (!is_v4(its)) |
7d75bbb4 | 3348 | continue; |
3faf24ea | 3349 | |
7d75bbb4 MZ |
3350 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
3351 | if (!baser) | |
3352 | return false; | |
3faf24ea | 3353 | |
539d3782 | 3354 | if (!its_alloc_table_entry(its, baser, vpe_id)) |
7d75bbb4 | 3355 | return false; |
3faf24ea SD |
3356 | } |
3357 | ||
4e6437f1 ZY |
3358 | /* Non v4.1? No need to iterate RDs and go back early. */ |
3359 | if (!gic_rdists->has_rvpeid) | |
3360 | return true; | |
3361 | ||
3362 | /* | |
3363 | * Make sure the L2 tables are allocated for all copies of | |
3364 | * the L1 table on *all* v4.1 RDs. | |
3365 | */ | |
3366 | for_each_possible_cpu(cpu) { | |
3367 | if (!allocate_vpe_l2_table(cpu, vpe_id)) | |
3368 | return false; | |
3369 | } | |
3370 | ||
3faf24ea SD |
3371 | return true; |
3372 | } | |
3373 | ||
84a6a2e7 | 3374 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 3375 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
3376 | { |
3377 | struct its_device *dev; | |
93f94ea0 | 3378 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 3379 | unsigned long flags; |
591e5bec | 3380 | u16 *col_map = NULL; |
84a6a2e7 MZ |
3381 | void *itt; |
3382 | int lpi_base; | |
3383 | int nr_lpis; | |
c8481267 | 3384 | int nr_ites; |
84a6a2e7 MZ |
3385 | int sz; |
3386 | ||
3faf24ea | 3387 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
3388 | return NULL; |
3389 | ||
147c8f37 MZ |
3390 | if (WARN_ON(!is_power_of_2(nvecs))) |
3391 | nvecs = roundup_pow_of_two(nvecs); | |
3392 | ||
84a6a2e7 | 3393 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 | 3394 | /* |
147c8f37 MZ |
3395 | * Even if the device wants a single LPI, the ITT must be |
3396 | * sized as a power of two (and you need at least one bit...). | |
c8481267 | 3397 | */ |
147c8f37 | 3398 | nr_ites = max(2, nvecs); |
ffedbf0c | 3399 | sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); |
84a6a2e7 | 3400 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
539d3782 | 3401 | itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); |
93f94ea0 | 3402 | if (alloc_lpis) { |
38dd7c49 | 3403 | lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); |
93f94ea0 | 3404 | if (lpi_map) |
6396bb22 | 3405 | col_map = kcalloc(nr_lpis, sizeof(*col_map), |
93f94ea0 MZ |
3406 | GFP_KERNEL); |
3407 | } else { | |
6396bb22 | 3408 | col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL); |
93f94ea0 MZ |
3409 | nr_lpis = 0; |
3410 | lpi_base = 0; | |
3411 | } | |
84a6a2e7 | 3412 | |
93f94ea0 | 3413 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
3414 | kfree(dev); |
3415 | kfree(itt); | |
ff5fe886 | 3416 | bitmap_free(lpi_map); |
591e5bec | 3417 | kfree(col_map); |
84a6a2e7 MZ |
3418 | return NULL; |
3419 | } | |
3420 | ||
328191c0 | 3421 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 3422 | |
84a6a2e7 MZ |
3423 | dev->its = its; |
3424 | dev->itt = itt; | |
c8481267 | 3425 | dev->nr_ites = nr_ites; |
591e5bec MZ |
3426 | dev->event_map.lpi_map = lpi_map; |
3427 | dev->event_map.col_map = col_map; | |
3428 | dev->event_map.lpi_base = lpi_base; | |
3429 | dev->event_map.nr_lpis = nr_lpis; | |
11635fa2 | 3430 | raw_spin_lock_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
3431 | dev->device_id = dev_id; |
3432 | INIT_LIST_HEAD(&dev->entry); | |
3433 | ||
3e39e8f5 | 3434 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 3435 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 3436 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 3437 | |
84a6a2e7 MZ |
3438 | /* Map device to its ITT */ |
3439 | its_send_mapd(dev, 1); | |
3440 | ||
3441 | return dev; | |
3442 | } | |
3443 | ||
3444 | static void its_free_device(struct its_device *its_dev) | |
3445 | { | |
3e39e8f5 MZ |
3446 | unsigned long flags; |
3447 | ||
3448 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 3449 | list_del(&its_dev->entry); |
3e39e8f5 | 3450 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
898aa5ce | 3451 | kfree(its_dev->event_map.col_map); |
84a6a2e7 MZ |
3452 | kfree(its_dev->itt); |
3453 | kfree(its_dev); | |
3454 | } | |
b48ac83d | 3455 | |
8208d170 | 3456 | static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq) |
b48ac83d MZ |
3457 | { |
3458 | int idx; | |
3459 | ||
342be106 | 3460 | /* Find a free LPI region in lpi_map and allocate them. */ |
8208d170 MZ |
3461 | idx = bitmap_find_free_region(dev->event_map.lpi_map, |
3462 | dev->event_map.nr_lpis, | |
3463 | get_count_order(nvecs)); | |
3464 | if (idx < 0) | |
b48ac83d MZ |
3465 | return -ENOSPC; |
3466 | ||
591e5bec | 3467 | *hwirq = dev->event_map.lpi_base + idx; |
b48ac83d | 3468 | |
b48ac83d MZ |
3469 | return 0; |
3470 | } | |
3471 | ||
54456db9 MZ |
3472 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
3473 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 3474 | { |
b48ac83d | 3475 | struct its_node *its; |
b48ac83d | 3476 | struct its_device *its_dev; |
54456db9 MZ |
3477 | struct msi_domain_info *msi_info; |
3478 | u32 dev_id; | |
9791ec7d | 3479 | int err = 0; |
54456db9 MZ |
3480 | |
3481 | /* | |
a7c90f51 | 3482 | * We ignore "dev" entirely, and rely on the dev_id that has |
54456db9 MZ |
3483 | * been passed via the scratchpad. This limits this domain's |
3484 | * usefulness to upper layers that definitely know that they | |
3485 | * are built on top of the ITS. | |
3486 | */ | |
3487 | dev_id = info->scratchpad[0].ul; | |
3488 | ||
3489 | msi_info = msi_get_domain_info(domain); | |
3490 | its = msi_info->data; | |
e8137f4f | 3491 | |
20b3d54e MZ |
3492 | if (!gic_rdists->has_direct_lpi && |
3493 | vpe_proxy.dev && | |
3494 | vpe_proxy.dev->its == its && | |
3495 | dev_id == vpe_proxy.dev->device_id) { | |
3496 | /* Bad luck. Get yourself a better implementation */ | |
3497 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
3498 | dev_id); | |
3499 | return -EINVAL; | |
3500 | } | |
3501 | ||
9791ec7d | 3502 | mutex_lock(&its->dev_alloc_lock); |
f130420e | 3503 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
3504 | if (its_dev) { |
3505 | /* | |
3506 | * We already have seen this ID, probably through | |
3507 | * another alias (PCI bridge of some sort). No need to | |
3508 | * create the device. | |
3509 | */ | |
9791ec7d | 3510 | its_dev->shared = true; |
f130420e | 3511 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
3512 | goto out; |
3513 | } | |
b48ac83d | 3514 | |
93f94ea0 | 3515 | its_dev = its_create_device(its, dev_id, nvec, true); |
9791ec7d MZ |
3516 | if (!its_dev) { |
3517 | err = -ENOMEM; | |
3518 | goto out; | |
3519 | } | |
b48ac83d | 3520 | |
5fe71d27 MZ |
3521 | if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE) |
3522 | its_dev->shared = true; | |
3523 | ||
f130420e | 3524 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 3525 | out: |
9791ec7d | 3526 | mutex_unlock(&its->dev_alloc_lock); |
b48ac83d | 3527 | info->scratchpad[0].ptr = its_dev; |
9791ec7d | 3528 | return err; |
b48ac83d MZ |
3529 | } |
3530 | ||
54456db9 MZ |
3531 | static struct msi_domain_ops its_msi_domain_ops = { |
3532 | .msi_prepare = its_msi_prepare, | |
3533 | }; | |
3534 | ||
b48ac83d MZ |
3535 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
3536 | unsigned int virq, | |
3537 | irq_hw_number_t hwirq) | |
3538 | { | |
f833f57f MZ |
3539 | struct irq_fwspec fwspec; |
3540 | ||
3541 | if (irq_domain_get_of_node(domain->parent)) { | |
3542 | fwspec.fwnode = domain->parent->fwnode; | |
3543 | fwspec.param_count = 3; | |
3544 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
3545 | fwspec.param[1] = hwirq; | |
3546 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
3547 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
3548 | fwspec.fwnode = domain->parent->fwnode; | |
3549 | fwspec.param_count = 2; | |
3550 | fwspec.param[0] = hwirq; | |
3551 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
3552 | } else { |
3553 | return -EINVAL; | |
3554 | } | |
b48ac83d | 3555 | |
f833f57f | 3556 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
3557 | } |
3558 | ||
3559 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
3560 | unsigned int nr_irqs, void *args) | |
3561 | { | |
3562 | msi_alloc_info_t *info = args; | |
3563 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
35ae7df2 | 3564 | struct its_node *its = its_dev->its; |
f0c7baca | 3565 | struct irq_data *irqd; |
b48ac83d MZ |
3566 | irq_hw_number_t hwirq; |
3567 | int err; | |
3568 | int i; | |
3569 | ||
8208d170 MZ |
3570 | err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq); |
3571 | if (err) | |
3572 | return err; | |
b48ac83d | 3573 | |
35ae7df2 JG |
3574 | err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); |
3575 | if (err) | |
3576 | return err; | |
3577 | ||
8208d170 MZ |
3578 | for (i = 0; i < nr_irqs; i++) { |
3579 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); | |
b48ac83d MZ |
3580 | if (err) |
3581 | return err; | |
3582 | ||
3583 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
8208d170 | 3584 | hwirq + i, &its_irq_chip, its_dev); |
f0c7baca TG |
3585 | irqd = irq_get_irq_data(virq + i); |
3586 | irqd_set_single_target(irqd); | |
3587 | irqd_set_affinity_on_activate(irqd); | |
f130420e | 3588 | pr_debug("ID:%d pID:%d vID:%d\n", |
8208d170 MZ |
3589 | (int)(hwirq + i - its_dev->event_map.lpi_base), |
3590 | (int)(hwirq + i), virq + i); | |
b48ac83d MZ |
3591 | } |
3592 | ||
3593 | return 0; | |
3594 | } | |
3595 | ||
72491643 | 3596 | static int its_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 3597 | struct irq_data *d, bool reserve) |
aca268df MZ |
3598 | { |
3599 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3600 | u32 event = its_get_event_id(d); | |
0d224d35 | 3601 | int cpu; |
fbf8f40e | 3602 | |
c5d6082d MZ |
3603 | cpu = its_select_cpu(d, cpu_online_mask); |
3604 | if (cpu < 0 || cpu >= nr_cpu_ids) | |
3605 | return -EINVAL; | |
c1797b11 | 3606 | |
2f13ff1d | 3607 | its_inc_lpi_count(d, cpu); |
0d224d35 MZ |
3608 | its_dev->event_map.col_map[event] = cpu; |
3609 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 3610 | |
aca268df | 3611 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 3612 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 3613 | return 0; |
aca268df MZ |
3614 | } |
3615 | ||
3616 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
3617 | struct irq_data *d) | |
3618 | { | |
3619 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
3620 | u32 event = its_get_event_id(d); | |
3621 | ||
2f13ff1d | 3622 | its_dec_lpi_count(d, its_dev->event_map.col_map[event]); |
aca268df MZ |
3623 | /* Stop the delivery of interrupts */ |
3624 | its_send_discard(its_dev, event); | |
3625 | } | |
3626 | ||
b48ac83d MZ |
3627 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
3628 | unsigned int nr_irqs) | |
3629 | { | |
3630 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
3631 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
9791ec7d | 3632 | struct its_node *its = its_dev->its; |
b48ac83d MZ |
3633 | int i; |
3634 | ||
c9c96e30 MZ |
3635 | bitmap_release_region(its_dev->event_map.lpi_map, |
3636 | its_get_event_id(irq_domain_get_irq_data(domain, virq)), | |
3637 | get_count_order(nr_irqs)); | |
3638 | ||
b48ac83d MZ |
3639 | for (i = 0; i < nr_irqs; i++) { |
3640 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
3641 | virq + i); | |
b48ac83d | 3642 | /* Nuke the entry in the domain */ |
2da39949 | 3643 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
3644 | } |
3645 | ||
9791ec7d MZ |
3646 | mutex_lock(&its->dev_alloc_lock); |
3647 | ||
3648 | /* | |
3649 | * If all interrupts have been freed, start mopping the | |
a359f757 | 3650 | * floor. This is conditioned on the device not being shared. |
9791ec7d MZ |
3651 | */ |
3652 | if (!its_dev->shared && | |
3653 | bitmap_empty(its_dev->event_map.lpi_map, | |
591e5bec | 3654 | its_dev->event_map.nr_lpis)) { |
38dd7c49 MZ |
3655 | its_lpi_free(its_dev->event_map.lpi_map, |
3656 | its_dev->event_map.lpi_base, | |
3657 | its_dev->event_map.nr_lpis); | |
b48ac83d MZ |
3658 | |
3659 | /* Unmap device/itt */ | |
3660 | its_send_mapd(its_dev, 0); | |
3661 | its_free_device(its_dev); | |
3662 | } | |
3663 | ||
9791ec7d MZ |
3664 | mutex_unlock(&its->dev_alloc_lock); |
3665 | ||
b48ac83d MZ |
3666 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
3667 | } | |
3668 | ||
3669 | static const struct irq_domain_ops its_domain_ops = { | |
3670 | .alloc = its_irq_domain_alloc, | |
3671 | .free = its_irq_domain_free, | |
aca268df MZ |
3672 | .activate = its_irq_domain_activate, |
3673 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 3674 | }; |
4c21f3c2 | 3675 | |
20b3d54e MZ |
3676 | /* |
3677 | * This is insane. | |
3678 | * | |
0684c704 | 3679 | * If a GICv4.0 doesn't implement Direct LPIs (which is extremely |
20b3d54e MZ |
3680 | * likely), the only way to perform an invalidate is to use a fake |
3681 | * device to issue an INV command, implying that the LPI has first | |
3682 | * been mapped to some event on that device. Since this is not exactly | |
3683 | * cheap, we try to keep that mapping around as long as possible, and | |
3684 | * only issue an UNMAP if we're short on available slots. | |
3685 | * | |
3686 | * Broken by design(tm). | |
0684c704 MZ |
3687 | * |
3688 | * GICv4.1, on the other hand, mandates that we're able to invalidate | |
3689 | * by writing to a MMIO register. It doesn't implement the whole of | |
3690 | * DirectLPI, but that's good enough. And most of the time, we don't | |
3691 | * even have to invalidate anything, as the redistributor can be told | |
3692 | * whether to generate a doorbell or not (we thus leave it enabled, | |
3693 | * always). | |
20b3d54e MZ |
3694 | */ |
3695 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
3696 | { | |
0684c704 MZ |
3697 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3698 | if (gic_rdists->has_rvpeid) | |
3699 | return; | |
3700 | ||
20b3d54e MZ |
3701 | /* Already unmapped? */ |
3702 | if (vpe->vpe_proxy_event == -1) | |
3703 | return; | |
3704 | ||
3705 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3706 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
3707 | ||
3708 | /* | |
3709 | * We don't track empty slots at all, so let's move the | |
3710 | * next_victim pointer if we can quickly reuse that slot | |
3711 | * instead of nuking an existing entry. Not clear that this is | |
3712 | * always a win though, and this might just generate a ripple | |
3713 | * effect... Let's just hope VPEs don't migrate too often. | |
3714 | */ | |
3715 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3716 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
3717 | ||
3718 | vpe->vpe_proxy_event = -1; | |
3719 | } | |
3720 | ||
3721 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
3722 | { | |
0684c704 MZ |
3723 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3724 | if (gic_rdists->has_rvpeid) | |
3725 | return; | |
3726 | ||
20b3d54e MZ |
3727 | if (!gic_rdists->has_direct_lpi) { |
3728 | unsigned long flags; | |
3729 | ||
3730 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3731 | its_vpe_db_proxy_unmap_locked(vpe); | |
3732 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3733 | } | |
3734 | } | |
3735 | ||
3736 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
3737 | { | |
0684c704 MZ |
3738 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3739 | if (gic_rdists->has_rvpeid) | |
3740 | return; | |
3741 | ||
20b3d54e MZ |
3742 | /* Already mapped? */ |
3743 | if (vpe->vpe_proxy_event != -1) | |
3744 | return; | |
3745 | ||
3746 | /* This slot was already allocated. Kick the other VPE out. */ | |
3747 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
3748 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
3749 | ||
3750 | /* Map the new VPE instead */ | |
3751 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
3752 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
3753 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
3754 | ||
3755 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
3756 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
3757 | } | |
3758 | ||
958b90d1 MZ |
3759 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
3760 | { | |
3761 | unsigned long flags; | |
3762 | struct its_collection *target_col; | |
3763 | ||
0684c704 MZ |
3764 | /* GICv4.1 doesn't use a proxy, so nothing to do here */ |
3765 | if (gic_rdists->has_rvpeid) | |
3766 | return; | |
3767 | ||
958b90d1 MZ |
3768 | if (gic_rdists->has_direct_lpi) { |
3769 | void __iomem *rdbase; | |
3770 | ||
3771 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
3772 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 3773 | wait_for_syncr(rdbase); |
958b90d1 MZ |
3774 | |
3775 | return; | |
3776 | } | |
3777 | ||
3778 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3779 | ||
3780 | its_vpe_db_proxy_map_locked(vpe); | |
3781 | ||
3782 | target_col = &vpe_proxy.dev->its->collections[to]; | |
3783 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
3784 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
3785 | ||
3786 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3787 | } | |
3788 | ||
3171a47a MZ |
3789 | static int its_vpe_set_affinity(struct irq_data *d, |
3790 | const struct cpumask *mask_val, | |
3791 | bool force) | |
3792 | { | |
3793 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
dd3f050a | 3794 | int from, cpu = cpumask_first(mask_val); |
f3a05921 | 3795 | unsigned long flags; |
3171a47a MZ |
3796 | |
3797 | /* | |
3798 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 3799 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
3800 | * into the proxy device, we need to move the doorbell |
3801 | * interrupt to its new location. | |
f3a05921 MZ |
3802 | * |
3803 | * Another thing is that changing the affinity of a vPE affects | |
3804 | * *other interrupts* such as all the vLPIs that are routed to | |
3805 | * this vPE. This means that the irq_desc lock is not enough to | |
3806 | * protect us, and that we must ensure nobody samples vpe->col_idx | |
3807 | * during the update, hence the lock below which must also be | |
3808 | * taken on any vLPI handling path that evaluates vpe->col_idx. | |
3171a47a | 3809 | */ |
f3a05921 MZ |
3810 | from = vpe_to_cpuid_lock(vpe, &flags); |
3811 | if (from == cpu) | |
dd3f050a | 3812 | goto out; |
958b90d1 | 3813 | |
dd3f050a MZ |
3814 | vpe->col_idx = cpu; |
3815 | ||
3816 | /* | |
3817 | * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD | |
3818 | * is sharing its VPE table with the current one. | |
3819 | */ | |
3820 | if (gic_data_rdist_cpu(cpu)->vpe_table_mask && | |
3821 | cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask)) | |
3822 | goto out; | |
3171a47a | 3823 | |
dd3f050a MZ |
3824 | its_send_vmovp(vpe); |
3825 | its_vpe_db_proxy_move(vpe, from, cpu); | |
3826 | ||
3827 | out: | |
44c4c25e | 3828 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
f3a05921 | 3829 | vpe_to_cpuid_unlock(vpe, flags); |
44c4c25e | 3830 | |
3171a47a MZ |
3831 | return IRQ_SET_MASK_OK_DONE; |
3832 | } | |
3833 | ||
96806229 MZ |
3834 | static void its_wait_vpt_parse_complete(void) |
3835 | { | |
3836 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
3837 | u64 val; | |
3838 | ||
3839 | if (!gic_rdists->has_vpend_valid_dirty) | |
3840 | return; | |
3841 | ||
31dbb6b1 ZY |
3842 | WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER, |
3843 | val, | |
3844 | !(val & GICR_VPENDBASER_Dirty), | |
0b394982 | 3845 | 1, 500)); |
96806229 MZ |
3846 | } |
3847 | ||
e643d803 MZ |
3848 | static void its_vpe_schedule(struct its_vpe *vpe) |
3849 | { | |
50c33097 | 3850 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3851 | u64 val; |
3852 | ||
3853 | /* Schedule the VPE */ | |
3854 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
3855 | GENMASK_ULL(51, 12); | |
3856 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
3857 | val |= GICR_VPROPBASER_RaWb; | |
3858 | val |= GICR_VPROPBASER_InnerShareable; | |
5186a6cc | 3859 | gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); |
e643d803 MZ |
3860 | |
3861 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
3862 | GENMASK_ULL(51, 16); | |
3863 | val |= GICR_VPENDBASER_RaWaWb; | |
b2cb11f4 | 3864 | val |= GICR_VPENDBASER_InnerShareable; |
e643d803 MZ |
3865 | /* |
3866 | * There is no good way of finding out if the pending table is | |
3867 | * empty as we can race against the doorbell interrupt very | |
3868 | * easily. So in the end, vpe->pending_last is only an | |
3869 | * indication that the vcpu has something pending, not one | |
3870 | * that the pending table is empty. A good implementation | |
3871 | * would be able to read its coarse map pretty quickly anyway, | |
3872 | * making this a tolerable issue. | |
3873 | */ | |
3874 | val |= GICR_VPENDBASER_PendingLast; | |
3875 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
3876 | val |= GICR_VPENDBASER_Valid; | |
5186a6cc | 3877 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); |
e643d803 MZ |
3878 | } |
3879 | ||
3880 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
3881 | { | |
50c33097 | 3882 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); |
e643d803 MZ |
3883 | u64 val; |
3884 | ||
e64fab1a | 3885 | val = its_clear_vpend_valid(vlpi_base, 0, 0); |
e643d803 | 3886 | |
e64fab1a MZ |
3887 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); |
3888 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
e643d803 MZ |
3889 | } |
3890 | ||
40619a2e MZ |
3891 | static void its_vpe_invall(struct its_vpe *vpe) |
3892 | { | |
3893 | struct its_node *its; | |
3894 | ||
3895 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 3896 | if (!is_v4(its)) |
40619a2e MZ |
3897 | continue; |
3898 | ||
2247e1bf MZ |
3899 | if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) |
3900 | continue; | |
3901 | ||
3c1cceeb MZ |
3902 | /* |
3903 | * Sending a VINVALL to a single ITS is enough, as all | |
3904 | * we need is to reach the redistributors. | |
3905 | */ | |
40619a2e | 3906 | its_send_vinvall(its, vpe); |
3c1cceeb | 3907 | return; |
40619a2e MZ |
3908 | } |
3909 | } | |
3910 | ||
e643d803 MZ |
3911 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
3912 | { | |
3913 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3914 | struct its_cmd_info *info = vcpu_info; | |
3915 | ||
3916 | switch (info->cmd_type) { | |
3917 | case SCHEDULE_VPE: | |
3918 | its_vpe_schedule(vpe); | |
3919 | return 0; | |
3920 | ||
3921 | case DESCHEDULE_VPE: | |
3922 | its_vpe_deschedule(vpe); | |
3923 | return 0; | |
3924 | ||
57e3cebd SL |
3925 | case COMMIT_VPE: |
3926 | its_wait_vpt_parse_complete(); | |
3927 | return 0; | |
3928 | ||
5e2f7642 | 3929 | case INVALL_VPE: |
40619a2e | 3930 | its_vpe_invall(vpe); |
5e2f7642 MZ |
3931 | return 0; |
3932 | ||
e643d803 MZ |
3933 | default: |
3934 | return -EINVAL; | |
3935 | } | |
3936 | } | |
3937 | ||
20b3d54e MZ |
3938 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
3939 | void (*cmd)(struct its_device *, u32)) | |
3940 | { | |
3941 | unsigned long flags; | |
3942 | ||
3943 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
3944 | ||
3945 | its_vpe_db_proxy_map_locked(vpe); | |
3946 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
3947 | ||
3948 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
3949 | } | |
3950 | ||
f6a91da7 MZ |
3951 | static void its_vpe_send_inv(struct irq_data *d) |
3952 | { | |
3953 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 3954 | |
20b3d54e MZ |
3955 | if (gic_rdists->has_direct_lpi) { |
3956 | void __iomem *rdbase; | |
3957 | ||
425c09be | 3958 | /* Target the redistributor this VPE is currently known on */ |
9058a4e9 | 3959 | raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
20b3d54e | 3960 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; |
425c09be | 3961 | gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); |
2f4f064b | 3962 | wait_for_syncr(rdbase); |
9058a4e9 | 3963 | raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); |
20b3d54e MZ |
3964 | } else { |
3965 | its_vpe_send_cmd(vpe, its_send_inv); | |
3966 | } | |
f6a91da7 MZ |
3967 | } |
3968 | ||
3969 | static void its_vpe_mask_irq(struct irq_data *d) | |
3970 | { | |
3971 | /* | |
3972 | * We need to unmask the LPI, which is described by the parent | |
3973 | * irq_data. Instead of calling into the parent (which won't | |
3974 | * exactly do the right thing, let's simply use the | |
3975 | * parent_data pointer. Yes, I'm naughty. | |
3976 | */ | |
3977 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
3978 | its_vpe_send_inv(d); | |
3979 | } | |
3980 | ||
3981 | static void its_vpe_unmask_irq(struct irq_data *d) | |
3982 | { | |
3983 | /* Same hack as above... */ | |
3984 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
3985 | its_vpe_send_inv(d); | |
3986 | } | |
3987 | ||
e57a3e28 MZ |
3988 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
3989 | enum irqchip_irq_state which, | |
3990 | bool state) | |
3991 | { | |
3992 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
3993 | ||
3994 | if (which != IRQCHIP_STATE_PENDING) | |
3995 | return -EINVAL; | |
3996 | ||
3997 | if (gic_rdists->has_direct_lpi) { | |
3998 | void __iomem *rdbase; | |
3999 | ||
4000 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
4001 | if (state) { | |
4002 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
4003 | } else { | |
4004 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2f4f064b | 4005 | wait_for_syncr(rdbase); |
e57a3e28 MZ |
4006 | } |
4007 | } else { | |
4008 | if (state) | |
4009 | its_vpe_send_cmd(vpe, its_send_int); | |
4010 | else | |
4011 | its_vpe_send_cmd(vpe, its_send_clear); | |
4012 | } | |
4013 | ||
4014 | return 0; | |
4015 | } | |
4016 | ||
7809f701 MZ |
4017 | static int its_vpe_retrigger(struct irq_data *d) |
4018 | { | |
4019 | return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true); | |
4020 | } | |
4021 | ||
8fff27ae MZ |
4022 | static struct irq_chip its_vpe_irq_chip = { |
4023 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
4024 | .irq_mask = its_vpe_mask_irq, |
4025 | .irq_unmask = its_vpe_unmask_irq, | |
4026 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 4027 | .irq_set_affinity = its_vpe_set_affinity, |
7809f701 | 4028 | .irq_retrigger = its_vpe_retrigger, |
e57a3e28 | 4029 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 4030 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
4031 | }; |
4032 | ||
d97c97ba MZ |
4033 | static struct its_node *find_4_1_its(void) |
4034 | { | |
4035 | static struct its_node *its = NULL; | |
4036 | ||
4037 | if (!its) { | |
4038 | list_for_each_entry(its, &its_nodes, entry) { | |
4039 | if (is_v4_1(its)) | |
4040 | return its; | |
4041 | } | |
4042 | ||
4043 | /* Oops? */ | |
4044 | its = NULL; | |
4045 | } | |
4046 | ||
4047 | return its; | |
4048 | } | |
4049 | ||
4050 | static void its_vpe_4_1_send_inv(struct irq_data *d) | |
4051 | { | |
4052 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4053 | struct its_node *its; | |
4054 | ||
4055 | /* | |
4056 | * GICv4.1 wants doorbells to be invalidated using the | |
4057 | * INVDB command in order to be broadcast to all RDs. Send | |
4058 | * it to the first valid ITS, and let the HW do its magic. | |
4059 | */ | |
4060 | its = find_4_1_its(); | |
4061 | if (its) | |
4062 | its_send_invdb(its, vpe); | |
4063 | } | |
4064 | ||
4065 | static void its_vpe_4_1_mask_irq(struct irq_data *d) | |
4066 | { | |
4067 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
4068 | its_vpe_4_1_send_inv(d); | |
4069 | } | |
4070 | ||
4071 | static void its_vpe_4_1_unmask_irq(struct irq_data *d) | |
4072 | { | |
4073 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
4074 | its_vpe_4_1_send_inv(d); | |
4075 | } | |
4076 | ||
91bf6395 MZ |
4077 | static void its_vpe_4_1_schedule(struct its_vpe *vpe, |
4078 | struct its_cmd_info *info) | |
4079 | { | |
4080 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
4081 | u64 val = 0; | |
4082 | ||
4083 | /* Schedule the VPE */ | |
4084 | val |= GICR_VPENDBASER_Valid; | |
4085 | val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; | |
4086 | val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; | |
4087 | val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); | |
4088 | ||
5186a6cc | 4089 | gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); |
91bf6395 MZ |
4090 | } |
4091 | ||
e64fab1a MZ |
4092 | static void its_vpe_4_1_deschedule(struct its_vpe *vpe, |
4093 | struct its_cmd_info *info) | |
4094 | { | |
4095 | void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); | |
4096 | u64 val; | |
4097 | ||
4098 | if (info->req_db) { | |
a3f574cd MZ |
4099 | unsigned long flags; |
4100 | ||
e64fab1a MZ |
4101 | /* |
4102 | * vPE is going to block: make the vPE non-resident with | |
4103 | * PendingLast clear and DB set. The GIC guarantees that if | |
4104 | * we read-back PendingLast clear, then a doorbell will be | |
4105 | * delivered when an interrupt comes. | |
a3f574cd MZ |
4106 | * |
4107 | * Note the locking to deal with the concurrent update of | |
4108 | * pending_last from the doorbell interrupt handler that can | |
4109 | * run concurrently. | |
e64fab1a | 4110 | */ |
a3f574cd | 4111 | raw_spin_lock_irqsave(&vpe->vpe_lock, flags); |
e64fab1a MZ |
4112 | val = its_clear_vpend_valid(vlpi_base, |
4113 | GICR_VPENDBASER_PendingLast, | |
4114 | GICR_VPENDBASER_4_1_DB); | |
4115 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
a3f574cd | 4116 | raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); |
e64fab1a MZ |
4117 | } else { |
4118 | /* | |
4119 | * We're not blocking, so just make the vPE non-resident | |
4120 | * with PendingLast set, indicating that we'll be back. | |
4121 | */ | |
4122 | val = its_clear_vpend_valid(vlpi_base, | |
4123 | 0, | |
4124 | GICR_VPENDBASER_PendingLast); | |
4125 | vpe->pending_last = true; | |
4126 | } | |
4127 | } | |
4128 | ||
b4a4bd0f MZ |
4129 | static void its_vpe_4_1_invall(struct its_vpe *vpe) |
4130 | { | |
4131 | void __iomem *rdbase; | |
3af9571c | 4132 | unsigned long flags; |
b4a4bd0f | 4133 | u64 val; |
3af9571c | 4134 | int cpu; |
b4a4bd0f MZ |
4135 | |
4136 | val = GICR_INVALLR_V; | |
4137 | val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); | |
4138 | ||
4139 | /* Target the redistributor this vPE is currently known on */ | |
3af9571c ZY |
4140 | cpu = vpe_to_cpuid_lock(vpe, &flags); |
4141 | raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); | |
4142 | rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; | |
b4a4bd0f | 4143 | gic_write_lpir(val, rdbase + GICR_INVALLR); |
b978c25f ZY |
4144 | |
4145 | wait_for_syncr(rdbase); | |
3af9571c ZY |
4146 | raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); |
4147 | vpe_to_cpuid_unlock(vpe, flags); | |
b4a4bd0f MZ |
4148 | } |
4149 | ||
29c647f3 MZ |
4150 | static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
4151 | { | |
91bf6395 | 4152 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); |
29c647f3 MZ |
4153 | struct its_cmd_info *info = vcpu_info; |
4154 | ||
4155 | switch (info->cmd_type) { | |
4156 | case SCHEDULE_VPE: | |
91bf6395 | 4157 | its_vpe_4_1_schedule(vpe, info); |
29c647f3 MZ |
4158 | return 0; |
4159 | ||
4160 | case DESCHEDULE_VPE: | |
e64fab1a | 4161 | its_vpe_4_1_deschedule(vpe, info); |
29c647f3 MZ |
4162 | return 0; |
4163 | ||
57e3cebd SL |
4164 | case COMMIT_VPE: |
4165 | its_wait_vpt_parse_complete(); | |
4166 | return 0; | |
4167 | ||
29c647f3 | 4168 | case INVALL_VPE: |
b4a4bd0f | 4169 | its_vpe_4_1_invall(vpe); |
29c647f3 MZ |
4170 | return 0; |
4171 | ||
4172 | default: | |
4173 | return -EINVAL; | |
4174 | } | |
4175 | } | |
4176 | ||
4177 | static struct irq_chip its_vpe_4_1_irq_chip = { | |
4178 | .name = "GICv4.1-vpe", | |
d97c97ba MZ |
4179 | .irq_mask = its_vpe_4_1_mask_irq, |
4180 | .irq_unmask = its_vpe_4_1_unmask_irq, | |
29c647f3 MZ |
4181 | .irq_eoi = irq_chip_eoi_parent, |
4182 | .irq_set_affinity = its_vpe_set_affinity, | |
4183 | .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity, | |
4184 | }; | |
4185 | ||
e252cf8a MZ |
4186 | static void its_configure_sgi(struct irq_data *d, bool clear) |
4187 | { | |
4188 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4189 | struct its_cmd_desc desc; | |
4190 | ||
4191 | desc.its_vsgi_cmd.vpe = vpe; | |
4192 | desc.its_vsgi_cmd.sgi = d->hwirq; | |
4193 | desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; | |
4194 | desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; | |
4195 | desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; | |
4196 | desc.its_vsgi_cmd.clear = clear; | |
4197 | ||
4198 | /* | |
4199 | * GICv4.1 allows us to send VSGI commands to any ITS as long as the | |
4200 | * destination VPE is mapped there. Since we map them eagerly at | |
4201 | * activation time, we're pretty sure the first GICv4.1 ITS will do. | |
4202 | */ | |
4203 | its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc); | |
4204 | } | |
4205 | ||
b4e8d644 MZ |
4206 | static void its_sgi_mask_irq(struct irq_data *d) |
4207 | { | |
4208 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4209 | ||
4210 | vpe->sgi_config[d->hwirq].enabled = false; | |
4211 | its_configure_sgi(d, false); | |
4212 | } | |
4213 | ||
4214 | static void its_sgi_unmask_irq(struct irq_data *d) | |
4215 | { | |
4216 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4217 | ||
4218 | vpe->sgi_config[d->hwirq].enabled = true; | |
4219 | its_configure_sgi(d, false); | |
4220 | } | |
4221 | ||
166cba71 MZ |
4222 | static int its_sgi_set_affinity(struct irq_data *d, |
4223 | const struct cpumask *mask_val, | |
4224 | bool force) | |
4225 | { | |
4226 | /* | |
4227 | * There is no notion of affinity for virtual SGIs, at least | |
a359f757 | 4228 | * not on the host (since they can only be targeting a vPE). |
166cba71 MZ |
4229 | * Tell the kernel we've done whatever it asked for. |
4230 | */ | |
4b2dfe1e | 4231 | irq_data_update_effective_affinity(d, mask_val); |
166cba71 MZ |
4232 | return IRQ_SET_MASK_OK; |
4233 | } | |
4234 | ||
7017ff0e MZ |
4235 | static int its_sgi_set_irqchip_state(struct irq_data *d, |
4236 | enum irqchip_irq_state which, | |
4237 | bool state) | |
4238 | { | |
4239 | if (which != IRQCHIP_STATE_PENDING) | |
4240 | return -EINVAL; | |
4241 | ||
4242 | if (state) { | |
4243 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4244 | struct its_node *its = find_4_1_its(); | |
4245 | u64 val; | |
4246 | ||
4247 | val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); | |
4248 | val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); | |
4249 | writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); | |
4250 | } else { | |
4251 | its_configure_sgi(d, true); | |
4252 | } | |
4253 | ||
4254 | return 0; | |
4255 | } | |
4256 | ||
4257 | static int its_sgi_get_irqchip_state(struct irq_data *d, | |
4258 | enum irqchip_irq_state which, bool *val) | |
4259 | { | |
4260 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4261 | void __iomem *base; | |
4262 | unsigned long flags; | |
4263 | u32 count = 1000000; /* 1s! */ | |
4264 | u32 status; | |
4265 | int cpu; | |
4266 | ||
4267 | if (which != IRQCHIP_STATE_PENDING) | |
4268 | return -EINVAL; | |
4269 | ||
4270 | /* | |
4271 | * Locking galore! We can race against two different events: | |
4272 | * | |
a359f757 | 4273 | * - Concurrent vPE affinity change: we must make sure it cannot |
7017ff0e MZ |
4274 | * happen, or we'll talk to the wrong redistributor. This is |
4275 | * identical to what happens with vLPIs. | |
4276 | * | |
4277 | * - Concurrent VSGIPENDR access: As it involves accessing two | |
4278 | * MMIO registers, this must be made atomic one way or another. | |
4279 | */ | |
4280 | cpu = vpe_to_cpuid_lock(vpe, &flags); | |
4281 | raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); | |
4282 | base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; | |
4283 | writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); | |
4284 | do { | |
4285 | status = readl_relaxed(base + GICR_VSGIPENDR); | |
4286 | if (!(status & GICR_VSGIPENDR_BUSY)) | |
4287 | goto out; | |
4288 | ||
4289 | count--; | |
4290 | if (!count) { | |
4291 | pr_err_ratelimited("Unable to get SGI status\n"); | |
4292 | goto out; | |
4293 | } | |
4294 | cpu_relax(); | |
4295 | udelay(1); | |
4296 | } while (count); | |
4297 | ||
4298 | out: | |
4299 | raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); | |
4300 | vpe_to_cpuid_unlock(vpe, flags); | |
4301 | ||
4302 | if (!count) | |
4303 | return -ENXIO; | |
4304 | ||
4305 | *val = !!(status & (1 << d->hwirq)); | |
4306 | ||
4307 | return 0; | |
4308 | } | |
4309 | ||
05d32df1 MZ |
4310 | static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
4311 | { | |
4312 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
4313 | struct its_cmd_info *info = vcpu_info; | |
4314 | ||
4315 | switch (info->cmd_type) { | |
4316 | case PROP_UPDATE_VSGI: | |
4317 | vpe->sgi_config[d->hwirq].priority = info->priority; | |
4318 | vpe->sgi_config[d->hwirq].group = info->group; | |
4319 | its_configure_sgi(d, false); | |
4320 | return 0; | |
4321 | ||
4322 | default: | |
4323 | return -EINVAL; | |
4324 | } | |
4325 | } | |
4326 | ||
166cba71 MZ |
4327 | static struct irq_chip its_sgi_irq_chip = { |
4328 | .name = "GICv4.1-sgi", | |
b4e8d644 MZ |
4329 | .irq_mask = its_sgi_mask_irq, |
4330 | .irq_unmask = its_sgi_unmask_irq, | |
166cba71 | 4331 | .irq_set_affinity = its_sgi_set_affinity, |
7017ff0e MZ |
4332 | .irq_set_irqchip_state = its_sgi_set_irqchip_state, |
4333 | .irq_get_irqchip_state = its_sgi_get_irqchip_state, | |
05d32df1 | 4334 | .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity, |
166cba71 MZ |
4335 | }; |
4336 | ||
4337 | static int its_sgi_irq_domain_alloc(struct irq_domain *domain, | |
4338 | unsigned int virq, unsigned int nr_irqs, | |
4339 | void *args) | |
4340 | { | |
4341 | struct its_vpe *vpe = args; | |
4342 | int i; | |
4343 | ||
4344 | /* Yes, we do want 16 SGIs */ | |
4345 | WARN_ON(nr_irqs != 16); | |
4346 | ||
4347 | for (i = 0; i < 16; i++) { | |
4348 | vpe->sgi_config[i].priority = 0; | |
4349 | vpe->sgi_config[i].enabled = false; | |
4350 | vpe->sgi_config[i].group = false; | |
4351 | ||
4352 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
4353 | &its_sgi_irq_chip, vpe); | |
4354 | irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); | |
4355 | } | |
4356 | ||
4357 | return 0; | |
4358 | } | |
4359 | ||
4360 | static void its_sgi_irq_domain_free(struct irq_domain *domain, | |
4361 | unsigned int virq, | |
4362 | unsigned int nr_irqs) | |
4363 | { | |
4364 | /* Nothing to do */ | |
4365 | } | |
4366 | ||
4367 | static int its_sgi_irq_domain_activate(struct irq_domain *domain, | |
4368 | struct irq_data *d, bool reserve) | |
4369 | { | |
e252cf8a MZ |
4370 | /* Write out the initial SGI configuration */ |
4371 | its_configure_sgi(d, false); | |
166cba71 MZ |
4372 | return 0; |
4373 | } | |
4374 | ||
4375 | static void its_sgi_irq_domain_deactivate(struct irq_domain *domain, | |
4376 | struct irq_data *d) | |
4377 | { | |
e252cf8a MZ |
4378 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); |
4379 | ||
4380 | /* | |
4381 | * The VSGI command is awkward: | |
4382 | * | |
4383 | * - To change the configuration, CLEAR must be set to false, | |
4384 | * leaving the pending bit unchanged. | |
4385 | * - To clear the pending bit, CLEAR must be set to true, leaving | |
4386 | * the configuration unchanged. | |
4387 | * | |
4388 | * You just can't do both at once, hence the two commands below. | |
4389 | */ | |
4390 | vpe->sgi_config[d->hwirq].enabled = false; | |
4391 | its_configure_sgi(d, false); | |
4392 | its_configure_sgi(d, true); | |
166cba71 MZ |
4393 | } |
4394 | ||
4395 | static const struct irq_domain_ops its_sgi_domain_ops = { | |
4396 | .alloc = its_sgi_irq_domain_alloc, | |
4397 | .free = its_sgi_irq_domain_free, | |
4398 | .activate = its_sgi_irq_domain_activate, | |
4399 | .deactivate = its_sgi_irq_domain_deactivate, | |
4400 | }; | |
4401 | ||
7d75bbb4 MZ |
4402 | static int its_vpe_id_alloc(void) |
4403 | { | |
32bd44dc | 4404 | return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL); |
7d75bbb4 MZ |
4405 | } |
4406 | ||
4407 | static void its_vpe_id_free(u16 id) | |
4408 | { | |
4409 | ida_simple_remove(&its_vpeid_ida, id); | |
4410 | } | |
4411 | ||
4412 | static int its_vpe_init(struct its_vpe *vpe) | |
4413 | { | |
4414 | struct page *vpt_page; | |
4415 | int vpe_id; | |
4416 | ||
4417 | /* Allocate vpe_id */ | |
4418 | vpe_id = its_vpe_id_alloc(); | |
4419 | if (vpe_id < 0) | |
4420 | return vpe_id; | |
4421 | ||
4422 | /* Allocate VPT */ | |
4423 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
4424 | if (!vpt_page) { | |
4425 | its_vpe_id_free(vpe_id); | |
4426 | return -ENOMEM; | |
4427 | } | |
4428 | ||
4429 | if (!its_alloc_vpe_table(vpe_id)) { | |
4430 | its_vpe_id_free(vpe_id); | |
34f8eb92 | 4431 | its_free_pending_table(vpt_page); |
7d75bbb4 MZ |
4432 | return -ENOMEM; |
4433 | } | |
4434 | ||
f3a05921 | 4435 | raw_spin_lock_init(&vpe->vpe_lock); |
7d75bbb4 MZ |
4436 | vpe->vpe_id = vpe_id; |
4437 | vpe->vpt_page = vpt_page; | |
64edfaa9 MZ |
4438 | if (gic_rdists->has_rvpeid) |
4439 | atomic_set(&vpe->vmapp_count, 0); | |
4440 | else | |
4441 | vpe->vpe_proxy_event = -1; | |
7d75bbb4 MZ |
4442 | |
4443 | return 0; | |
4444 | } | |
4445 | ||
4446 | static void its_vpe_teardown(struct its_vpe *vpe) | |
4447 | { | |
20b3d54e | 4448 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
4449 | its_vpe_id_free(vpe->vpe_id); |
4450 | its_free_pending_table(vpe->vpt_page); | |
4451 | } | |
4452 | ||
4453 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
4454 | unsigned int virq, | |
4455 | unsigned int nr_irqs) | |
4456 | { | |
4457 | struct its_vm *vm = domain->host_data; | |
4458 | int i; | |
4459 | ||
4460 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
4461 | ||
4462 | for (i = 0; i < nr_irqs; i++) { | |
4463 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
4464 | virq + i); | |
4465 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
4466 | ||
4467 | BUG_ON(vm != vpe->its_vm); | |
4468 | ||
4469 | clear_bit(data->hwirq, vm->db_bitmap); | |
4470 | its_vpe_teardown(vpe); | |
4471 | irq_domain_reset_irq_data(data); | |
4472 | } | |
4473 | ||
4474 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
38dd7c49 | 4475 | its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); |
7d75bbb4 MZ |
4476 | its_free_prop_table(vm->vprop_page); |
4477 | } | |
4478 | } | |
4479 | ||
4480 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
4481 | unsigned int nr_irqs, void *args) | |
4482 | { | |
29c647f3 | 4483 | struct irq_chip *irqchip = &its_vpe_irq_chip; |
7d75bbb4 MZ |
4484 | struct its_vm *vm = args; |
4485 | unsigned long *bitmap; | |
4486 | struct page *vprop_page; | |
4487 | int base, nr_ids, i, err = 0; | |
4488 | ||
4489 | BUG_ON(!vm); | |
4490 | ||
38dd7c49 | 4491 | bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids); |
7d75bbb4 MZ |
4492 | if (!bitmap) |
4493 | return -ENOMEM; | |
4494 | ||
4495 | if (nr_ids < nr_irqs) { | |
38dd7c49 | 4496 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4497 | return -ENOMEM; |
4498 | } | |
4499 | ||
4500 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
4501 | if (!vprop_page) { | |
38dd7c49 | 4502 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4503 | return -ENOMEM; |
4504 | } | |
4505 | ||
4506 | vm->db_bitmap = bitmap; | |
4507 | vm->db_lpi_base = base; | |
4508 | vm->nr_db_lpis = nr_ids; | |
4509 | vm->vprop_page = vprop_page; | |
4510 | ||
29c647f3 MZ |
4511 | if (gic_rdists->has_rvpeid) |
4512 | irqchip = &its_vpe_4_1_irq_chip; | |
4513 | ||
7d75bbb4 MZ |
4514 | for (i = 0; i < nr_irqs; i++) { |
4515 | vm->vpes[i]->vpe_db_lpi = base + i; | |
4516 | err = its_vpe_init(vm->vpes[i]); | |
4517 | if (err) | |
4518 | break; | |
4519 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
4520 | vm->vpes[i]->vpe_db_lpi); | |
4521 | if (err) | |
4522 | break; | |
4523 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
29c647f3 | 4524 | irqchip, vm->vpes[i]); |
7d75bbb4 MZ |
4525 | set_bit(i, bitmap); |
4526 | } | |
4527 | ||
4528 | if (err) { | |
4529 | if (i > 0) | |
280bef51 | 4530 | its_vpe_irq_domain_free(domain, virq, i); |
7d75bbb4 | 4531 | |
38dd7c49 | 4532 | its_lpi_free(bitmap, base, nr_ids); |
7d75bbb4 MZ |
4533 | its_free_prop_table(vprop_page); |
4534 | } | |
4535 | ||
4536 | return err; | |
4537 | } | |
4538 | ||
72491643 | 4539 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
702cb0a0 | 4540 | struct irq_data *d, bool reserve) |
eb78192b MZ |
4541 | { |
4542 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
40619a2e | 4543 | struct its_node *its; |
eb78192b | 4544 | |
009384b3 MZ |
4545 | /* |
4546 | * If we use the list map, we issue VMAPP on demand... Unless | |
4547 | * we're on a GICv4.1 and we eagerly map the VPE on all ITSs | |
4548 | * so that VSGIs can work. | |
4549 | */ | |
4550 | if (!gic_requires_eager_mapping()) | |
6ef930f2 | 4551 | return 0; |
eb78192b MZ |
4552 | |
4553 | /* Map the VPE to the first possible CPU */ | |
4554 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
40619a2e MZ |
4555 | |
4556 | list_for_each_entry(its, &its_nodes, entry) { | |
0dd57fed | 4557 | if (!is_v4(its)) |
40619a2e MZ |
4558 | continue; |
4559 | ||
75fd951b | 4560 | its_send_vmapp(its, vpe, true); |
40619a2e MZ |
4561 | its_send_vinvall(its, vpe); |
4562 | } | |
4563 | ||
44c4c25e MZ |
4564 | irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); |
4565 | ||
72491643 | 4566 | return 0; |
eb78192b MZ |
4567 | } |
4568 | ||
4569 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
4570 | struct irq_data *d) | |
4571 | { | |
4572 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
75fd951b MZ |
4573 | struct its_node *its; |
4574 | ||
2247e1bf | 4575 | /* |
009384b3 MZ |
4576 | * If we use the list map on GICv4.0, we unmap the VPE once no |
4577 | * VLPIs are associated with the VM. | |
2247e1bf | 4578 | */ |
009384b3 | 4579 | if (!gic_requires_eager_mapping()) |
2247e1bf | 4580 | return; |
eb78192b | 4581 | |
75fd951b | 4582 | list_for_each_entry(its, &its_nodes, entry) { |
0dd57fed | 4583 | if (!is_v4(its)) |
75fd951b | 4584 | continue; |
eb78192b | 4585 | |
75fd951b MZ |
4586 | its_send_vmapp(its, vpe, false); |
4587 | } | |
301beaf1 MZ |
4588 | |
4589 | /* | |
4590 | * There may be a direct read to the VPT after unmapping the | |
4591 | * vPE, to guarantee the validity of this, we make the VPT | |
4592 | * memory coherent with the CPU caches here. | |
4593 | */ | |
4594 | if (find_4_1_its() && !atomic_read(&vpe->vmapp_count)) | |
4595 | gic_flush_dcache_to_poc(page_address(vpe->vpt_page), | |
4596 | LPI_PENDBASE_SZ); | |
eb78192b MZ |
4597 | } |
4598 | ||
8fff27ae | 4599 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
4600 | .alloc = its_vpe_irq_domain_alloc, |
4601 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
4602 | .activate = its_vpe_irq_domain_activate, |
4603 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
4604 | }; |
4605 | ||
4559fbb3 YW |
4606 | static int its_force_quiescent(void __iomem *base) |
4607 | { | |
4608 | u32 count = 1000000; /* 1s */ | |
4609 | u32 val; | |
4610 | ||
4611 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
4612 | /* |
4613 | * GIC architecture specification requires the ITS to be both | |
4614 | * disabled and quiescent for writes to GITS_BASER<n> or | |
4615 | * GITS_CBASER to not have UNPREDICTABLE results. | |
4616 | */ | |
4617 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
4618 | return 0; |
4619 | ||
4620 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 4621 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
4622 | writel_relaxed(val, base + GITS_CTLR); |
4623 | ||
4624 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
4625 | while (1) { | |
4626 | val = readl_relaxed(base + GITS_CTLR); | |
4627 | if (val & GITS_CTLR_QUIESCENT) | |
4628 | return 0; | |
4629 | ||
4630 | count--; | |
4631 | if (!count) | |
4632 | return -EBUSY; | |
4633 | ||
4634 | cpu_relax(); | |
4635 | udelay(1); | |
4636 | } | |
4637 | } | |
4638 | ||
9d111d49 | 4639 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
4640 | { |
4641 | struct its_node *its = data; | |
4642 | ||
576a8342 MZ |
4643 | /* erratum 22375: only alloc 8MB table size (20 bits) */ |
4644 | its->typer &= ~GITS_TYPER_DEVBITS; | |
4645 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); | |
94100970 | 4646 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
4647 | |
4648 | return true; | |
94100970 RR |
4649 | } |
4650 | ||
9d111d49 | 4651 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
4652 | { |
4653 | struct its_node *its = data; | |
4654 | ||
4655 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
4656 | |
4657 | return true; | |
fbf8f40e GK |
4658 | } |
4659 | ||
9d111d49 | 4660 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
4661 | { |
4662 | struct its_node *its = data; | |
4663 | ||
4664 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
ffedbf0c MZ |
4665 | its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; |
4666 | its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); | |
9d111d49 AB |
4667 | |
4668 | return true; | |
90922a2d SD |
4669 | } |
4670 | ||
558b0165 AB |
4671 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
4672 | { | |
4673 | struct its_node *its = its_dev->its; | |
4674 | ||
4675 | /* | |
4676 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
4677 | * which maps 32-bit writes targeted at a separate window of | |
4678 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
4679 | * with device ID taken from bits [device_id_bits + 1:2] of | |
4680 | * the window offset. | |
4681 | */ | |
4682 | return its->pre_its_base + (its_dev->device_id << 2); | |
4683 | } | |
4684 | ||
4685 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
4686 | { | |
4687 | struct its_node *its = data; | |
4688 | u32 pre_its_window[2]; | |
4689 | u32 ids; | |
4690 | ||
4691 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
4692 | "socionext,synquacer-pre-its", | |
4693 | pre_its_window, | |
4694 | ARRAY_SIZE(pre_its_window))) { | |
4695 | ||
4696 | its->pre_its_base = pre_its_window[0]; | |
4697 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
4698 | ||
4699 | ids = ilog2(pre_its_window[1]) - 2; | |
576a8342 MZ |
4700 | if (device_ids(its) > ids) { |
4701 | its->typer &= ~GITS_TYPER_DEVBITS; | |
4702 | its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); | |
4703 | } | |
558b0165 AB |
4704 | |
4705 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
dcb83f6e | 4706 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI; |
558b0165 AB |
4707 | return true; |
4708 | } | |
4709 | return false; | |
4710 | } | |
4711 | ||
5c9a882e MZ |
4712 | static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) |
4713 | { | |
4714 | struct its_node *its = data; | |
4715 | ||
4716 | /* | |
4717 | * Hip07 insists on using the wrong address for the VLPI | |
4718 | * page. Trick it into doing the right thing... | |
4719 | */ | |
4720 | its->vlpi_redist_offset = SZ_128K; | |
4721 | return true; | |
90922a2d SD |
4722 | } |
4723 | ||
a8707f55 SR |
4724 | static bool __maybe_unused its_enable_rk3588001(void *data) |
4725 | { | |
4726 | struct its_node *its = data; | |
4727 | ||
4728 | if (!of_machine_is_compatible("rockchip,rk3588")) | |
4729 | return false; | |
4730 | ||
4731 | its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; | |
4732 | gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; | |
4733 | ||
4734 | return true; | |
4735 | } | |
4736 | ||
67510cca | 4737 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
4738 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
4739 | { | |
4740 | .desc = "ITS: Cavium errata 22375, 24313", | |
4741 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
4742 | .mask = 0xffff0fff, | |
4743 | .init = its_enable_quirk_cavium_22375, | |
4744 | }, | |
fbf8f40e GK |
4745 | #endif |
4746 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
4747 | { | |
4748 | .desc = "ITS: Cavium erratum 23144", | |
4749 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
4750 | .mask = 0xffff0fff, | |
4751 | .init = its_enable_quirk_cavium_23144, | |
4752 | }, | |
90922a2d SD |
4753 | #endif |
4754 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
4755 | { | |
4756 | .desc = "ITS: QDF2400 erratum 0065", | |
4757 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
4758 | .mask = 0xffffffff, | |
4759 | .init = its_enable_quirk_qdf2400_e0065, | |
4760 | }, | |
558b0165 AB |
4761 | #endif |
4762 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
4763 | { | |
4764 | /* | |
4765 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
4766 | * implementation, but with a 'pre-ITS' added that requires | |
4767 | * special handling in software. | |
4768 | */ | |
4769 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
4770 | .iidr = 0x0001143b, | |
4771 | .mask = 0xffffffff, | |
4772 | .init = its_enable_quirk_socionext_synquacer, | |
4773 | }, | |
5c9a882e MZ |
4774 | #endif |
4775 | #ifdef CONFIG_HISILICON_ERRATUM_161600802 | |
4776 | { | |
4777 | .desc = "ITS: Hip07 erratum 161600802", | |
4778 | .iidr = 0x00000004, | |
4779 | .mask = 0xffffffff, | |
4780 | .init = its_enable_quirk_hip07_161600802, | |
4781 | }, | |
a8707f55 SR |
4782 | #endif |
4783 | #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001 | |
4784 | { | |
4785 | .desc = "ITS: Rockchip erratum RK3588001", | |
4786 | .iidr = 0x0201743b, | |
4787 | .mask = 0xffffffff, | |
4788 | .init = its_enable_rk3588001, | |
4789 | }, | |
94100970 | 4790 | #endif |
67510cca RR |
4791 | { |
4792 | } | |
4793 | }; | |
4794 | ||
4795 | static void its_enable_quirks(struct its_node *its) | |
4796 | { | |
4797 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
4798 | ||
4799 | gic_enable_quirks(iidr, its_quirks, its); | |
4800 | } | |
4801 | ||
dba0bc7b DB |
4802 | static int its_save_disable(void) |
4803 | { | |
4804 | struct its_node *its; | |
4805 | int err = 0; | |
4806 | ||
a8db7456 | 4807 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
4808 | list_for_each_entry(its, &its_nodes, entry) { |
4809 | void __iomem *base; | |
4810 | ||
dba0bc7b DB |
4811 | base = its->base; |
4812 | its->ctlr_save = readl_relaxed(base + GITS_CTLR); | |
4813 | err = its_force_quiescent(base); | |
4814 | if (err) { | |
4815 | pr_err("ITS@%pa: failed to quiesce: %d\n", | |
4816 | &its->phys_base, err); | |
4817 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
4818 | goto err; | |
4819 | } | |
4820 | ||
4821 | its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); | |
4822 | } | |
4823 | ||
4824 | err: | |
4825 | if (err) { | |
4826 | list_for_each_entry_continue_reverse(its, &its_nodes, entry) { | |
4827 | void __iomem *base; | |
4828 | ||
dba0bc7b DB |
4829 | base = its->base; |
4830 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
4831 | } | |
4832 | } | |
a8db7456 | 4833 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
4834 | |
4835 | return err; | |
4836 | } | |
4837 | ||
4838 | static void its_restore_enable(void) | |
4839 | { | |
4840 | struct its_node *its; | |
4841 | int ret; | |
4842 | ||
a8db7456 | 4843 | raw_spin_lock(&its_lock); |
dba0bc7b DB |
4844 | list_for_each_entry(its, &its_nodes, entry) { |
4845 | void __iomem *base; | |
4846 | int i; | |
4847 | ||
dba0bc7b DB |
4848 | base = its->base; |
4849 | ||
4850 | /* | |
4851 | * Make sure that the ITS is disabled. If it fails to quiesce, | |
4852 | * don't restore it since writing to CBASER or BASER<n> | |
4853 | * registers is undefined according to the GIC v3 ITS | |
4854 | * Specification. | |
74cde1a5 XQ |
4855 | * |
4856 | * Firmware resuming with the ITS enabled is terminally broken. | |
dba0bc7b | 4857 | */ |
74cde1a5 | 4858 | WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE); |
dba0bc7b DB |
4859 | ret = its_force_quiescent(base); |
4860 | if (ret) { | |
4861 | pr_err("ITS@%pa: failed to quiesce on resume: %d\n", | |
4862 | &its->phys_base, ret); | |
4863 | continue; | |
4864 | } | |
4865 | ||
4866 | gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); | |
4867 | ||
4868 | /* | |
4869 | * Writing CBASER resets CREADR to 0, so make CWRITER and | |
4870 | * cmd_write line up with it. | |
4871 | */ | |
4872 | its->cmd_write = its->cmd_base; | |
4873 | gits_write_cwriter(0, base + GITS_CWRITER); | |
4874 | ||
4875 | /* Restore GITS_BASER from the value cache. */ | |
4876 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
4877 | struct its_baser *baser = &its->tables[i]; | |
4878 | ||
4879 | if (!(baser->val & GITS_BASER_VALID)) | |
4880 | continue; | |
4881 | ||
4882 | its_write_baser(its, baser, baser->val); | |
4883 | } | |
4884 | writel_relaxed(its->ctlr_save, base + GITS_CTLR); | |
920181ce DB |
4885 | |
4886 | /* | |
4887 | * Reinit the collection if it's stored in the ITS. This is | |
4888 | * indicated by the col_id being less than the HCC field. | |
4889 | * CID < HCC as specified in the GIC v3 Documentation. | |
4890 | */ | |
4891 | if (its->collections[smp_processor_id()].col_id < | |
4892 | GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) | |
4893 | its_cpu_init_collection(its); | |
dba0bc7b | 4894 | } |
a8db7456 | 4895 | raw_spin_unlock(&its_lock); |
dba0bc7b DB |
4896 | } |
4897 | ||
4898 | static struct syscore_ops its_syscore_ops = { | |
4899 | .suspend = its_save_disable, | |
4900 | .resume = its_restore_enable, | |
4901 | }; | |
4902 | ||
c733ebb7 MZ |
4903 | static void __init __iomem *its_map_one(struct resource *res, int *err) |
4904 | { | |
4905 | void __iomem *its_base; | |
4906 | u32 val; | |
4907 | ||
4908 | its_base = ioremap(res->start, SZ_64K); | |
4909 | if (!its_base) { | |
4910 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); | |
4911 | *err = -ENOMEM; | |
4912 | return NULL; | |
4913 | } | |
4914 | ||
4915 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
4916 | if (val != 0x30 && val != 0x40) { | |
4917 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); | |
4918 | *err = -ENODEV; | |
4919 | goto out_unmap; | |
4920 | } | |
4921 | ||
4922 | *err = its_force_quiescent(its_base); | |
4923 | if (*err) { | |
4924 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); | |
4925 | goto out_unmap; | |
4926 | } | |
4927 | ||
4928 | return its_base; | |
4929 | ||
4930 | out_unmap: | |
4931 | iounmap(its_base); | |
4932 | return NULL; | |
4933 | } | |
4934 | ||
db40f0a7 | 4935 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
4936 | { |
4937 | struct irq_domain *inner_domain; | |
4938 | struct msi_domain_info *info; | |
4939 | ||
4940 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
4941 | if (!info) | |
4942 | return -ENOMEM; | |
4943 | ||
1e46e040 JH |
4944 | info->ops = &its_msi_domain_ops; |
4945 | info->data = its; | |
4946 | ||
4947 | inner_domain = irq_domain_create_hierarchy(its_parent, | |
4948 | its->msi_domain_flags, 0, | |
4949 | handle, &its_domain_ops, | |
4950 | info); | |
d14ae5e6 TN |
4951 | if (!inner_domain) { |
4952 | kfree(info); | |
4953 | return -ENOMEM; | |
4954 | } | |
4955 | ||
96f0d93a | 4956 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
d14ae5e6 TN |
4957 | |
4958 | return 0; | |
4959 | } | |
4960 | ||
8fff27ae MZ |
4961 | static int its_init_vpe_domain(void) |
4962 | { | |
20b3d54e MZ |
4963 | struct its_node *its; |
4964 | u32 devid; | |
4965 | int entries; | |
4966 | ||
4967 | if (gic_rdists->has_direct_lpi) { | |
4968 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
4969 | return 0; | |
4970 | } | |
4971 | ||
4972 | /* Any ITS will do, even if not v4 */ | |
4973 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
4974 | ||
4975 | entries = roundup_pow_of_two(nr_cpu_ids); | |
6396bb22 | 4976 | vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes), |
20b3d54e | 4977 | GFP_KERNEL); |
944a1a17 | 4978 | if (!vpe_proxy.vpes) |
20b3d54e | 4979 | return -ENOMEM; |
20b3d54e MZ |
4980 | |
4981 | /* Use the last possible DevID */ | |
576a8342 | 4982 | devid = GENMASK(device_ids(its) - 1, 0); |
20b3d54e MZ |
4983 | vpe_proxy.dev = its_create_device(its, devid, entries, false); |
4984 | if (!vpe_proxy.dev) { | |
4985 | kfree(vpe_proxy.vpes); | |
4986 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
4987 | return -ENOMEM; | |
4988 | } | |
4989 | ||
c427a475 | 4990 | BUG_ON(entries > vpe_proxy.dev->nr_ites); |
20b3d54e MZ |
4991 | |
4992 | raw_spin_lock_init(&vpe_proxy.lock); | |
4993 | vpe_proxy.next_victim = 0; | |
4994 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
4995 | devid, vpe_proxy.dev->nr_ites); | |
4996 | ||
8fff27ae MZ |
4997 | return 0; |
4998 | } | |
4999 | ||
3dfa576b MZ |
5000 | static int __init its_compute_its_list_map(struct resource *res, |
5001 | void __iomem *its_base) | |
5002 | { | |
5003 | int its_number; | |
5004 | u32 ctlr; | |
5005 | ||
5006 | /* | |
5007 | * This is assumed to be done early enough that we're | |
5008 | * guaranteed to be single-threaded, hence no | |
5009 | * locking. Should this change, we should address | |
5010 | * this. | |
5011 | */ | |
ab60491e MZ |
5012 | its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX); |
5013 | if (its_number >= GICv4_ITS_LIST_MAX) { | |
3dfa576b MZ |
5014 | pr_err("ITS@%pa: No ITSList entry available!\n", |
5015 | &res->start); | |
5016 | return -EINVAL; | |
5017 | } | |
5018 | ||
5019 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
5020 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
5021 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
5022 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
5023 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
5024 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
5025 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
5026 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
5027 | } | |
5028 | ||
5029 | if (test_and_set_bit(its_number, &its_list_map)) { | |
5030 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
5031 | &res->start, its_number); | |
5032 | return -EINVAL; | |
5033 | } | |
5034 | ||
5035 | return its_number; | |
5036 | } | |
5037 | ||
db40f0a7 TN |
5038 | static int __init its_probe_one(struct resource *res, |
5039 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 5040 | { |
4c21f3c2 MZ |
5041 | struct its_node *its; |
5042 | void __iomem *its_base; | |
3dfa576b | 5043 | u64 baser, tmp, typer; |
539d3782 | 5044 | struct page *page; |
c733ebb7 | 5045 | u32 ctlr; |
4c21f3c2 MZ |
5046 | int err; |
5047 | ||
c733ebb7 MZ |
5048 | its_base = its_map_one(res, &err); |
5049 | if (!its_base) | |
5050 | return err; | |
4559fbb3 | 5051 | |
db40f0a7 | 5052 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
5053 | |
5054 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
5055 | if (!its) { | |
5056 | err = -ENOMEM; | |
5057 | goto out_unmap; | |
5058 | } | |
5059 | ||
5060 | raw_spin_lock_init(&its->lock); | |
9791ec7d | 5061 | mutex_init(&its->dev_alloc_lock); |
4c21f3c2 MZ |
5062 | INIT_LIST_HEAD(&its->entry); |
5063 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 5064 | typer = gic_read_typer(its_base + GITS_TYPER); |
0dd57fed | 5065 | its->typer = typer; |
4c21f3c2 | 5066 | its->base = its_base; |
db40f0a7 | 5067 | its->phys_base = res->start; |
0dd57fed | 5068 | if (is_v4(its)) { |
3dfa576b MZ |
5069 | if (!(typer & GITS_TYPER_VMOVP)) { |
5070 | err = its_compute_its_list_map(res, its_base); | |
5071 | if (err < 0) | |
5072 | goto out_free_its; | |
5073 | ||
debf6d02 MZ |
5074 | its->list_nr = err; |
5075 | ||
3dfa576b MZ |
5076 | pr_info("ITS@%pa: Using ITS number %d\n", |
5077 | &res->start, err); | |
5078 | } else { | |
5079 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
5080 | } | |
5e516846 MZ |
5081 | |
5082 | if (is_v4_1(its)) { | |
5083 | u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer); | |
5e46a484 MZ |
5084 | |
5085 | its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K); | |
5086 | if (!its->sgir_base) { | |
5087 | err = -ENOMEM; | |
5088 | goto out_free_its; | |
5089 | } | |
5090 | ||
5e516846 MZ |
5091 | its->mpidr = readl_relaxed(its_base + GITS_MPIDR); |
5092 | ||
5093 | pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", | |
5094 | &res->start, its->mpidr, svpet); | |
5095 | } | |
3dfa576b MZ |
5096 | } |
5097 | ||
db40f0a7 | 5098 | its->numa_node = numa_node; |
4c21f3c2 | 5099 | |
539d3782 SD |
5100 | page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, |
5101 | get_order(ITS_CMD_QUEUE_SZ)); | |
5102 | if (!page) { | |
4c21f3c2 | 5103 | err = -ENOMEM; |
5e46a484 | 5104 | goto out_unmap_sgir; |
4c21f3c2 | 5105 | } |
539d3782 | 5106 | its->cmd_base = (void *)page_address(page); |
4c21f3c2 | 5107 | its->cmd_write = its->cmd_base; |
558b0165 AB |
5108 | its->fwnode_handle = handle; |
5109 | its->get_msi_base = its_irq_get_msi_base; | |
dcb83f6e | 5110 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI; |
4c21f3c2 | 5111 | |
67510cca RR |
5112 | its_enable_quirks(its); |
5113 | ||
0e0b0f69 | 5114 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
5115 | if (err) |
5116 | goto out_free_cmd; | |
5117 | ||
5118 | err = its_alloc_collections(its); | |
5119 | if (err) | |
5120 | goto out_free_tables; | |
5121 | ||
5122 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 5123 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
5124 | GITS_CBASER_InnerShareable | |
5125 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
5126 | GITS_CBASER_VALID); | |
5127 | ||
0968a619 VM |
5128 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
5129 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 5130 | |
a8707f55 SR |
5131 | if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) |
5132 | tmp &= ~GITS_CBASER_SHAREABILITY_MASK; | |
5133 | ||
4ad3e363 | 5134 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
5135 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
5136 | /* | |
5137 | * The HW reports non-shareable, we must | |
5138 | * remove the cacheability attributes as | |
5139 | * well. | |
5140 | */ | |
5141 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
5142 | GITS_CBASER_CACHEABILITY_MASK); | |
5143 | baser |= GITS_CBASER_nC; | |
0968a619 | 5144 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 5145 | } |
4c21f3c2 MZ |
5146 | pr_info("ITS: using cache flushing for cmd queue\n"); |
5147 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
5148 | } | |
5149 | ||
0968a619 | 5150 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 5151 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d | 5152 | ctlr |= GITS_CTLR_ENABLE; |
0dd57fed | 5153 | if (is_v4(its)) |
d51c4b4d MZ |
5154 | ctlr |= GITS_CTLR_ImDe; |
5155 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 5156 | |
db40f0a7 | 5157 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
5158 | if (err) |
5159 | goto out_free_tables; | |
4c21f3c2 | 5160 | |
a8db7456 | 5161 | raw_spin_lock(&its_lock); |
4c21f3c2 | 5162 | list_add(&its->entry, &its_nodes); |
a8db7456 | 5163 | raw_spin_unlock(&its_lock); |
4c21f3c2 MZ |
5164 | |
5165 | return 0; | |
5166 | ||
4c21f3c2 MZ |
5167 | out_free_tables: |
5168 | its_free_tables(its); | |
5169 | out_free_cmd: | |
5bc13c2c | 5170 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
5e46a484 MZ |
5171 | out_unmap_sgir: |
5172 | if (its->sgir_base) | |
5173 | iounmap(its->sgir_base); | |
4c21f3c2 MZ |
5174 | out_free_its: |
5175 | kfree(its); | |
5176 | out_unmap: | |
5177 | iounmap(its_base); | |
db40f0a7 | 5178 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
5179 | return err; |
5180 | } | |
5181 | ||
5182 | static bool gic_rdists_supports_plpis(void) | |
5183 | { | |
589ce5f4 | 5184 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
5185 | } |
5186 | ||
6eb486b6 SD |
5187 | static int redist_disable_lpis(void) |
5188 | { | |
5189 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
5190 | u64 timeout = USEC_PER_SEC; | |
5191 | u64 val; | |
5192 | ||
5193 | if (!gic_rdists_supports_plpis()) { | |
5194 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
5195 | return -ENXIO; | |
5196 | } | |
5197 | ||
5198 | val = readl_relaxed(rbase + GICR_CTLR); | |
5199 | if (!(val & GICR_CTLR_ENABLE_LPIS)) | |
5200 | return 0; | |
5201 | ||
11e37d35 MZ |
5202 | /* |
5203 | * If coming via a CPU hotplug event, we don't need to disable | |
5204 | * LPIs before trying to re-enable them. They are already | |
5205 | * configured and all is well in the world. | |
c440a9d9 MZ |
5206 | * |
5207 | * If running with preallocated tables, there is nothing to do. | |
11e37d35 | 5208 | */ |
c0cdc890 | 5209 | if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) || |
c440a9d9 | 5210 | (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) |
11e37d35 MZ |
5211 | return 0; |
5212 | ||
5213 | /* | |
5214 | * From that point on, we only try to do some damage control. | |
5215 | */ | |
5216 | pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n", | |
6eb486b6 SD |
5217 | smp_processor_id()); |
5218 | add_taint(TAINT_CRAP, LOCKDEP_STILL_OK); | |
5219 | ||
5220 | /* Disable LPIs */ | |
5221 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
5222 | writel_relaxed(val, rbase + GICR_CTLR); | |
5223 | ||
5224 | /* Make sure any change to GICR_CTLR is observable by the GIC */ | |
5225 | dsb(sy); | |
5226 | ||
5227 | /* | |
5228 | * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs | |
5229 | * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. | |
5230 | * Error out if we time out waiting for RWP to clear. | |
5231 | */ | |
5232 | while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { | |
5233 | if (!timeout) { | |
5234 | pr_err("CPU%d: Timeout while disabling LPIs\n", | |
5235 | smp_processor_id()); | |
5236 | return -ETIMEDOUT; | |
5237 | } | |
5238 | udelay(1); | |
5239 | timeout--; | |
5240 | } | |
5241 | ||
5242 | /* | |
5243 | * After it has been written to 1, it is IMPLEMENTATION | |
5244 | * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be | |
5245 | * cleared to 0. Error out if clearing the bit failed. | |
5246 | */ | |
5247 | if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { | |
5248 | pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id()); | |
5249 | return -EBUSY; | |
5250 | } | |
5251 | ||
5252 | return 0; | |
5253 | } | |
5254 | ||
4c21f3c2 MZ |
5255 | int its_cpu_init(void) |
5256 | { | |
4c21f3c2 | 5257 | if (!list_empty(&its_nodes)) { |
6eb486b6 SD |
5258 | int ret; |
5259 | ||
5260 | ret = redist_disable_lpis(); | |
5261 | if (ret) | |
5262 | return ret; | |
5263 | ||
4c21f3c2 | 5264 | its_cpu_init_lpis(); |
920181ce | 5265 | its_cpu_init_collections(); |
4c21f3c2 MZ |
5266 | } |
5267 | ||
5268 | return 0; | |
5269 | } | |
5270 | ||
835f442f VS |
5271 | static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work) |
5272 | { | |
5273 | cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state); | |
5274 | gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; | |
5275 | } | |
5276 | ||
5277 | static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work, | |
5278 | rdist_memreserve_cpuhp_cleanup_workfn); | |
5279 | ||
d23bc2bc VS |
5280 | static int its_cpu_memreserve_lpi(unsigned int cpu) |
5281 | { | |
5282 | struct page *pend_page; | |
5283 | int ret = 0; | |
5284 | ||
5285 | /* This gets to run exactly once per CPU */ | |
5286 | if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE) | |
5287 | return 0; | |
5288 | ||
5289 | pend_page = gic_data_rdist()->pend_page; | |
5290 | if (WARN_ON(!pend_page)) { | |
5291 | ret = -ENOMEM; | |
5292 | goto out; | |
5293 | } | |
5294 | /* | |
5295 | * If the pending table was pre-programmed, free the memory we | |
5296 | * preemptively allocated. Otherwise, reserve that memory for | |
5297 | * later kexecs. | |
5298 | */ | |
5299 | if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) { | |
5300 | its_free_pending_table(pend_page); | |
5301 | gic_data_rdist()->pend_page = NULL; | |
5302 | } else { | |
5303 | phys_addr_t paddr = page_to_phys(pend_page); | |
5304 | WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ)); | |
5305 | } | |
5306 | ||
5307 | out: | |
835f442f | 5308 | /* Last CPU being brought up gets to issue the cleanup */ |
16436f70 AB |
5309 | if (!IS_ENABLED(CONFIG_SMP) || |
5310 | cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask)) | |
835f442f VS |
5311 | schedule_work(&rdist_memreserve_cpuhp_cleanup_work); |
5312 | ||
d23bc2bc VS |
5313 | gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE; |
5314 | return ret; | |
5315 | } | |
5316 | ||
c733ebb7 MZ |
5317 | /* Mark all the BASER registers as invalid before they get reprogrammed */ |
5318 | static int __init its_reset_one(struct resource *res) | |
5319 | { | |
5320 | void __iomem *its_base; | |
5321 | int err, i; | |
5322 | ||
5323 | its_base = its_map_one(res, &err); | |
5324 | if (!its_base) | |
5325 | return err; | |
5326 | ||
5327 | for (i = 0; i < GITS_BASER_NR_REGS; i++) | |
5328 | gits_write_baser(0, its_base + GITS_BASER + (i << 3)); | |
5329 | ||
5330 | iounmap(its_base); | |
5331 | return 0; | |
5332 | } | |
5333 | ||
935bba7c | 5334 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
5335 | { .compatible = "arm,gic-v3-its", }, |
5336 | {}, | |
5337 | }; | |
5338 | ||
db40f0a7 | 5339 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
5340 | { |
5341 | struct device_node *np; | |
db40f0a7 | 5342 | struct resource res; |
4c21f3c2 | 5343 | |
c733ebb7 MZ |
5344 | /* |
5345 | * Make sure *all* the ITS are reset before we probe any, as | |
5346 | * they may be sharing memory. If any of the ITS fails to | |
5347 | * reset, don't even try to go any further, as this could | |
5348 | * result in something even worse. | |
5349 | */ | |
5350 | for (np = of_find_matching_node(node, its_device_id); np; | |
5351 | np = of_find_matching_node(np, its_device_id)) { | |
5352 | int err; | |
5353 | ||
5354 | if (!of_device_is_available(np) || | |
5355 | !of_property_read_bool(np, "msi-controller") || | |
5356 | of_address_to_resource(np, 0, &res)) | |
5357 | continue; | |
5358 | ||
5359 | err = its_reset_one(&res); | |
5360 | if (err) | |
5361 | return err; | |
5362 | } | |
5363 | ||
4c21f3c2 MZ |
5364 | for (np = of_find_matching_node(node, its_device_id); np; |
5365 | np = of_find_matching_node(np, its_device_id)) { | |
95a25625 SB |
5366 | if (!of_device_is_available(np)) |
5367 | continue; | |
d14ae5e6 | 5368 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
5369 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
5370 | np); | |
d14ae5e6 TN |
5371 | continue; |
5372 | } | |
5373 | ||
db40f0a7 | 5374 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 5375 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
5376 | continue; |
5377 | } | |
5378 | ||
5379 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 5380 | } |
db40f0a7 TN |
5381 | return 0; |
5382 | } | |
5383 | ||
3f010cf1 TN |
5384 | #ifdef CONFIG_ACPI |
5385 | ||
5386 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
5387 | ||
d1ce263f | 5388 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
5389 | struct its_srat_map { |
5390 | /* numa node id */ | |
5391 | u32 numa_node; | |
5392 | /* GIC ITS ID */ | |
5393 | u32 its_id; | |
5394 | }; | |
5395 | ||
fdf6e7a8 | 5396 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
5397 | static int its_in_srat __initdata; |
5398 | ||
5399 | static int __init acpi_get_its_numa_node(u32 its_id) | |
5400 | { | |
5401 | int i; | |
5402 | ||
5403 | for (i = 0; i < its_in_srat; i++) { | |
5404 | if (its_id == its_srat_maps[i].its_id) | |
5405 | return its_srat_maps[i].numa_node; | |
5406 | } | |
5407 | return NUMA_NO_NODE; | |
5408 | } | |
5409 | ||
60574d1e | 5410 | static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header, |
fdf6e7a8 HG |
5411 | const unsigned long end) |
5412 | { | |
5413 | return 0; | |
5414 | } | |
5415 | ||
60574d1e | 5416 | static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header, |
dbd2b826 GK |
5417 | const unsigned long end) |
5418 | { | |
5419 | int node; | |
5420 | struct acpi_srat_gic_its_affinity *its_affinity; | |
5421 | ||
5422 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
5423 | if (!its_affinity) | |
5424 | return -EINVAL; | |
5425 | ||
5426 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
5427 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
5428 | its_affinity->header.length); | |
5429 | return -EINVAL; | |
5430 | } | |
5431 | ||
95ac5bf4 JC |
5432 | /* |
5433 | * Note that in theory a new proximity node could be created by this | |
5434 | * entry as it is an SRAT resource allocation structure. | |
5435 | * We do not currently support doing so. | |
5436 | */ | |
5437 | node = pxm_to_node(its_affinity->proximity_domain); | |
dbd2b826 GK |
5438 | |
5439 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
5440 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
5441 | return 0; | |
5442 | } | |
5443 | ||
5444 | its_srat_maps[its_in_srat].numa_node = node; | |
5445 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
5446 | its_in_srat++; | |
5447 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
5448 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
5449 | ||
5450 | return 0; | |
5451 | } | |
5452 | ||
5453 | static void __init acpi_table_parse_srat_its(void) | |
5454 | { | |
fdf6e7a8 HG |
5455 | int count; |
5456 | ||
5457 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
5458 | sizeof(struct acpi_table_srat), | |
5459 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
5460 | gic_acpi_match_srat_its, 0); | |
5461 | if (count <= 0) | |
5462 | return; | |
5463 | ||
6da2ec56 KC |
5464 | its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map), |
5465 | GFP_KERNEL); | |
944a1a17 | 5466 | if (!its_srat_maps) |
fdf6e7a8 | 5467 | return; |
fdf6e7a8 | 5468 | |
dbd2b826 GK |
5469 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
5470 | sizeof(struct acpi_table_srat), | |
5471 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
5472 | gic_acpi_parse_srat_its, 0); | |
5473 | } | |
fdf6e7a8 HG |
5474 | |
5475 | /* free the its_srat_maps after ITS probing */ | |
5476 | static void __init acpi_its_srat_maps_free(void) | |
5477 | { | |
5478 | kfree(its_srat_maps); | |
5479 | } | |
dbd2b826 GK |
5480 | #else |
5481 | static void __init acpi_table_parse_srat_its(void) { } | |
5482 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 5483 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
5484 | #endif |
5485 | ||
60574d1e | 5486 | static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, |
3f010cf1 TN |
5487 | const unsigned long end) |
5488 | { | |
5489 | struct acpi_madt_generic_translator *its_entry; | |
5490 | struct fwnode_handle *dom_handle; | |
5491 | struct resource res; | |
5492 | int err; | |
5493 | ||
5494 | its_entry = (struct acpi_madt_generic_translator *)header; | |
5495 | memset(&res, 0, sizeof(res)); | |
5496 | res.start = its_entry->base_address; | |
5497 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
5498 | res.flags = IORESOURCE_MEM; | |
5499 | ||
5778cc77 | 5500 | dom_handle = irq_domain_alloc_fwnode(&res.start); |
3f010cf1 TN |
5501 | if (!dom_handle) { |
5502 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
5503 | &res.start); | |
5504 | return -ENOMEM; | |
5505 | } | |
5506 | ||
8b4282e6 SK |
5507 | err = iort_register_domain_token(its_entry->translation_id, res.start, |
5508 | dom_handle); | |
3f010cf1 TN |
5509 | if (err) { |
5510 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
5511 | &res.start, its_entry->translation_id); | |
5512 | goto dom_err; | |
5513 | } | |
5514 | ||
dbd2b826 GK |
5515 | err = its_probe_one(&res, dom_handle, |
5516 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
5517 | if (!err) |
5518 | return 0; | |
5519 | ||
5520 | iort_deregister_domain_token(its_entry->translation_id); | |
5521 | dom_err: | |
5522 | irq_domain_free_fwnode(dom_handle); | |
5523 | return err; | |
5524 | } | |
5525 | ||
c733ebb7 MZ |
5526 | static int __init its_acpi_reset(union acpi_subtable_headers *header, |
5527 | const unsigned long end) | |
5528 | { | |
5529 | struct acpi_madt_generic_translator *its_entry; | |
5530 | struct resource res; | |
5531 | ||
5532 | its_entry = (struct acpi_madt_generic_translator *)header; | |
5533 | res = (struct resource) { | |
5534 | .start = its_entry->base_address, | |
5535 | .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1, | |
5536 | .flags = IORESOURCE_MEM, | |
5537 | }; | |
5538 | ||
5539 | return its_reset_one(&res); | |
5540 | } | |
5541 | ||
3f010cf1 TN |
5542 | static void __init its_acpi_probe(void) |
5543 | { | |
dbd2b826 | 5544 | acpi_table_parse_srat_its(); |
c733ebb7 MZ |
5545 | /* |
5546 | * Make sure *all* the ITS are reset before we probe any, as | |
5547 | * they may be sharing memory. If any of the ITS fails to | |
5548 | * reset, don't even try to go any further, as this could | |
5549 | * result in something even worse. | |
5550 | */ | |
5551 | if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, | |
5552 | its_acpi_reset, 0) > 0) | |
5553 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, | |
5554 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 5555 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
5556 | } |
5557 | #else | |
5558 | static void __init its_acpi_probe(void) { } | |
5559 | #endif | |
5560 | ||
d23bc2bc VS |
5561 | int __init its_lpi_memreserve_init(void) |
5562 | { | |
5563 | int state; | |
5564 | ||
5565 | if (!efi_enabled(EFI_CONFIG_TABLES)) | |
5566 | return 0; | |
5567 | ||
eba1e44b MZ |
5568 | if (list_empty(&its_nodes)) |
5569 | return 0; | |
5570 | ||
835f442f | 5571 | gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; |
d23bc2bc VS |
5572 | state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, |
5573 | "irqchip/arm/gicv3/memreserve:online", | |
5574 | its_cpu_memreserve_lpi, | |
5575 | NULL); | |
5576 | if (state < 0) | |
5577 | return state; | |
5578 | ||
835f442f VS |
5579 | gic_rdists->cpuhp_memreserve_state = state; |
5580 | ||
d23bc2bc VS |
5581 | return 0; |
5582 | } | |
5583 | ||
db40f0a7 TN |
5584 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
5585 | struct irq_domain *parent_domain) | |
5586 | { | |
5587 | struct device_node *of_node; | |
8fff27ae MZ |
5588 | struct its_node *its; |
5589 | bool has_v4 = false; | |
3c40706d | 5590 | bool has_v4_1 = false; |
8fff27ae | 5591 | int err; |
db40f0a7 | 5592 | |
5e516846 MZ |
5593 | gic_rdists = rdists; |
5594 | ||
db40f0a7 TN |
5595 | its_parent = parent_domain; |
5596 | of_node = to_of_node(handle); | |
5597 | if (of_node) | |
5598 | its_of_probe(of_node); | |
5599 | else | |
3f010cf1 | 5600 | its_acpi_probe(); |
4c21f3c2 MZ |
5601 | |
5602 | if (list_empty(&its_nodes)) { | |
5603 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
5604 | return -ENXIO; | |
5605 | } | |
5606 | ||
11e37d35 | 5607 | err = allocate_lpi_tables(); |
8fff27ae MZ |
5608 | if (err) |
5609 | return err; | |
5610 | ||
3c40706d | 5611 | list_for_each_entry(its, &its_nodes, entry) { |
0dd57fed | 5612 | has_v4 |= is_v4(its); |
3c40706d MZ |
5613 | has_v4_1 |= is_v4_1(its); |
5614 | } | |
5615 | ||
5616 | /* Don't bother with inconsistent systems */ | |
5617 | if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) | |
5618 | rdists->has_rvpeid = false; | |
8fff27ae MZ |
5619 | |
5620 | if (has_v4 & rdists->has_vlpis) { | |
166cba71 MZ |
5621 | const struct irq_domain_ops *sgi_ops; |
5622 | ||
5623 | if (has_v4_1) | |
5624 | sgi_ops = &its_sgi_domain_ops; | |
5625 | else | |
5626 | sgi_ops = NULL; | |
5627 | ||
3d63cb53 | 5628 | if (its_init_vpe_domain() || |
166cba71 | 5629 | its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) { |
8fff27ae MZ |
5630 | rdists->has_vlpis = false; |
5631 | pr_err("ITS: Disabling GICv4 support\n"); | |
5632 | } | |
5633 | } | |
5634 | ||
dba0bc7b DB |
5635 | register_syscore_ops(&its_syscore_ops); |
5636 | ||
8fff27ae | 5637 | return 0; |
4c21f3c2 | 5638 | } |