[linux-2.6-block.git] / drivers / irqchip / irq-gic-v2m.c

/*
 * ARM GIC v2m MSI(-X) support
 * Support for Message Signaled Interrupts for systems that
 * implement ARM Generic Interrupt Controller: GICv2m.
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
 *	    Brandon Anderson <brandon.anderson@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#define pr_fmt(fmt) "GICv2m: " fmt

#include <linux/acpi.h>
#include <linux/dma-iommu.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irqchip/arm-gic.h>

/*
* MSI_TYPER:
*     [31:26] Reserved
*     [25:16] lowest SPI assigned to MSI
*     [15:10] Reserved
*     [9:0]   Numer of SPIs assigned to MSI
*/
#define V2M_MSI_TYPER		       0x008
#define V2M_MSI_TYPER_BASE_SHIFT       16
#define V2M_MSI_TYPER_BASE_MASK	       0x3FF
#define V2M_MSI_TYPER_NUM_MASK	       0x3FF
#define V2M_MSI_SETSPI_NS	       0x040
#define V2M_MIN_SPI		       32
#define V2M_MAX_SPI		       1019
#define V2M_MSI_IIDR		       0xFCC

#define V2M_MSI_TYPER_BASE_SPI(x)      \
	       (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)

#define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)

/* APM X-Gene with GICv2m MSI_IIDR register value */
#define XGENE_GICV2M_MSI_IIDR		0x06000170

/* Broadcom NS2 GICv2m MSI_IIDR register value */
#define BCM_NS2_GICV2M_MSI_IIDR		0x0000013f

/* List of flags for specific v2m implementation */
#define GICV2M_NEEDS_SPI_OFFSET		0x00000001

static LIST_HEAD(v2m_nodes);
static DEFINE_SPINLOCK(v2m_lock);

struct v2m_data {
	struct list_head entry;
	struct fwnode_handle *fwnode;
	struct resource res;	/* GICv2m resource */
	void __iomem *base;	/* GICv2m virt address */
	u32 spi_start;		/* The SPI number that MSIs start */
	u32 nr_spis;		/* The number of SPIs for MSIs */
	u32 spi_offset;		/* offset to be subtracted from SPI number */
	unsigned long *bm;	/* MSI vector bitmap */
	u32 flags;		/* v2m flags for specific implementation */
};

static void gicv2m_mask_msi_irq(struct irq_data *d)
{
	pci_msi_mask_irq(d);
	irq_chip_mask_parent(d);
}

static void gicv2m_unmask_msi_irq(struct irq_data *d)
{
	pci_msi_unmask_irq(d);
	irq_chip_unmask_parent(d);
}

static struct irq_chip gicv2m_msi_irq_chip = {
	.name			= "MSI",
	.irq_mask		= gicv2m_mask_msi_irq,
	.irq_unmask		= gicv2m_unmask_msi_irq,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
};

static struct msi_domain_info gicv2m_msi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
		   MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
	.chip	= &gicv2m_msi_irq_chip,
};

static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;

	msg->address_hi = upper_32_bits(addr);
	msg->address_lo = lower_32_bits(addr);
	msg->data = data->hwirq;

	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
		msg->data -= v2m->spi_offset;

	iommu_dma_map_msi_msg(data->irq, msg);
}

static struct irq_chip gicv2m_irq_chip = {
	.name			= "GICv2m",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,
};

static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
				       unsigned int virq,
				       irq_hw_number_t hwirq)
{
	struct irq_fwspec fwspec;
	struct irq_data *d;
	int err;

	if (is_of_node(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 3;
		fwspec.param[0] = 0;
		fwspec.param[1] = hwirq - 32;
		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 2;
		fwspec.param[0] = hwirq;
		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
	} else {
		return -EINVAL;
	}

	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
	if (err)
		return err;

	/* Configure the interrupt line to be edge */
	d = irq_domain_get_irq_data(domain->parent, virq);
	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
			       int nr_irqs)
{
	spin_lock(&v2m_lock);
	bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
			      get_count_order(nr_irqs));
	spin_unlock(&v2m_lock);
}

static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *args)
{
	struct v2m_data *v2m = NULL, *tmp;
	int hwirq, offset, i, err = 0;

	spin_lock(&v2m_lock);
	list_for_each_entry(tmp, &v2m_nodes, entry) {
		offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
						 get_count_order(nr_irqs));
		if (offset >= 0) {
			v2m = tmp;
			break;
		}
	}
	spin_unlock(&v2m_lock);

	if (!v2m)
		return -ENOSPC;

	hwirq = v2m->spi_start + offset;

	for (i = 0; i < nr_irqs; i++) {
		err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
		if (err)
			goto fail;

		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &gicv2m_irq_chip, v2m);
	}

	return 0;

fail:
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
	gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
	return err;
}

static void gicv2m_irq_domain_free(struct irq_domain *domain,
				   unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);

	gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops gicv2m_domain_ops = {
	.alloc			= gicv2m_irq_domain_alloc,
	.free			= gicv2m_irq_domain_free,
};

static bool is_msi_spi_valid(u32 base, u32 num)
{
	if (base < V2M_MIN_SPI) {
		pr_err("Invalid MSI base SPI (base:%u)\n", base);
		return false;
	}

	if ((num == 0) || (base + num > V2M_MAX_SPI)) {
		pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
		return false;
	}

	return true;
}

static struct irq_chip gicv2m_pmsi_irq_chip = {
	.name			= "pMSI",
};

static struct msi_domain_ops gicv2m_pmsi_ops = {
};

static struct msi_domain_info gicv2m_pmsi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
	.ops	= &gicv2m_pmsi_ops,
	.chip	= &gicv2m_pmsi_irq_chip,
};

static void gicv2m_teardown(void)
{
	struct v2m_data *v2m, *tmp;

	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
		list_del(&v2m->entry);
		kfree(v2m->bm);
		iounmap(v2m->base);
		of_node_put(to_of_node(v2m->fwnode));
		if (is_fwnode_irqchip(v2m->fwnode))
			irq_domain_free_fwnode(v2m->fwnode);
		kfree(v2m);
	}
}

static int gicv2m_allocate_domains(struct irq_domain *parent)
{
	struct irq_domain *inner_domain, *pci_domain, *plat_domain;
	struct v2m_data *v2m;

	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!v2m)
		return 0;

	inner_domain = irq_domain_create_tree(v2m->fwnode,
					      &gicv2m_domain_ops, v2m);
	if (!inner_domain) {
		pr_err("Failed to create GICv2m domain\n");
		return -ENOMEM;
	}

	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
	inner_domain->parent = parent;
	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
					       &gicv2m_msi_domain_info,
					       inner_domain);
	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
						     &gicv2m_pmsi_domain_info,
						     inner_domain);
	if (!pci_domain || !plat_domain) {
		pr_err("Failed to create MSI domains\n");
		if (plat_domain)
			irq_domain_remove(plat_domain);
		if (pci_domain)
			irq_domain_remove(pci_domain);
		irq_domain_remove(inner_domain);
		return -ENOMEM;
	}

	return 0;
}

static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
				  u32 spi_start, u32 nr_spis,
				  struct resource *res)
{
	int ret;
	struct v2m_data *v2m;

	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	if (!v2m) {
		pr_err("Failed to allocate struct v2m_data.\n");
		return -ENOMEM;
	}

	INIT_LIST_HEAD(&v2m->entry);
	v2m->fwnode = fwnode;

	memcpy(&v2m->res, res, sizeof(struct resource));

	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	if (!v2m->base) {
		pr_err("Failed to map GICv2m resource\n");
		ret = -ENOMEM;
		goto err_free_v2m;
	}

	if (spi_start && nr_spis) {
		v2m->spi_start = spi_start;
		v2m->nr_spis = nr_spis;
	} else {
		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);

		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	}

	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
		ret = -EINVAL;
		goto err_iounmap;
	}

	/*
	 * APM X-Gene GICv2m implementation has an erratum where
	 * the MSI data needs to be the offset from the spi_start
	 * in order to trigger the correct MSI interrupt. This is
	 * different from the standard GICv2m implementation where
	 * the MSI data is the absolute value within the range from
	 * spi_start to (spi_start + num_spis).
	 *
	 * Broadom NS2 GICv2m implementation has an erratum where the MSI data
	 * is 'spi_number - 32'
	 */
	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
	case XGENE_GICV2M_MSI_IIDR:
		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
		v2m->spi_offset = v2m->spi_start;
		break;
	case BCM_NS2_GICV2M_MSI_IIDR:
		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
		v2m->spi_offset = 32;
		break;
	}

	v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
			  GFP_KERNEL);
	if (!v2m->bm) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	list_add_tail(&v2m->entry, &v2m_nodes);

	pr_info("range%pR, SPI[%d:%d]\n", res,
		v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
	return 0;

err_iounmap:
	iounmap(v2m->base);
err_free_v2m:
	kfree(v2m);
	return ret;
}

static struct of_device_id gicv2m_device_id[] = {
	{	.compatible	= "arm,gic-v2m-frame",	},
	{},
};

static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
				 struct irq_domain *parent)
{
	int ret = 0;
	struct device_node *node = to_of_node(parent_handle);
	struct device_node *child;

	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	     child = of_find_matching_node(child, gicv2m_device_id)) {
		u32 spi_start = 0, nr_spis = 0;
		struct resource res;

		if (!of_find_property(child, "msi-controller", NULL))
			continue;

		ret = of_address_to_resource(child, 0, &res);
		if (ret) {
			pr_err("Failed to allocate v2m resource.\n");
			break;
		}

		if (!of_property_read_u32(child, "arm,msi-base-spi",
					  &spi_start) &&
		    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
				spi_start, nr_spis);

		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
		if (ret) {
			of_node_put(child);
			break;
		}
	}

	if (!ret)
		ret = gicv2m_allocate_domains(parent);
	if (ret)
		gicv2m_teardown();
	return ret;
}

#ifdef CONFIG_ACPI
static int acpi_num_msi;

static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
{
	struct v2m_data *data;

	if (WARN_ON(acpi_num_msi <= 0))
		return NULL;

	/* We only return the fwnode of the first MSI frame. */
	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!data)
		return NULL;

	return data->fwnode;
}

static int __init
acpi_parse_madt_msi(union acpi_subtable_headers *header,
		    const unsigned long end)
{
	int ret;
	struct resource res;
	u32 spi_start = 0, nr_spis = 0;
	struct acpi_madt_generic_msi_frame *m;
	struct fwnode_handle *fwnode;

	m = (struct acpi_madt_generic_msi_frame *)header;
	if (BAD_MADT_ENTRY(m, end))
		return -EINVAL;

	res.start = m->base_address;
	res.end = m->base_address + SZ_4K - 1;
	res.flags = IORESOURCE_MEM;

	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
		spi_start = m->spi_base;
		nr_spis = m->spi_count;

		pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
			spi_start, nr_spis);
	}

	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	if (!fwnode) {
		pr_err("Unable to allocate GICv2m domain token\n");
		return -EINVAL;
	}

	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	if (ret)
		irq_domain_free_fwnode(fwnode);

	return ret;
}

static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	int ret;

	if (acpi_num_msi > 0)
		return 0;

	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
				      acpi_parse_madt_msi, 0);

	if (acpi_num_msi <= 0)
		goto err_out;

	ret = gicv2m_allocate_domains(parent);
	if (ret)
		goto err_out;

	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);

	return 0;

err_out:
	gicv2m_teardown();
	return -EINVAL;
}
#else /* CONFIG_ACPI */
static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	return -EINVAL;
}
#endif /* CONFIG_ACPI */

int __init gicv2m_init(struct fwnode_handle *parent_handle,
		       struct irq_domain *parent)
{
	if (is_of_node(parent_handle))
		return gicv2m_of_init(parent_handle, parent);

	return gicv2m_acpi_init(parent);
}
Commit	Line	Data
853a33ce SS	1	/*
	2	* ARM GIC v2m MSI(-X) support
	3	* Support for Message Signaled Interrupts for systems that
	4	* implement ARM Generic Interrupt Controller: GICv2m.
	5	*
	6	* Copyright (C) 2014 Advanced Micro Devices, Inc.
	7	* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
	8	* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
	9	* Brandon Anderson <brandon.anderson@amd.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published
	13	* by the Free Software Foundation.
	14	*/
	15
	16	#define pr_fmt(fmt) "GICv2m: " fmt
	17
0644b3da	18	#include <linux/acpi.h>
44bb7e24	19	#include <linux/dma-iommu.h>
853a33ce SS	20	#include <linux/irq.h>
	21	#include <linux/irqdomain.h>
	22	#include <linux/kernel.h>
0644b3da	23	#include <linux/msi.h>
853a33ce SS	24	#include <linux/of_address.h>
	25	#include <linux/of_pci.h>
	26	#include <linux/slab.h>
	27	#include <linux/spinlock.h>
7c034f16	28	#include <linux/irqchip/arm-gic.h>
853a33ce SS	29
	30	/*
	31	* MSI_TYPER:
	32	* [31:26] Reserved
	33	* [25:16] lowest SPI assigned to MSI
	34	* [15:10] Reserved
	35	* [9:0] Numer of SPIs assigned to MSI
	36	*/
	37	#define V2M_MSI_TYPER 0x008
	38	#define V2M_MSI_TYPER_BASE_SHIFT 16
	39	#define V2M_MSI_TYPER_BASE_MASK 0x3FF
	40	#define V2M_MSI_TYPER_NUM_MASK 0x3FF
	41	#define V2M_MSI_SETSPI_NS 0x040
	42	#define V2M_MIN_SPI 32
	43	#define V2M_MAX_SPI 1019
ee5f7d64	44	#define V2M_MSI_IIDR 0xFCC
853a33ce SS	45
	46	#define V2M_MSI_TYPER_BASE_SPI(x) \
	47	(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
	48
	49	#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
	50
ee5f7d64 DD	51	/* APM X-Gene with GICv2m MSI_IIDR register value */
	52	#define XGENE_GICV2M_MSI_IIDR 0x06000170
	53
74c967aa RJ	54	/* Broadcom NS2 GICv2m MSI_IIDR register value */
	55	#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
	56
ee5f7d64 DD	57	/* List of flags for specific v2m implementation */
	58	#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
	59
a71225e2 MZ	60	static LIST_HEAD(v2m_nodes);
	61	static DEFINE_SPINLOCK(v2m_lock);
	62
853a33ce	63	struct v2m_data {
a71225e2	64	struct list_head entry;
4266ab1a	65	struct fwnode_handle *fwnode;
853a33ce SS	66	struct resource res; /* GICv2m resource */
	67	void __iomem base; / GICv2m virt address */
	68	u32 spi_start; /* The SPI number that MSIs start */
	69	u32 nr_spis; /* The number of SPIs for MSIs */
74c967aa	70	u32 spi_offset; /* offset to be subtracted from SPI number */
853a33ce	71	unsigned long bm; / MSI vector bitmap */
ee5f7d64	72	u32 flags; /* v2m flags for specific implementation */
853a33ce SS	73	};
	74
	75	static void gicv2m_mask_msi_irq(struct irq_data *d)
	76	{
	77	pci_msi_mask_irq(d);
	78	irq_chip_mask_parent(d);
	79	}
	80
	81	static void gicv2m_unmask_msi_irq(struct irq_data *d)
	82	{
	83	pci_msi_unmask_irq(d);
	84	irq_chip_unmask_parent(d);
	85	}
	86
	87	static struct irq_chip gicv2m_msi_irq_chip = {
	88	.name = "MSI",
	89	.irq_mask = gicv2m_mask_msi_irq,
	90	.irq_unmask = gicv2m_unmask_msi_irq,
	91	.irq_eoi = irq_chip_eoi_parent,
	92	.irq_write_msi_msg = pci_msi_domain_write_msg,
	93	};
	94
	95	static struct msi_domain_info gicv2m_msi_domain_info = {
	96	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
de337ee3	97	MSI_FLAG_PCI_MSIX \| MSI_FLAG_MULTI_PCI_MSI),
853a33ce SS	98	.chip = &gicv2m_msi_irq_chip,
	99	};
	100
853a33ce SS	101	static void gicv2m_compose_msi_msg(struct irq_data data, struct msi_msg msg)
	102	{
	103	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	104	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
	105
157add60 PF	106	msg->address_hi = upper_32_bits(addr);
157add60 PF	107	msg->address_lo = lower_32_bits(addr);
853a33ce	108	msg->data = data->hwirq;
ee5f7d64 DD	109
ee5f7d64 DD	110	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
74c967aa	111	msg->data -= v2m->spi_offset;
44bb7e24 RM	112
44bb7e24 RM	113	iommu_dma_map_msi_msg(data->irq, msg);
853a33ce SS	114	}
	115
	116	static struct irq_chip gicv2m_irq_chip = {
	117	.name = "GICv2m",
	118	.irq_mask = irq_chip_mask_parent,
	119	.irq_unmask = irq_chip_unmask_parent,
	120	.irq_eoi = irq_chip_eoi_parent,
0407dace	121	.irq_set_affinity = irq_chip_set_affinity_parent,
853a33ce SS	122	.irq_compose_msi_msg = gicv2m_compose_msi_msg,
	123	};
	124
	125	static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
	126	unsigned int virq,
	127	irq_hw_number_t hwirq)
	128	{
f833f57f	129	struct irq_fwspec fwspec;
853a33ce SS	130	struct irq_data *d;
	131	int err;
	132
f833f57f MZ	133	if (is_of_node(domain->parent->fwnode)) {
	134	fwspec.fwnode = domain->parent->fwnode;
	135	fwspec.param_count = 3;
	136	fwspec.param[0] = 0;
	137	fwspec.param[1] = hwirq - 32;
	138	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0644b3da SS	139	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
	140	fwspec.fwnode = domain->parent->fwnode;
	141	fwspec.param_count = 2;
	142	fwspec.param[0] = hwirq;
	143	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
f833f57f MZ	144	} else {
	145	return -EINVAL;
	146	}
853a33ce	147
f833f57f	148	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
853a33ce SS	149	if (err)
	150	return err;
	151
	152	/* Configure the interrupt line to be edge */
	153	d = irq_domain_get_irq_data(domain->parent, virq);
	154	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	155	return 0;
	156	}
	157
de337ee3 MZ	158	static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
de337ee3 MZ	159	int nr_irqs)
853a33ce	160	{
a71225e2	161	spin_lock(&v2m_lock);
de337ee3 MZ	162	bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
de337ee3 MZ	163	get_count_order(nr_irqs));
a71225e2	164	spin_unlock(&v2m_lock);
853a33ce SS	165	}
	166
	167	static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	168	unsigned int nr_irqs, void *args)
	169	{
a71225e2	170	struct v2m_data v2m = NULL, tmp;
de337ee3	171	int hwirq, offset, i, err = 0;
853a33ce	172
a71225e2 MZ	173	spin_lock(&v2m_lock);
a71225e2 MZ	174	list_for_each_entry(tmp, &v2m_nodes, entry) {
de337ee3 MZ	175	offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
	176	get_count_order(nr_irqs));
	177	if (offset >= 0) {
a71225e2 MZ	178	v2m = tmp;
	179	break;
	180	}
	181	}
	182	spin_unlock(&v2m_lock);
853a33ce	183
a71225e2 MZ	184	if (!v2m)
a71225e2 MZ	185	return -ENOSPC;
853a33ce SS	186
	187	hwirq = v2m->spi_start + offset;
	188
de337ee3 MZ	189	for (i = 0; i < nr_irqs; i++) {
	190	err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
	191	if (err)
	192	goto fail;
853a33ce	193
de337ee3 MZ	194	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	195	&gicv2m_irq_chip, v2m);
	196	}
853a33ce SS	197
853a33ce SS	198	return 0;
de337ee3 MZ	199
	200	fail:
	201	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
cbaf45a6	202	gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
de337ee3	203	return err;
853a33ce SS	204	}
	205
	206	static void gicv2m_irq_domain_free(struct irq_domain *domain,
	207	unsigned int virq, unsigned int nr_irqs)
	208	{
	209	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	210	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
	211
de337ee3	212	gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
853a33ce SS	213	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
	214	}
	215
	216	static const struct irq_domain_ops gicv2m_domain_ops = {
	217	.alloc = gicv2m_irq_domain_alloc,
	218	.free = gicv2m_irq_domain_free,
	219	};
	220
	221	static bool is_msi_spi_valid(u32 base, u32 num)
	222	{
	223	if (base < V2M_MIN_SPI) {
	224	pr_err("Invalid MSI base SPI (base:%u)\n", base);
	225	return false;
	226	}
	227
	228	if ((num == 0) \|\| (base + num > V2M_MAX_SPI)) {
	229	pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
	230	num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
	231	return false;
	232	}
	233
	234	return true;
	235	}
	236
ef50645a MZ	237	static struct irq_chip gicv2m_pmsi_irq_chip = {
	238	.name = "pMSI",
	239	};
	240
	241	static struct msi_domain_ops gicv2m_pmsi_ops = {
	242	};
	243
	244	static struct msi_domain_info gicv2m_pmsi_domain_info = {
	245	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS),
	246	.ops = &gicv2m_pmsi_ops,
	247	.chip = &gicv2m_pmsi_irq_chip,
	248	};
	249
a71225e2 MZ	250	static void gicv2m_teardown(void)
	251	{
	252	struct v2m_data v2m, tmp;
	253
	254	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
	255	list_del(&v2m->entry);
	256	kfree(v2m->bm);
	257	iounmap(v2m->base);
4266ab1a	258	of_node_put(to_of_node(v2m->fwnode));
0644b3da SS	259	if (is_fwnode_irqchip(v2m->fwnode))
0644b3da SS	260	irq_domain_free_fwnode(v2m->fwnode);
a71225e2 MZ	261	kfree(v2m);
	262	}
	263	}
	264
	265	static int gicv2m_allocate_domains(struct irq_domain *parent)
	266	{
	267	struct irq_domain inner_domain, pci_domain, *plat_domain;
	268	struct v2m_data *v2m;
	269
	270	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	271	if (!v2m)
	272	return 0;
	273
4266ab1a	274	inner_domain = irq_domain_create_tree(v2m->fwnode,
a71225e2 MZ	275	&gicv2m_domain_ops, v2m);
	276	if (!inner_domain) {
	277	pr_err("Failed to create GICv2m domain\n");
	278	return -ENOMEM;
	279	}
	280
96f0d93a	281	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
a71225e2	282	inner_domain->parent = parent;
4266ab1a	283	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	284	&gicv2m_msi_domain_info,
a71225e2 MZ	285	inner_domain);
4266ab1a	286	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	287	&gicv2m_pmsi_domain_info,
	288	inner_domain);
	289	if (!pci_domain \|\| !plat_domain) {
	290	pr_err("Failed to create MSI domains\n");
	291	if (plat_domain)
	292	irq_domain_remove(plat_domain);
	293	if (pci_domain)
	294	irq_domain_remove(pci_domain);
	295	irq_domain_remove(inner_domain);
	296	return -ENOMEM;
	297	}
	298
	299	return 0;
	300	}
	301
4266ab1a SS	302	static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
	303	u32 spi_start, u32 nr_spis,
	304	struct resource *res)
853a33ce SS	305	{
	306	int ret;
	307	struct v2m_data *v2m;
	308
	309	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	310	if (!v2m) {
	311	pr_err("Failed to allocate struct v2m_data.\n");
	312	return -ENOMEM;
	313	}
	314
a71225e2	315	INIT_LIST_HEAD(&v2m->entry);
4266ab1a	316	v2m->fwnode = fwnode;
a71225e2	317
4266ab1a	318	memcpy(&v2m->res, res, sizeof(struct resource));
853a33ce SS	319
	320	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	321	if (!v2m->base) {
	322	pr_err("Failed to map GICv2m resource\n");
	323	ret = -ENOMEM;
	324	goto err_free_v2m;
	325	}
	326
4266ab1a SS	327	if (spi_start && nr_spis) {
	328	v2m->spi_start = spi_start;
	329	v2m->nr_spis = nr_spis;
853a33ce SS	330	} else {
	331	u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
	332
	333	v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
	334	v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	335	}
	336
	337	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
	338	ret = -EINVAL;
	339	goto err_iounmap;
	340	}
	341
ee5f7d64 DD	342	/*
	343	* APM X-Gene GICv2m implementation has an erratum where
	344	* the MSI data needs to be the offset from the spi_start
	345	* in order to trigger the correct MSI interrupt. This is
	346	* different from the standard GICv2m implementation where
	347	* the MSI data is the absolute value within the range from
	348	* spi_start to (spi_start + num_spis).
74c967aa RJ	349	*
	350	* Broadom NS2 GICv2m implementation has an erratum where the MSI data
	351	* is 'spi_number - 32'
ee5f7d64	352	*/
74c967aa RJ	353	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
	354	case XGENE_GICV2M_MSI_IIDR:
	355	v2m->flags \|= GICV2M_NEEDS_SPI_OFFSET;
	356	v2m->spi_offset = v2m->spi_start;
	357	break;
	358	case BCM_NS2_GICV2M_MSI_IIDR:
ee5f7d64	359	v2m->flags \|= GICV2M_NEEDS_SPI_OFFSET;
74c967aa RJ	360	v2m->spi_offset = 32;
	361	break;
	362	}
ee5f7d64	363
6396bb22	364	v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
853a33ce SS	365	GFP_KERNEL);
	366	if (!v2m->bm) {
	367	ret = -ENOMEM;
	368	goto err_iounmap;
	369	}
	370
a71225e2	371	list_add_tail(&v2m->entry, &v2m_nodes);
853a33ce	372
5a1ff480 SS	373	pr_info("range%pR, SPI[%d:%d]\n", res,
5a1ff480 SS	374	v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
853a33ce SS	375	return 0;
853a33ce SS	376
853a33ce SS	377	err_iounmap:
	378	iounmap(v2m->base);
	379	err_free_v2m:
	380	kfree(v2m);
	381	return ret;
	382	}
	383
	384	static struct of_device_id gicv2m_device_id[] = {
	385	{ .compatible = "arm,gic-v2m-frame", },
	386	{},
	387	};
	388
0644b3da SS	389	static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
0644b3da SS	390	struct irq_domain *parent)
853a33ce SS	391	{
853a33ce SS	392	int ret = 0;
0644b3da	393	struct device_node *node = to_of_node(parent_handle);
853a33ce SS	394	struct device_node *child;
	395
	396	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	397	child = of_find_matching_node(child, gicv2m_device_id)) {
4266ab1a SS	398	u32 spi_start = 0, nr_spis = 0;
	399	struct resource res;
	400
853a33ce SS	401	if (!of_find_property(child, "msi-controller", NULL))
	402	continue;
	403
4266ab1a SS	404	ret = of_address_to_resource(child, 0, &res);
	405	if (ret) {
	406	pr_err("Failed to allocate v2m resource.\n");
	407	break;
	408	}
	409
	410	if (!of_property_read_u32(child, "arm,msi-base-spi",
	411	&spi_start) &&
	412	!of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
	413	pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	414	spi_start, nr_spis);
	415
	416	ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
853a33ce	417	if (ret) {
86d14c72	418	of_node_put(child);
853a33ce SS	419	break;
	420	}
	421	}
	422
a71225e2 MZ	423	if (!ret)
	424	ret = gicv2m_allocate_domains(parent);
	425	if (ret)
	426	gicv2m_teardown();
853a33ce SS	427	return ret;
853a33ce SS	428	}
0644b3da SS	429
	430	#ifdef CONFIG_ACPI
	431	static int acpi_num_msi;
	432
	433	static struct fwnode_handle gicv2m_get_fwnode(struct device dev)
	434	{
	435	struct v2m_data *data;
	436
	437	if (WARN_ON(acpi_num_msi <= 0))
	438	return NULL;
	439
	440	/* We only return the fwnode of the first MSI frame. */
	441	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	442	if (!data)
	443	return NULL;
	444
	445	return data->fwnode;
	446	}
	447
	448	static int __init
60574d1e	449	acpi_parse_madt_msi(union acpi_subtable_headers *header,
0644b3da SS	450	const unsigned long end)
	451	{
	452	int ret;
	453	struct resource res;
	454	u32 spi_start = 0, nr_spis = 0;
	455	struct acpi_madt_generic_msi_frame *m;
	456	struct fwnode_handle *fwnode;
	457
	458	m = (struct acpi_madt_generic_msi_frame *)header;
	459	if (BAD_MADT_ENTRY(m, end))
	460	return -EINVAL;
	461
	462	res.start = m->base_address;
5a1ff480 SS	463	res.end = m->base_address + SZ_4K - 1;
5a1ff480 SS	464	res.flags = IORESOURCE_MEM;
0644b3da SS	465
	466	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
	467	spi_start = m->spi_base;
	468	nr_spis = m->spi_count;
	469
	470	pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	471	spi_start, nr_spis);
	472	}
	473
	474	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	475	if (!fwnode) {
	476	pr_err("Unable to allocate GICv2m domain token\n");
	477	return -EINVAL;
	478	}
	479
	480	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	481	if (ret)
	482	irq_domain_free_fwnode(fwnode);
	483
	484	return ret;
	485	}
	486
	487	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	488	{
	489	int ret;
	490
	491	if (acpi_num_msi > 0)
	492	return 0;
	493
	494	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
	495	acpi_parse_madt_msi, 0);
	496
	497	if (acpi_num_msi <= 0)
	498	goto err_out;
	499
	500	ret = gicv2m_allocate_domains(parent);
	501	if (ret)
	502	goto err_out;
	503
	504	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
	505
	506	return 0;
	507
	508	err_out:
	509	gicv2m_teardown();
	510	return -EINVAL;
	511	}
	512	#else /* CONFIG_ACPI */
	513	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	514	{
	515	return -EINVAL;
	516	}
	517	#endif /* CONFIG_ACPI */
	518
	519	int __init gicv2m_init(struct fwnode_handle *parent_handle,
	520	struct irq_domain *parent)
	521	{
	522	if (is_of_node(parent_handle))
	523	return gicv2m_of_init(parent_handle, parent);
	524
	525	return gicv2m_acpi_init(parent);
	526	}