Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d51d0af4 MZ |
2 | /* |
3 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
d51d0af4 MZ |
4 | */ |
5 | ||
6 | #include <linux/interrupt.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/irq.h> | |
9 | #include <linux/irqchip/arm-gic.h> | |
10 | ||
11 | #include "irq-gic-common.h" | |
12 | ||
aa08192a AB |
13 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
14 | ||
502d6df1 JG |
15 | static const struct gic_kvm_info *gic_kvm_info; |
16 | ||
17 | const struct gic_kvm_info *gic_get_kvm_info(void) | |
18 | { | |
19 | return gic_kvm_info; | |
20 | } | |
21 | ||
22 | void gic_set_kvm_info(const struct gic_kvm_info *info) | |
23 | { | |
24 | BUG_ON(gic_kvm_info != NULL); | |
25 | gic_kvm_info = info; | |
26 | } | |
27 | ||
f70fdb42 SK |
28 | void gic_enable_of_quirks(const struct device_node *np, |
29 | const struct gic_quirk *quirks, void *data) | |
30 | { | |
31 | for (; quirks->desc; quirks++) { | |
32 | if (!of_device_is_compatible(np, quirks->compatible)) | |
33 | continue; | |
34 | if (quirks->init(data)) | |
35 | pr_info("GIC: enabling workaround for %s\n", | |
36 | quirks->desc); | |
37 | } | |
38 | } | |
39 | ||
67510cca RR |
40 | void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, |
41 | void *data) | |
42 | { | |
43 | for (; quirks->desc; quirks++) { | |
25edaed6 MZ |
44 | if (quirks->compatible) |
45 | continue; | |
67510cca RR |
46 | if (quirks->iidr != (quirks->mask & iidr)) |
47 | continue; | |
9d111d49 AB |
48 | if (quirks->init(data)) |
49 | pr_info("GIC: enabling workaround for %s\n", | |
50 | quirks->desc); | |
67510cca RR |
51 | } |
52 | } | |
53 | ||
fb7e7deb | 54 | int gic_configure_irq(unsigned int irq, unsigned int type, |
d51d0af4 MZ |
55 | void __iomem *base, void (*sync_access)(void)) |
56 | { | |
d51d0af4 MZ |
57 | u32 confmask = 0x2 << ((irq % 16) * 2); |
58 | u32 confoff = (irq / 16) * 4; | |
fb7e7deb LD |
59 | u32 val, oldval; |
60 | int ret = 0; | |
aa08192a | 61 | unsigned long flags; |
d51d0af4 MZ |
62 | |
63 | /* | |
64 | * Read current configuration register, and insert the config | |
65 | * for "irq", depending on "type". | |
66 | */ | |
aa08192a | 67 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
13d22e2e | 68 | val = oldval = readl_relaxed(base + confoff); |
fb7e7deb | 69 | if (type & IRQ_TYPE_LEVEL_MASK) |
d51d0af4 | 70 | val &= ~confmask; |
fb7e7deb | 71 | else if (type & IRQ_TYPE_EDGE_BOTH) |
d51d0af4 MZ |
72 | val |= confmask; |
73 | ||
ec1a454d | 74 | /* If the current configuration is the same, then we are done */ |
aa08192a AB |
75 | if (val == oldval) { |
76 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
ec1a454d | 77 | return 0; |
aa08192a | 78 | } |
ec1a454d | 79 | |
d51d0af4 MZ |
80 | /* |
81 | * Write back the new configuration, and possibly re-enable | |
992345a5 JH |
82 | * the interrupt. If we fail to write a new configuration for |
83 | * an SPI then WARN and return an error. If we fail to write the | |
84 | * configuration for a PPI this is most likely because the GIC | |
85 | * does not allow us to set the configuration or we are in a | |
86 | * non-secure mode, and hence it may not be catastrophic. | |
d51d0af4 | 87 | */ |
13d22e2e MZ |
88 | writel_relaxed(val, base + confoff); |
89 | if (readl_relaxed(base + confoff) != val) | |
90 | ret = -EINVAL; | |
91 | ||
aa08192a | 92 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d51d0af4 | 93 | |
d51d0af4 MZ |
94 | if (sync_access) |
95 | sync_access(); | |
fb7e7deb LD |
96 | |
97 | return ret; | |
d51d0af4 MZ |
98 | } |
99 | ||
cdbb813d JH |
100 | void gic_dist_config(void __iomem *base, int gic_irqs, |
101 | void (*sync_access)(void)) | |
d51d0af4 MZ |
102 | { |
103 | unsigned int i; | |
104 | ||
105 | /* | |
106 | * Set all global interrupts to be level triggered, active low. | |
107 | */ | |
108 | for (i = 32; i < gic_irqs; i += 16) | |
e5f81539 FK |
109 | writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, |
110 | base + GIC_DIST_CONFIG + i / 4); | |
d51d0af4 MZ |
111 | |
112 | /* | |
113 | * Set priority on all global interrupts. | |
114 | */ | |
115 | for (i = 32; i < gic_irqs; i += 4) | |
e5f81539 | 116 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); |
d51d0af4 MZ |
117 | |
118 | /* | |
0eece2b2 MZ |
119 | * Deactivate and disable all SPIs. Leave the PPI and SGIs |
120 | * alone as they are in the redistributor registers on GICv3. | |
d51d0af4 | 121 | */ |
0eece2b2 | 122 | for (i = 32; i < gic_irqs; i += 32) { |
e5f81539 | 123 | writel_relaxed(GICD_INT_EN_CLR_X32, |
0eece2b2 MZ |
124 | base + GIC_DIST_ACTIVE_CLEAR + i / 8); |
125 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
126 | base + GIC_DIST_ENABLE_CLEAR + i / 8); | |
127 | } | |
d51d0af4 MZ |
128 | |
129 | if (sync_access) | |
130 | sync_access(); | |
131 | } | |
132 | ||
1a60e1e6 | 133 | void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)) |
d51d0af4 MZ |
134 | { |
135 | int i; | |
136 | ||
137 | /* | |
138 | * Deal with the banked PPI and SGI interrupts - disable all | |
1a60e1e6 | 139 | * private interrupts. Make sure everything is deactivated. |
d51d0af4 | 140 | */ |
1a60e1e6 MZ |
141 | for (i = 0; i < nr; i += 32) { |
142 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
143 | base + GIC_DIST_ACTIVE_CLEAR + i / 8); | |
144 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
145 | base + GIC_DIST_ENABLE_CLEAR + i / 8); | |
146 | } | |
d51d0af4 MZ |
147 | |
148 | /* | |
149 | * Set priority on PPI and SGI interrupts | |
150 | */ | |
1a60e1e6 | 151 | for (i = 0; i < nr; i += 4) |
e5f81539 FK |
152 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
153 | base + GIC_DIST_PRI + i * 4 / 4); | |
d51d0af4 MZ |
154 | |
155 | if (sync_access) | |
156 | sync_access(); | |
157 | } |