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7f646e92 FF |
1 | /* |
2 | * Generic Broadcom Set Top Box Level 2 Interrupt controller driver | |
3 | * | |
49aa6ef0 | 4 | * Copyright (C) 2014-2017 Broadcom |
7f646e92 FF |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
05f12757 | 22 | #include <linux/spinlock.h> |
7f646e92 FF |
23 | #include <linux/of.h> |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_platform.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/irqdomain.h> | |
31 | #include <linux/irqchip.h> | |
32 | #include <linux/irqchip/chained_irq.h> | |
33 | ||
c0ca7262 DB |
34 | struct brcmstb_intc_init_params { |
35 | irq_flow_handler_t handler; | |
36 | int cpu_status; | |
37 | int cpu_clear; | |
38 | int cpu_mask_status; | |
39 | int cpu_mask_set; | |
40 | int cpu_mask_clear; | |
41 | }; | |
42 | ||
43 | /* Register offsets in the L2 latched interrupt controller */ | |
44 | static const struct brcmstb_intc_init_params l2_edge_intc_init = { | |
45 | .handler = handle_edge_irq, | |
46 | .cpu_status = 0x00, | |
47 | .cpu_clear = 0x08, | |
48 | .cpu_mask_status = 0x0c, | |
49 | .cpu_mask_set = 0x10, | |
50 | .cpu_mask_clear = 0x14 | |
51 | }; | |
52 | ||
53 | /* Register offsets in the L2 level interrupt controller */ | |
54 | static const struct brcmstb_intc_init_params l2_lvl_intc_init = { | |
55 | .handler = handle_level_irq, | |
56 | .cpu_status = 0x00, | |
57 | .cpu_clear = -1, /* Register not present */ | |
58 | .cpu_mask_status = 0x04, | |
59 | .cpu_mask_set = 0x08, | |
60 | .cpu_mask_clear = 0x0C | |
61 | }; | |
7f646e92 FF |
62 | |
63 | /* L2 intc private data structure */ | |
64 | struct brcmstb_l2_intc_data { | |
7f646e92 | 65 | struct irq_domain *domain; |
49aa6ef0 | 66 | struct irq_chip_generic *gc; |
8480ca47 DB |
67 | int status_offset; |
68 | int mask_offset; | |
7f646e92 FF |
69 | bool can_wake; |
70 | u32 saved_mask; /* for suspend/resume */ | |
71 | }; | |
72 | ||
49aa6ef0 DB |
73 | /** |
74 | * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt | |
75 | * @d: irq_data | |
76 | * | |
77 | * Chip has separate enable/disable registers instead of a single mask | |
78 | * register and pending interrupt is acknowledged by setting a bit. | |
79 | * | |
80 | * Note: This function is generic and could easily be added to the | |
81 | * generic irqchip implementation if there ever becomes a will to do so. | |
82 | * Perhaps with a name like irq_gc_mask_disable_and_ack_set(). | |
83 | * | |
84 | * e.g.: https://patchwork.kernel.org/patch/9831047/ | |
85 | */ | |
86 | static void brcmstb_l2_mask_and_ack(struct irq_data *d) | |
87 | { | |
88 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
89 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
90 | u32 mask = d->mask; | |
91 | ||
92 | irq_gc_lock(gc); | |
93 | irq_reg_writel(gc, mask, ct->regs.disable); | |
94 | *ct->mask_cache &= ~mask; | |
95 | irq_reg_writel(gc, mask, ct->regs.ack); | |
96 | irq_gc_unlock(gc); | |
97 | } | |
98 | ||
bd0b9ac4 | 99 | static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) |
7f646e92 FF |
100 | { |
101 | struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); | |
102 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
bd0b9ac4 | 103 | unsigned int irq; |
7f646e92 FF |
104 | u32 status; |
105 | ||
106 | chained_irq_enter(chip, desc); | |
107 | ||
8480ca47 DB |
108 | status = irq_reg_readl(b->gc, b->status_offset) & |
109 | ~(irq_reg_readl(b->gc, b->mask_offset)); | |
7f646e92 FF |
110 | |
111 | if (status == 0) { | |
05f12757 | 112 | raw_spin_lock(&desc->lock); |
bd0b9ac4 | 113 | handle_bad_irq(desc); |
05f12757 | 114 | raw_spin_unlock(&desc->lock); |
7f646e92 FF |
115 | goto out; |
116 | } | |
117 | ||
118 | do { | |
119 | irq = ffs(status) - 1; | |
7f646e92 | 120 | status &= ~(1 << irq); |
49aa6ef0 | 121 | generic_handle_irq(irq_linear_revmap(b->domain, irq)); |
7f646e92 FF |
122 | } while (status); |
123 | out: | |
124 | chained_irq_exit(chip, desc); | |
125 | } | |
126 | ||
127 | static void brcmstb_l2_intc_suspend(struct irq_data *d) | |
128 | { | |
129 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
8480ca47 | 130 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
7f646e92 | 131 | struct brcmstb_l2_intc_data *b = gc->private; |
33517881 | 132 | unsigned long flags; |
7f646e92 | 133 | |
33517881 | 134 | irq_gc_lock_irqsave(gc, flags); |
7f646e92 | 135 | /* Save the current mask */ |
8480ca47 | 136 | b->saved_mask = irq_reg_readl(gc, ct->regs.mask); |
7f646e92 FF |
137 | |
138 | if (b->can_wake) { | |
139 | /* Program the wakeup mask */ | |
8480ca47 DB |
140 | irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable); |
141 | irq_reg_writel(gc, gc->wake_active, ct->regs.enable); | |
7f646e92 | 142 | } |
33517881 | 143 | irq_gc_unlock_irqrestore(gc, flags); |
7f646e92 FF |
144 | } |
145 | ||
146 | static void brcmstb_l2_intc_resume(struct irq_data *d) | |
147 | { | |
148 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
8480ca47 | 149 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
7f646e92 | 150 | struct brcmstb_l2_intc_data *b = gc->private; |
33517881 | 151 | unsigned long flags; |
7f646e92 | 152 | |
33517881 | 153 | irq_gc_lock_irqsave(gc, flags); |
c0ca7262 | 154 | if (ct->chip.irq_ack) { |
8480ca47 DB |
155 | /* Clear unmasked non-wakeup interrupts */ |
156 | irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, | |
157 | ct->regs.ack); | |
158 | } | |
7f646e92 FF |
159 | |
160 | /* Restore the saved mask */ | |
8480ca47 DB |
161 | irq_reg_writel(gc, b->saved_mask, ct->regs.disable); |
162 | irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable); | |
33517881 | 163 | irq_gc_unlock_irqrestore(gc, flags); |
7f646e92 FF |
164 | } |
165 | ||
2ae9add9 | 166 | static int __init brcmstb_l2_intc_of_init(struct device_node *np, |
c0ca7262 DB |
167 | struct device_node *parent, |
168 | const struct brcmstb_intc_init_params | |
169 | *init_params) | |
7f646e92 FF |
170 | { |
171 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
172 | struct brcmstb_l2_intc_data *data; | |
7f646e92 FF |
173 | struct irq_chip_type *ct; |
174 | int ret; | |
1abbdbac | 175 | unsigned int flags; |
49aa6ef0 DB |
176 | int parent_irq; |
177 | void __iomem *base; | |
7f646e92 FF |
178 | |
179 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
180 | if (!data) | |
181 | return -ENOMEM; | |
182 | ||
49aa6ef0 DB |
183 | base = of_iomap(np, 0); |
184 | if (!base) { | |
7f646e92 FF |
185 | pr_err("failed to remap intc L2 registers\n"); |
186 | ret = -ENOMEM; | |
187 | goto out_free; | |
188 | } | |
189 | ||
190 | /* Disable all interrupts by default */ | |
c0ca7262 | 191 | writel(0xffffffff, base + init_params->cpu_mask_set); |
c9ae71e0 BN |
192 | |
193 | /* Wakeup interrupts may be retained from S5 (cold boot) */ | |
194 | data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); | |
c0ca7262 DB |
195 | if (!data->can_wake && (init_params->cpu_clear >= 0)) |
196 | writel(0xffffffff, base + init_params->cpu_clear); | |
7f646e92 | 197 | |
49aa6ef0 DB |
198 | parent_irq = irq_of_parse_and_map(np, 0); |
199 | if (!parent_irq) { | |
7f646e92 | 200 | pr_err("failed to find parent interrupt\n"); |
d99ba446 | 201 | ret = -EINVAL; |
7f646e92 FF |
202 | goto out_unmap; |
203 | } | |
204 | ||
205 | data->domain = irq_domain_add_linear(np, 32, | |
206 | &irq_generic_chip_ops, NULL); | |
207 | if (!data->domain) { | |
208 | ret = -ENOMEM; | |
209 | goto out_unmap; | |
210 | } | |
211 | ||
1abbdbac KC |
212 | /* MIPS chips strapped for BE will automagically configure the |
213 | * peripheral registers for CPU-native byte order. | |
214 | */ | |
215 | flags = 0; | |
216 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) | |
217 | flags |= IRQ_GC_BE_IO; | |
218 | ||
7f646e92 FF |
219 | /* Allocate a single Generic IRQ chip for this node */ |
220 | ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, | |
c0ca7262 | 221 | np->full_name, init_params->handler, clr, 0, flags); |
7f646e92 FF |
222 | if (ret) { |
223 | pr_err("failed to allocate generic irq chip\n"); | |
224 | goto out_free_domain; | |
225 | } | |
226 | ||
227 | /* Set the IRQ chaining logic */ | |
49aa6ef0 | 228 | irq_set_chained_handler_and_data(parent_irq, |
f286c173 | 229 | brcmstb_l2_intc_irq_handle, data); |
7f646e92 | 230 | |
49aa6ef0 DB |
231 | data->gc = irq_get_domain_generic_chip(data->domain, 0); |
232 | data->gc->reg_base = base; | |
233 | data->gc->private = data; | |
c0ca7262 DB |
234 | data->status_offset = init_params->cpu_status; |
235 | data->mask_offset = init_params->cpu_mask_status; | |
8480ca47 | 236 | |
49aa6ef0 | 237 | ct = data->gc->chip_types; |
7f646e92 | 238 | |
c0ca7262 DB |
239 | if (init_params->cpu_clear >= 0) { |
240 | ct->regs.ack = init_params->cpu_clear; | |
241 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
242 | ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack; | |
243 | } else { | |
244 | /* No Ack - but still slightly more efficient to define this */ | |
245 | ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; | |
246 | } | |
7f646e92 FF |
247 | |
248 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
c0ca7262 DB |
249 | ct->regs.disable = init_params->cpu_mask_set; |
250 | ct->regs.mask = init_params->cpu_mask_status; | |
7f646e92 FF |
251 | |
252 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
c0ca7262 | 253 | ct->regs.enable = init_params->cpu_mask_clear; |
7f646e92 FF |
254 | |
255 | ct->chip.irq_suspend = brcmstb_l2_intc_suspend; | |
256 | ct->chip.irq_resume = brcmstb_l2_intc_resume; | |
c017d211 | 257 | ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend; |
7f646e92 | 258 | |
c9ae71e0 | 259 | if (data->can_wake) { |
7f646e92 FF |
260 | /* This IRQ chip can wake the system, set all child interrupts |
261 | * in wake_enabled mask | |
262 | */ | |
49aa6ef0 | 263 | data->gc->wake_enabled = 0xffffffff; |
7f646e92 FF |
264 | ct->chip.irq_set_wake = irq_gc_set_wake; |
265 | } | |
266 | ||
082ce27f FF |
267 | pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq); |
268 | ||
7f646e92 FF |
269 | return 0; |
270 | ||
271 | out_free_domain: | |
272 | irq_domain_remove(data->domain); | |
273 | out_unmap: | |
49aa6ef0 | 274 | iounmap(base); |
7f646e92 FF |
275 | out_free: |
276 | kfree(data); | |
277 | return ret; | |
278 | } | |
c0ca7262 | 279 | |
dc3173c7 | 280 | static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np, |
c0ca7262 DB |
281 | struct device_node *parent) |
282 | { | |
283 | return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init); | |
284 | } | |
285 | IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init); | |
286 | ||
dc3173c7 | 287 | static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np, |
c0ca7262 DB |
288 | struct device_node *parent) |
289 | { | |
290 | return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init); | |
291 | } | |
292 | IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc", | |
293 | brcmstb_l2_lvl_intc_of_init); |