[linux-block.git] / drivers / irqchip / irq-brcmstb-l2.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
 *
 * Copyright (C) 2014-2017 Broadcom
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

struct brcmstb_intc_init_params {
	irq_flow_handler_t handler;
	int cpu_status;
	int cpu_clear;
	int cpu_mask_status;
	int cpu_mask_set;
	int cpu_mask_clear;
};

/* Register offsets in the L2 latched interrupt controller */
static const struct brcmstb_intc_init_params l2_edge_intc_init = {
	.handler		= handle_edge_irq,
	.cpu_status		= 0x00,
	.cpu_clear		= 0x08,
	.cpu_mask_status	= 0x0c,
	.cpu_mask_set		= 0x10,
	.cpu_mask_clear		= 0x14
};

/* Register offsets in the L2 level interrupt controller */
static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
	.handler		= handle_level_irq,
	.cpu_status		= 0x00,
	.cpu_clear		= -1, /* Register not present */
	.cpu_mask_status	= 0x04,
	.cpu_mask_set		= 0x08,
	.cpu_mask_clear		= 0x0C
};

/* L2 intc private data structure */
struct brcmstb_l2_intc_data {
	struct irq_domain *domain;
	struct irq_chip_generic *gc;
	int status_offset;
	int mask_offset;
	bool can_wake;
	u32 saved_mask; /* for suspend/resume */
};

/**
 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register and pending interrupt is acknowledged by setting a bit.
 *
 * Note: This function is generic and could easily be added to the
 * generic irqchip implementation if there ever becomes a will to do so.
 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
 *
 * e.g.: https://patchwork.kernel.org/patch/9831047/
 */
static void brcmstb_l2_mask_and_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
{
	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int irq;
	u32 status;

	chained_irq_enter(chip, desc);

	status = irq_reg_readl(b->gc, b->status_offset) &
		~(irq_reg_readl(b->gc, b->mask_offset));

	if (status == 0) {
		raw_spin_lock(&desc->lock);
		handle_bad_irq(desc);
		raw_spin_unlock(&desc->lock);
		goto out;
	}

	do {
		irq = ffs(status) - 1;
		status &= ~(1 << irq);
		generic_handle_domain_irq(b->domain, irq);
	} while (status);
out:
	chained_irq_exit(chip, desc);
}

static void brcmstb_l2_intc_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct brcmstb_l2_intc_data *b = gc->private;
	unsigned long flags;

	irq_gc_lock_irqsave(gc, flags);
	/* Save the current mask */
	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);

	if (b->can_wake) {
		/* Program the wakeup mask */
		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
	}
	irq_gc_unlock_irqrestore(gc, flags);
}

static void brcmstb_l2_intc_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct brcmstb_l2_intc_data *b = gc->private;
	unsigned long flags;

	irq_gc_lock_irqsave(gc, flags);
	if (ct->chip.irq_ack) {
		/* Clear unmasked non-wakeup interrupts */
		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
				ct->regs.ack);
	}

	/* Restore the saved mask */
	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
	irq_gc_unlock_irqrestore(gc, flags);
}

static int __init brcmstb_l2_intc_of_init(struct device_node *np,
					  struct device_node *parent,
					  const struct brcmstb_intc_init_params
					  *init_params)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int set = 0;
	struct brcmstb_l2_intc_data *data;
	struct irq_chip_type *ct;
	int ret;
	unsigned int flags;
	int parent_irq;
	void __iomem *base;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("failed to remap intc L2 registers\n");
		ret = -ENOMEM;
		goto out_free;
	}

	/* Disable all interrupts by default */
	writel(0xffffffff, base + init_params->cpu_mask_set);

	/* Wakeup interrupts may be retained from S5 (cold boot) */
	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
	if (!data->can_wake && (init_params->cpu_clear >= 0))
		writel(0xffffffff, base + init_params->cpu_clear);

	parent_irq = irq_of_parse_and_map(np, 0);
	if (!parent_irq) {
		pr_err("failed to find parent interrupt\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	data->domain = irq_domain_add_linear(np, 32,
				&irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = 0;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	if (init_params->handler == handle_level_irq)
		set |= IRQ_LEVEL;

	/* Allocate a single Generic IRQ chip for this node */
	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
			np->full_name, init_params->handler, clr, set, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	/* Set the IRQ chaining logic */
	irq_set_chained_handler_and_data(parent_irq,
					 brcmstb_l2_intc_irq_handle, data);

	data->gc = irq_get_domain_generic_chip(data->domain, 0);
	data->gc->reg_base = base;
	data->gc->private = data;
	data->status_offset = init_params->cpu_status;
	data->mask_offset = init_params->cpu_mask_status;

	ct = data->gc->chip_types;

	if (init_params->cpu_clear >= 0) {
		ct->regs.ack = init_params->cpu_clear;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
	} else {
		/* No Ack - but still slightly more efficient to define this */
		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	}

	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->regs.disable = init_params->cpu_mask_set;
	ct->regs.mask = init_params->cpu_mask_status;

	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->regs.enable = init_params->cpu_mask_clear;

	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
	ct->chip.irq_resume = brcmstb_l2_intc_resume;
	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;

	if (data->can_wake) {
		/* This IRQ chip can wake the system, set all child interrupts
		 * in wake_enabled mask
		 */
		data->gc->wake_enabled = 0xffffffff;
		ct->chip.irq_set_wake = irq_gc_set_wake;
		enable_irq_wake(parent_irq);
	}

	pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_unmap:
	iounmap(base);
out_free:
	kfree(data);
	return ret;
}

static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
	struct device_node *parent)
{
	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
}

static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
	struct device_node *parent)
{
	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
}

IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
7f646e92 FF	2	/*
	3	* Generic Broadcom Set Top Box Level 2 Interrupt controller driver
	4	*
49aa6ef0	5	* Copyright (C) 2014-2017 Broadcom
7f646e92 FF	6	*/
	7
	8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	9
	10	#include <linux/init.h>
	11	#include <linux/slab.h>
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
05f12757	14	#include <linux/spinlock.h>
7f646e92 FF	15	#include <linux/of.h>
	16	#include <linux/of_irq.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_platform.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/io.h>
	22	#include <linux/irqdomain.h>
	23	#include <linux/irqchip.h>
	24	#include <linux/irqchip/chained_irq.h>
	25
c0ca7262 DB	26	struct brcmstb_intc_init_params {
	27	irq_flow_handler_t handler;
	28	int cpu_status;
	29	int cpu_clear;
	30	int cpu_mask_status;
	31	int cpu_mask_set;
	32	int cpu_mask_clear;
	33	};
	34
	35	/* Register offsets in the L2 latched interrupt controller */
	36	static const struct brcmstb_intc_init_params l2_edge_intc_init = {
	37	.handler = handle_edge_irq,
	38	.cpu_status = 0x00,
	39	.cpu_clear = 0x08,
	40	.cpu_mask_status = 0x0c,
	41	.cpu_mask_set = 0x10,
	42	.cpu_mask_clear = 0x14
	43	};
	44
	45	/* Register offsets in the L2 level interrupt controller */
	46	static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
	47	.handler = handle_level_irq,
	48	.cpu_status = 0x00,
	49	.cpu_clear = -1, /* Register not present */
	50	.cpu_mask_status = 0x04,
	51	.cpu_mask_set = 0x08,
	52	.cpu_mask_clear = 0x0C
	53	};
7f646e92 FF	54
	55	/* L2 intc private data structure */
	56	struct brcmstb_l2_intc_data {
7f646e92	57	struct irq_domain *domain;
49aa6ef0	58	struct irq_chip_generic *gc;
8480ca47 DB	59	int status_offset;
8480ca47 DB	60	int mask_offset;
7f646e92 FF	61	bool can_wake;
	62	u32 saved_mask; /* for suspend/resume */
	63	};
	64
49aa6ef0 DB	65	/**
	66	* brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
	67	* @d: irq_data
	68	*
	69	* Chip has separate enable/disable registers instead of a single mask
	70	* register and pending interrupt is acknowledged by setting a bit.
	71	*
	72	* Note: This function is generic and could easily be added to the
	73	* generic irqchip implementation if there ever becomes a will to do so.
	74	* Perhaps with a name like irq_gc_mask_disable_and_ack_set().
	75	*
	76	* e.g.: https://patchwork.kernel.org/patch/9831047/
	77	*/
	78	static void brcmstb_l2_mask_and_ack(struct irq_data *d)
	79	{
	80	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	81	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	82	u32 mask = d->mask;
	83
	84	irq_gc_lock(gc);
	85	irq_reg_writel(gc, mask, ct->regs.disable);
	86	*ct->mask_cache &= ~mask;
	87	irq_reg_writel(gc, mask, ct->regs.ack);
	88	irq_gc_unlock(gc);
	89	}
	90
bd0b9ac4	91	static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
7f646e92 FF	92	{
	93	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
	94	struct irq_chip *chip = irq_desc_get_chip(desc);
bd0b9ac4	95	unsigned int irq;
7f646e92 FF	96	u32 status;
	97
	98	chained_irq_enter(chip, desc);
	99
8480ca47 DB	100	status = irq_reg_readl(b->gc, b->status_offset) &
8480ca47 DB	101	~(irq_reg_readl(b->gc, b->mask_offset));
7f646e92 FF	102
7f646e92 FF	103	if (status == 0) {
05f12757	104	raw_spin_lock(&desc->lock);
bd0b9ac4	105	handle_bad_irq(desc);
05f12757	106	raw_spin_unlock(&desc->lock);
7f646e92 FF	107	goto out;
	108	}
	109
	110	do {
	111	irq = ffs(status) - 1;
7f646e92	112	status &= ~(1 << irq);
046a6ee2	113	generic_handle_domain_irq(b->domain, irq);
7f646e92 FF	114	} while (status);
	115	out:
	116	chained_irq_exit(chip, desc);
	117	}
	118
	119	static void brcmstb_l2_intc_suspend(struct irq_data *d)
	120	{
	121	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
8480ca47	122	struct irq_chip_type *ct = irq_data_get_chip_type(d);
7f646e92	123	struct brcmstb_l2_intc_data *b = gc->private;
33517881	124	unsigned long flags;
7f646e92	125
33517881	126	irq_gc_lock_irqsave(gc, flags);
7f646e92	127	/* Save the current mask */
8480ca47	128	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
7f646e92 FF	129
	130	if (b->can_wake) {
	131	/* Program the wakeup mask */
8480ca47 DB	132	irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
8480ca47 DB	133	irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
7f646e92	134	}
33517881	135	irq_gc_unlock_irqrestore(gc, flags);
7f646e92 FF	136	}
	137
	138	static void brcmstb_l2_intc_resume(struct irq_data *d)
	139	{
	140	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
8480ca47	141	struct irq_chip_type *ct = irq_data_get_chip_type(d);
7f646e92	142	struct brcmstb_l2_intc_data *b = gc->private;
33517881	143	unsigned long flags;
7f646e92	144
33517881	145	irq_gc_lock_irqsave(gc, flags);
c0ca7262	146	if (ct->chip.irq_ack) {
8480ca47 DB	147	/* Clear unmasked non-wakeup interrupts */
	148	irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
	149	ct->regs.ack);
	150	}
7f646e92 FF	151
7f646e92 FF	152	/* Restore the saved mask */
8480ca47 DB	153	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
8480ca47 DB	154	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
33517881	155	irq_gc_unlock_irqrestore(gc, flags);
7f646e92 FF	156	}
7f646e92 FF	157
2ae9add9	158	static int __init brcmstb_l2_intc_of_init(struct device_node *np,
c0ca7262 DB	159	struct device_node *parent,
	160	const struct brcmstb_intc_init_params
	161	*init_params)
7f646e92 FF	162	{
7f646e92 FF	163	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
94debe03	164	unsigned int set = 0;
7f646e92	165	struct brcmstb_l2_intc_data *data;
7f646e92 FF	166	struct irq_chip_type *ct;
7f646e92 FF	167	int ret;
1abbdbac	168	unsigned int flags;
49aa6ef0 DB	169	int parent_irq;
49aa6ef0 DB	170	void __iomem *base;
7f646e92 FF	171
	172	data = kzalloc(sizeof(*data), GFP_KERNEL);
	173	if (!data)
	174	return -ENOMEM;
	175
49aa6ef0 DB	176	base = of_iomap(np, 0);
49aa6ef0 DB	177	if (!base) {
7f646e92 FF	178	pr_err("failed to remap intc L2 registers\n");
	179	ret = -ENOMEM;
	180	goto out_free;
	181	}
	182
	183	/* Disable all interrupts by default */
c0ca7262	184	writel(0xffffffff, base + init_params->cpu_mask_set);
c9ae71e0 BN	185
	186	/* Wakeup interrupts may be retained from S5 (cold boot) */
	187	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
c0ca7262 DB	188	if (!data->can_wake && (init_params->cpu_clear >= 0))
c0ca7262 DB	189	writel(0xffffffff, base + init_params->cpu_clear);
7f646e92	190
49aa6ef0 DB	191	parent_irq = irq_of_parse_and_map(np, 0);
49aa6ef0 DB	192	if (!parent_irq) {
7f646e92	193	pr_err("failed to find parent interrupt\n");
d99ba446	194	ret = -EINVAL;
7f646e92 FF	195	goto out_unmap;
	196	}
	197
	198	data->domain = irq_domain_add_linear(np, 32,
	199	&irq_generic_chip_ops, NULL);
	200	if (!data->domain) {
	201	ret = -ENOMEM;
	202	goto out_unmap;
	203	}
	204
1abbdbac KC	205	/* MIPS chips strapped for BE will automagically configure the
	206	* peripheral registers for CPU-native byte order.
	207	*/
	208	flags = 0;
	209	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	210	flags \|= IRQ_GC_BE_IO;
	211
94debe03 FF	212	if (init_params->handler == handle_level_irq)
	213	set \|= IRQ_LEVEL;
	214
7f646e92 FF	215	/* Allocate a single Generic IRQ chip for this node */
7f646e92 FF	216	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
94debe03	217	np->full_name, init_params->handler, clr, set, flags);
7f646e92 FF	218	if (ret) {
	219	pr_err("failed to allocate generic irq chip\n");
	220	goto out_free_domain;
	221	}
	222
	223	/* Set the IRQ chaining logic */
49aa6ef0	224	irq_set_chained_handler_and_data(parent_irq,
f286c173	225	brcmstb_l2_intc_irq_handle, data);
7f646e92	226
49aa6ef0 DB	227	data->gc = irq_get_domain_generic_chip(data->domain, 0);
	228	data->gc->reg_base = base;
	229	data->gc->private = data;
c0ca7262 DB	230	data->status_offset = init_params->cpu_status;
c0ca7262 DB	231	data->mask_offset = init_params->cpu_mask_status;
8480ca47	232
49aa6ef0	233	ct = data->gc->chip_types;
7f646e92	234
c0ca7262 DB	235	if (init_params->cpu_clear >= 0) {
	236	ct->regs.ack = init_params->cpu_clear;
	237	ct->chip.irq_ack = irq_gc_ack_set_bit;
	238	ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
	239	} else {
	240	/* No Ack - but still slightly more efficient to define this */
	241	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	242	}
7f646e92 FF	243
7f646e92 FF	244	ct->chip.irq_mask = irq_gc_mask_disable_reg;
c0ca7262 DB	245	ct->regs.disable = init_params->cpu_mask_set;
c0ca7262 DB	246	ct->regs.mask = init_params->cpu_mask_status;
7f646e92 FF	247
7f646e92 FF	248	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
c0ca7262	249	ct->regs.enable = init_params->cpu_mask_clear;
7f646e92 FF	250
	251	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
	252	ct->chip.irq_resume = brcmstb_l2_intc_resume;
c017d211	253	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
7f646e92	254
c9ae71e0	255	if (data->can_wake) {
7f646e92 FF	256	/* This IRQ chip can wake the system, set all child interrupts
	257	* in wake_enabled mask
	258	*/
49aa6ef0	259	data->gc->wake_enabled = 0xffffffff;
7f646e92	260	ct->chip.irq_set_wake = irq_gc_set_wake;
c8d8d6fc	261	enable_irq_wake(parent_irq);
7f646e92 FF	262	}
7f646e92 FF	263
082ce27f FF	264	pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
082ce27f FF	265
7f646e92 FF	266	return 0;
	267
	268	out_free_domain:
	269	irq_domain_remove(data->domain);
	270	out_unmap:
49aa6ef0	271	iounmap(base);
7f646e92 FF	272	out_free:
	273	kfree(data);
	274	return ret;
	275	}
c0ca7262	276
dc3173c7	277	static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
c0ca7262 DB	278	struct device_node *parent)
	279	{
	280	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
	281	}
c0ca7262	282
dc3173c7	283	static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
c0ca7262 DB	284	struct device_node *parent)
	285	{
	286	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
	287	}
51d9db5c FF	288
	289	IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
	290	IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
	291	IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
	292	IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
	293	IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
	294	IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
	295	MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
	296	MODULE_LICENSE("GPL v2");