[linux-2.6-block.git] / drivers / irqchip / irq-bcm7120-l2.c

/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define MAX_MAPPINGS	(MAX_WORDS * 2)
#define IRQS_PER_WORD	32

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *map_base[MAX_MAPPINGS];
	void __iomem *pair_base[MAX_WORDS];
	int en_offset[MAX_WORDS];
	int stat_offset[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	u32 irq_map_mask[MAX_WORDS];
	int num_parent_irqs;
	const __be32 *map_mask_prop;
};

static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
{
	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
					    gc->mask_cache;
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(b->domain,
					   base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct bcm7120_l2_intc_data *b = gc->private;

	irq_gc_lock(gc);
	if (b->can_wake)
		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
			       ct->regs.mask);
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	/* Restore the saved mask */
	irq_gc_lock(gc);
	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq)
{
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (!parent_irq) {
		pr_err("failed to map interrupt %d\n", irq);
		return -EINVAL;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 */
	for (idx = 0; idx < data->n_words; idx++) {
		if (data->map_mask_prop) {
			data->irq_map_mask[idx] |=
				be32_to_cpup(data->map_mask_prop +
					     irq * data->n_words + idx);
		} else {
			data->irq_map_mask[idx] = 0xffffffff;
		}
	}

	irq_set_chained_handler_and_data(parent_irq,
					 bcm7120_l2_intc_irq_handle, data);

	return 0;
}

static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	int ret;

	data->map_base[0] = of_iomap(dn, 0);
	if (!data->map_base[0]) {
		pr_err("unable to map registers\n");
		return -ENOMEM;
	}

	data->pair_base[0] = data->map_base[0];
	data->en_offset[0] = IRQEN;
	data->stat_offset[0] = IRQSTAT;
	data->n_words = 1;

	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	if (!data->map_mask_prop ||
	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		return -EINVAL;
	}

	return 0;
}

static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	unsigned int gc_idx;

	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
		unsigned int map_idx = gc_idx * 2;
		void __iomem *en = of_iomap(dn, map_idx + 0);
		void __iomem *stat = of_iomap(dn, map_idx + 1);
		void __iomem *base = min(en, stat);

		data->map_base[map_idx + 0] = en;
		data->map_base[map_idx + 1] = stat;

		if (!base)
			break;

		data->pair_base[gc_idx] = base;
		data->en_offset[gc_idx] = en - base;
		data->stat_offset[gc_idx] = stat - base;
	}

	if (!gc_idx) {
		pr_err("unable to map registers\n");
		return -EINVAL;
	}

	data->n_words = gc_idx;
	return 0;
}

int __init bcm7120_l2_intc_probe(struct device_node *dn,
				 struct device_node *parent,
				 int (*iomap_regs_fn)(struct device_node *,
					struct bcm7120_l2_intc_data *),
				 const char *intc_name)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret = 0;
	unsigned int idx, irq, flags;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->num_parent_irqs = of_irq_count(dn);
	if (data->num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	ret = iomap_regs_fn(dn, data);
	if (ret < 0)
		goto out_unmap;

	for (idx = 0; idx < data->n_words; idx++) {
		__raw_writel(data->irq_fwd_mask[idx],
			     data->pair_base[idx] +
			     data->en_offset[idx]);
	}

	for (irq = 0; irq < data->num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq);
		if (ret)
			goto out_unmap;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = IRQ_GC_INIT_MASK_CACHE;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		data->can_wake = true;

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
		gc->private = data;
		ct = gc->chip_types;

		gc->reg_base = data->pair_base[idx];
		ct->regs.mask = data->en_offset[idx];

		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
		ct->chip.irq_resume = bcm7120_l2_intc_resume;

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
			intc_name, data->map_base[0], data->num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_unmap:
	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
		if (data->map_base[idx])
			iounmap(data->map_base[idx]);
	}
	kfree(data);
	return ret;
}

int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
				     "BCM7120 L2");
}

int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
				     "BCM3380 L2");
}

IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
		bcm7120_l2_intc_probe_7120);

IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
		bcm7120_l2_intc_probe_3380);
Commit	Line	Data
a5042de2 FF	1	/*
	2	* Broadcom BCM7120 style Level 2 interrupt controller driver
	3	*
	4	* Copyright (C) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
c17261fa	16	#include <linux/kconfig.h>
7b7230e7	17	#include <linux/kernel.h>
a5042de2 FF	18	#include <linux/platform_device.h>
	19	#include <linux/of.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/io.h>
	26	#include <linux/irqdomain.h>
	27	#include <linux/reboot.h>
c76acf4d	28	#include <linux/bitops.h>
41a83e06	29	#include <linux/irqchip.h>
a5042de2 FF	30	#include <linux/irqchip/chained_irq.h>
a5042de2 FF	31
a5042de2 FF	32	/* Register offset in the L2 interrupt controller */
	33	#define IRQEN 0x00
	34	#define IRQSTAT 0x04
	35
c76acf4d	36	#define MAX_WORDS 4
ca40f1b2	37	#define MAX_MAPPINGS (MAX_WORDS * 2)
c76acf4d KC	38	#define IRQS_PER_WORD 32
c76acf4d KC	39
a5042de2	40	struct bcm7120_l2_intc_data {
c76acf4d	41	unsigned int n_words;
5b5468cf KC	42	void __iomem *map_base[MAX_MAPPINGS];
	43	void __iomem *pair_base[MAX_WORDS];
	44	int en_offset[MAX_WORDS];
	45	int stat_offset[MAX_WORDS];
a5042de2 FF	46	struct irq_domain *domain;
a5042de2 FF	47	bool can_wake;
c76acf4d KC	48	u32 irq_fwd_mask[MAX_WORDS];
c76acf4d KC	49	u32 irq_map_mask[MAX_WORDS];
ca40f1b2 KC	50	int num_parent_irqs;
ca40f1b2 KC	51	const __be32 *map_mask_prop;
a5042de2 FF	52	};
	53
	54	static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
	55	{
	56	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	57	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	58	unsigned int idx;
a5042de2 FF	59
	60	chained_irq_enter(chip, desc);
	61
c76acf4d KC	62	for (idx = 0; idx < b->n_words; idx++) {
	63	int base = idx * IRQS_PER_WORD;
	64	struct irq_chip_generic *gc =
	65	irq_get_domain_generic_chip(b->domain, base);
	66	unsigned long pending;
	67	int hwirq;
	68
	69	irq_gc_lock(gc);
5b5468cf KC	70	pending = irq_reg_readl(gc, b->stat_offset[idx]) &
5b5468cf KC	71	gc->mask_cache;
c76acf4d KC	72	irq_gc_unlock(gc);
	73
	74	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	75	generic_handle_irq(irq_find_mapping(b->domain,
	76	base + hwirq));
	77	}
a5042de2 FF	78	}
a5042de2 FF	79
a5042de2 FF	80	chained_irq_exit(chip, desc);
	81	}
	82
	83	static void bcm7120_l2_intc_suspend(struct irq_data *d)
	84	{
	85	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
5b5468cf	86	struct irq_chip_type *ct = irq_data_get_chip_type(d);
a5042de2	87	struct bcm7120_l2_intc_data *b = gc->private;
a5042de2 FF	88
a5042de2 FF	89	irq_gc_lock(gc);
c17261fa	90	if (b->can_wake)
5b5468cf KC	91	irq_reg_writel(gc, gc->mask_cache \| gc->wake_active,
5b5468cf KC	92	ct->regs.mask);
a5042de2 FF	93	irq_gc_unlock(gc);
	94	}
	95
	96	static void bcm7120_l2_intc_resume(struct irq_data *d)
	97	{
	98	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
5b5468cf	99	struct irq_chip_type *ct = irq_data_get_chip_type(d);
a5042de2 FF	100
	101	/* Restore the saved mask */
	102	irq_gc_lock(gc);
5b5468cf	103	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
a5042de2 FF	104	irq_gc_unlock(gc);
	105	}
	106
	107	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	108	struct bcm7120_l2_intc_data *data,
ca40f1b2	109	int irq)
a5042de2 FF	110	{
a5042de2 FF	111	int parent_irq;
c76acf4d	112	unsigned int idx;
a5042de2 FF	113
a5042de2 FF	114	parent_irq = irq_of_parse_and_map(dn, irq);
714710e1	115	if (!parent_irq) {
a5042de2	116	pr_err("failed to map interrupt %d\n", irq);
714710e1	117	return -EINVAL;
a5042de2 FF	118	}
a5042de2 FF	119
c76acf4d KC	120	/* For multiple parent IRQs with multiple words, this looks like:
	121	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	122	*/
7b7230e7 KC	123	for (idx = 0; idx < data->n_words; idx++) {
	124	if (data->map_mask_prop) {
	125	data->irq_map_mask[idx] \|=
	126	be32_to_cpup(data->map_mask_prop +
	127	irq * data->n_words + idx);
	128	} else {
	129	data->irq_map_mask[idx] = 0xffffffff;
	130	}
	131	}
a5042de2	132
99e32ab1 TG	133	irq_set_chained_handler_and_data(parent_irq,
99e32ab1 TG	134	bcm7120_l2_intc_irq_handle, data);
a5042de2 FF	135
	136	return 0;
	137	}
	138
ca40f1b2 KC	139	static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
	140	struct bcm7120_l2_intc_data *data)
	141	{
	142	int ret;
	143
	144	data->map_base[0] = of_iomap(dn, 0);
	145	if (!data->map_base[0]) {
	146	pr_err("unable to map registers\n");
	147	return -ENOMEM;
	148	}
	149
	150	data->pair_base[0] = data->map_base[0];
	151	data->en_offset[0] = IRQEN;
	152	data->stat_offset[0] = IRQSTAT;
	153	data->n_words = 1;
	154
	155	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	156	data->irq_fwd_mask, data->n_words);
	157	if (ret != 0 && ret != -EINVAL) {
	158	/* property exists but has the wrong number of words */
	159	pr_err("invalid brcm,int-fwd-mask property\n");
	160	return -EINVAL;
	161	}
	162
	163	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	164	if (!data->map_mask_prop \|\|
	165	(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
	166	pr_err("invalid brcm,int-map-mask property\n");
	167	return -EINVAL;
	168	}
	169
	170	return 0;
	171	}
	172
7b7230e7 KC	173	static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
	174	struct bcm7120_l2_intc_data *data)
	175	{
	176	unsigned int gc_idx;
	177
	178	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
	179	unsigned int map_idx = gc_idx * 2;
	180	void __iomem *en = of_iomap(dn, map_idx + 0);
	181	void __iomem *stat = of_iomap(dn, map_idx + 1);
	182	void __iomem *base = min(en, stat);
	183
	184	data->map_base[map_idx + 0] = en;
	185	data->map_base[map_idx + 1] = stat;
	186
	187	if (!base)
	188	break;
	189
	190	data->pair_base[gc_idx] = base;
	191	data->en_offset[gc_idx] = en - base;
	192	data->stat_offset[gc_idx] = stat - base;
	193	}
	194
	195	if (!gc_idx) {
	196	pr_err("unable to map registers\n");
	197	return -EINVAL;
	198	}
	199
	200	data->n_words = gc_idx;
	201	return 0;
	202	}
	203
ca40f1b2 KC	204	int __init bcm7120_l2_intc_probe(struct device_node *dn,
	205	struct device_node *parent,
	206	int (iomap_regs_fn)(struct device_node ,
	207	struct bcm7120_l2_intc_data *),
	208	const char *intc_name)
a5042de2 FF	209	{
	210	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	211	struct bcm7120_l2_intc_data *data;
	212	struct irq_chip_generic *gc;
	213	struct irq_chip_type *ct;
ca40f1b2	214	int ret = 0;
c17261fa	215	unsigned int idx, irq, flags;
a5042de2 FF	216
	217	data = kzalloc(sizeof(*data), GFP_KERNEL);
	218	if (!data)
	219	return -ENOMEM;
	220
ca40f1b2 KC	221	data->num_parent_irqs = of_irq_count(dn);
ca40f1b2 KC	222	if (data->num_parent_irqs <= 0) {
a5042de2 FF	223	pr_err("invalid number of parent interrupts\n");
	224	ret = -ENOMEM;
	225	goto out_unmap;
	226	}
	227
ca40f1b2 KC	228	ret = iomap_regs_fn(dn, data);
ca40f1b2 KC	229	if (ret < 0)
a5042de2	230	goto out_unmap;
ca40f1b2 KC	231
	232	for (idx = 0; idx < data->n_words; idx++) {
	233	__raw_writel(data->irq_fwd_mask[idx],
	234	data->pair_base[idx] +
	235	data->en_offset[idx]);
a5042de2 FF	236	}
a5042de2 FF	237
ca40f1b2 KC	238	for (irq = 0; irq < data->num_parent_irqs; irq++) {
ca40f1b2 KC	239	ret = bcm7120_l2_intc_init_one(dn, data, irq);
a5042de2 FF	240	if (ret)
	241	goto out_unmap;
	242	}
	243
c76acf4d KC	244	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	245	&irq_generic_chip_ops, NULL);
a5042de2 FF	246	if (!data->domain) {
	247	ret = -ENOMEM;
	248	goto out_unmap;
	249	}
	250
c17261fa KC	251	/* MIPS chips strapped for BE will automagically configure the
	252	* peripheral registers for CPU-native byte order.
	253	*/
	254	flags = IRQ_GC_INIT_MASK_CACHE;
	255	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	256	flags \|= IRQ_GC_BE_IO;
	257
c76acf4d	258	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
c17261fa	259	dn->full_name, handle_level_irq, clr, 0, flags);
a5042de2 FF	260	if (ret) {
	261	pr_err("failed to allocate generic irq chip\n");
	262	goto out_free_domain;
	263	}
	264
c76acf4d	265	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
a5042de2	266	data->can_wake = true;
c76acf4d KC	267
	268	for (idx = 0; idx < data->n_words; idx++) {
	269	irq = idx * IRQS_PER_WORD;
	270	gc = irq_get_domain_generic_chip(data->domain, irq);
	271
	272	gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
c76acf4d KC	273	gc->private = data;
	274	ct = gc->chip_types;
	275
5b5468cf KC	276	gc->reg_base = data->pair_base[idx];
	277	ct->regs.mask = data->en_offset[idx];
	278
c76acf4d KC	279	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	280	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	281	ct->chip.irq_ack = irq_gc_noop;
	282	ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
	283	ct->chip.irq_resume = bcm7120_l2_intc_resume;
	284
	285	if (data->can_wake) {
	286	/* This IRQ chip can wake the system, set all
	287	* relevant child interupts in wake_enabled mask
	288	*/
	289	gc->wake_enabled = 0xffffffff;
	290	gc->wake_enabled &= ~gc->unused;
	291	ct->chip.irq_set_wake = irq_gc_set_wake;
	292	}
a5042de2 FF	293	}
a5042de2 FF	294
ca40f1b2 KC	295	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
ca40f1b2 KC	296	intc_name, data->map_base[0], data->num_parent_irqs);
a5042de2 FF	297
	298	return 0;
	299
	300	out_free_domain:
	301	irq_domain_remove(data->domain);
	302	out_unmap:
5b5468cf KC	303	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
	304	if (data->map_base[idx])
	305	iounmap(data->map_base[idx]);
c76acf4d	306	}
a5042de2 FF	307	kfree(data);
	308	return ret;
	309	}
ca40f1b2 KC	310
	311	int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
	312	struct device_node *parent)
	313	{
	314	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
	315	"BCM7120 L2");
	316	}
	317
7b7230e7 KC	318	int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
	319	struct device_node *parent)
	320	{
	321	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
	322	"BCM3380 L2");
	323	}
	324
a4fcbb86	325	IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
ca40f1b2	326	bcm7120_l2_intc_probe_7120);
7b7230e7 KC	327
	328	IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
	329	bcm7120_l2_intc_probe_3380);