[linux-block.git] / drivers / irqchip / irq-bcm7120-l2.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define MAX_MAPPINGS	(MAX_WORDS * 2)
#define IRQS_PER_WORD	32

struct bcm7120_l1_intc_data {
	struct bcm7120_l2_intc_data *b;
	u32 irq_map_mask[MAX_WORDS];
};

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *map_base[MAX_MAPPINGS];
	void __iomem *pair_base[MAX_WORDS];
	int en_offset[MAX_WORDS];
	int stat_offset[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	struct bcm7120_l1_intc_data *l1_data;
	int num_parent_irqs;
	const __be32 *map_mask_prop;
};

static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
{
	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
	struct bcm7120_l2_intc_data *b = data->b;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
					    gc->mask_cache &
					    data->irq_map_mask[idx];
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
			generic_handle_domain_irq(b->domain, base + hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
{
	struct bcm7120_l2_intc_data *b = gc->private;
	struct irq_chip_type *ct = gc->chip_types;

	irq_gc_lock(gc);
	if (b->can_wake)
		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
			       ct->regs.mask);
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
{
	struct irq_chip_type *ct = gc->chip_types;

	/* Restore the saved mask */
	irq_gc_lock(gc);
	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq, u32 *valid_mask)
{
	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (!parent_irq) {
		pr_err("failed to map interrupt %d\n", irq);
		return -EINVAL;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 *
	 * We need to associate a given parent interrupt with its corresponding
	 * map_mask in order to mask the status register with it because we
	 * have the same handler being called for multiple parent interrupts.
	 *
	 * This is typically something needed on BCM7xxx (STB chips).
	 */
	for (idx = 0; idx < data->n_words; idx++) {
		if (data->map_mask_prop) {
			l1_data->irq_map_mask[idx] |=
				be32_to_cpup(data->map_mask_prop +
					     irq * data->n_words + idx);
		} else {
			l1_data->irq_map_mask[idx] = 0xffffffff;
		}
		valid_mask[idx] |= l1_data->irq_map_mask[idx];
	}

	l1_data->b = data;

	irq_set_chained_handler_and_data(parent_irq,
					 bcm7120_l2_intc_irq_handle, l1_data);
	if (data->can_wake)
		enable_irq_wake(parent_irq);

	return 0;
}

static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	int ret;

	data->map_base[0] = of_iomap(dn, 0);
	if (!data->map_base[0]) {
		pr_err("unable to map registers\n");
		return -ENOMEM;
	}

	data->pair_base[0] = data->map_base[0];
	data->en_offset[0] = IRQEN;
	data->stat_offset[0] = IRQSTAT;
	data->n_words = 1;

	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	if (!data->map_mask_prop ||
	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		return -EINVAL;
	}

	return 0;
}

static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	unsigned int gc_idx;

	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
		unsigned int map_idx = gc_idx * 2;
		void __iomem *en = of_iomap(dn, map_idx + 0);
		void __iomem *stat = of_iomap(dn, map_idx + 1);
		void __iomem *base = min(en, stat);

		data->map_base[map_idx + 0] = en;
		data->map_base[map_idx + 1] = stat;

		if (!base)
			break;

		data->pair_base[gc_idx] = base;
		data->en_offset[gc_idx] = en - base;
		data->stat_offset[gc_idx] = stat - base;
	}

	if (!gc_idx) {
		pr_err("unable to map registers\n");
		return -EINVAL;
	}

	data->n_words = gc_idx;
	return 0;
}

static int __init bcm7120_l2_intc_probe(struct device_node *dn,
				 struct device_node *parent,
				 int (*iomap_regs_fn)(struct device_node *,
					struct bcm7120_l2_intc_data *),
				 const char *intc_name)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct platform_device *pdev;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret = 0;
	unsigned int idx, irq, flags;
	u32 valid_mask[MAX_WORDS] = { };

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	pdev = of_find_device_by_node(dn);
	if (!pdev) {
		ret = -ENODEV;
		goto out_free_data;
	}

	data->num_parent_irqs = platform_irq_count(pdev);
	put_device(&pdev->dev);
	if (data->num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
				GFP_KERNEL);
	if (!data->l1_data) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	ret = iomap_regs_fn(dn, data);
	if (ret < 0)
		goto out_free_l1_data;

	data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");

	for (irq = 0; irq < data->num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
		if (ret)
			goto out_free_l1_data;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = IRQ_GC_INIT_MASK_CACHE;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~valid_mask[idx];
		gc->private = data;
		ct = gc->chip_types;

		gc->reg_base = data->pair_base[idx];
		ct->regs.mask = data->en_offset[idx];

		/* gc->reg_base is defined and so is gc->writel */
		irq_reg_writel(gc, data->irq_fwd_mask[idx],
			       data->en_offset[idx]);

		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		gc->suspend = bcm7120_l2_intc_suspend;
		gc->resume = bcm7120_l2_intc_resume;

		/*
		 * Initialize mask-cache, in case we need it for
		 * saving/restoring fwd mask even w/o any child interrupts
		 * installed
		 */
		gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interrupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
		intc_name, dn, data->num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_free_l1_data:
	kfree(data->l1_data);
out_unmap:
	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
		if (data->map_base[idx])
			iounmap(data->map_base[idx]);
	}
out_free_data:
	kfree(data);
	return ret;
}

static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
					     struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
				     "BCM7120 L2");
}

static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
					     struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
				     "BCM3380 L2");
}

IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2)
IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120)
IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380)
IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2)
MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
a5042de2 FF	2	/*
	3	* Broadcom BCM7120 style Level 2 interrupt controller driver
	4	*
	5	* Copyright (C) 2014 Broadcom Corporation
a5042de2 FF	6	*/
	7
	8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	9
	10	#include <linux/init.h>
	11	#include <linux/slab.h>
	12	#include <linux/module.h>
7b7230e7	13	#include <linux/kernel.h>
a5042de2 FF	14	#include <linux/platform_device.h>
	15	#include <linux/of.h>
	16	#include <linux/of_irq.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_platform.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/io.h>
	22	#include <linux/irqdomain.h>
	23	#include <linux/reboot.h>
c76acf4d	24	#include <linux/bitops.h>
41a83e06	25	#include <linux/irqchip.h>
a5042de2 FF	26	#include <linux/irqchip/chained_irq.h>
a5042de2 FF	27
a5042de2 FF	28	/* Register offset in the L2 interrupt controller */
	29	#define IRQEN 0x00
	30	#define IRQSTAT 0x04
	31
c76acf4d	32	#define MAX_WORDS 4
ca40f1b2	33	#define MAX_MAPPINGS (MAX_WORDS * 2)
c76acf4d KC	34	#define IRQS_PER_WORD 32
c76acf4d KC	35
0aef3997 FF	36	struct bcm7120_l1_intc_data {
	37	struct bcm7120_l2_intc_data *b;
	38	u32 irq_map_mask[MAX_WORDS];
	39	};
	40
a5042de2	41	struct bcm7120_l2_intc_data {
c76acf4d	42	unsigned int n_words;
5b5468cf KC	43	void __iomem *map_base[MAX_MAPPINGS];
	44	void __iomem *pair_base[MAX_WORDS];
	45	int en_offset[MAX_WORDS];
	46	int stat_offset[MAX_WORDS];
a5042de2 FF	47	struct irq_domain *domain;
a5042de2 FF	48	bool can_wake;
c76acf4d	49	u32 irq_fwd_mask[MAX_WORDS];
0aef3997	50	struct bcm7120_l1_intc_data *l1_data;
ca40f1b2 KC	51	int num_parent_irqs;
ca40f1b2 KC	52	const __be32 *map_mask_prop;
a5042de2 FF	53	};
a5042de2 FF	54
bd0b9ac4	55	static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
a5042de2	56	{
0aef3997 FF	57	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
0aef3997 FF	58	struct bcm7120_l2_intc_data *b = data->b;
a5042de2	59	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	60	unsigned int idx;
a5042de2 FF	61
	62	chained_irq_enter(chip, desc);
	63
c76acf4d KC	64	for (idx = 0; idx < b->n_words; idx++) {
	65	int base = idx * IRQS_PER_WORD;
	66	struct irq_chip_generic *gc =
	67	irq_get_domain_generic_chip(b->domain, base);
	68	unsigned long pending;
	69	int hwirq;
	70
	71	irq_gc_lock(gc);
5b5468cf	72	pending = irq_reg_readl(gc, b->stat_offset[idx]) &
0aef3997 FF	73	gc->mask_cache &
0aef3997 FF	74	data->irq_map_mask[idx];
c76acf4d KC	75	irq_gc_unlock(gc);
c76acf4d KC	76
046a6ee2 MZ	77	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
046a6ee2 MZ	78	generic_handle_domain_irq(b->domain, base + hwirq);
a5042de2 FF	79	}
a5042de2 FF	80
a5042de2 FF	81	chained_irq_exit(chip, desc);
	82	}
	83
fd537766	84	static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
a5042de2	85	{
a5042de2	86	struct bcm7120_l2_intc_data *b = gc->private;
fd537766	87	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	88
a5042de2 FF	89	irq_gc_lock(gc);
c17261fa	90	if (b->can_wake)
5b5468cf KC	91	irq_reg_writel(gc, gc->mask_cache \| gc->wake_active,
5b5468cf KC	92	ct->regs.mask);
a5042de2 FF	93	irq_gc_unlock(gc);
	94	}
	95
fd537766	96	static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
a5042de2	97	{
fd537766	98	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	99
	100	/* Restore the saved mask */
	101	irq_gc_lock(gc);
5b5468cf	102	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
a5042de2 FF	103	irq_gc_unlock(gc);
	104	}
	105
	106	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	107	struct bcm7120_l2_intc_data *data,
0aef3997	108	int irq, u32 *valid_mask)
a5042de2	109	{
0aef3997	110	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
a5042de2	111	int parent_irq;
c76acf4d	112	unsigned int idx;
a5042de2 FF	113
a5042de2 FF	114	parent_irq = irq_of_parse_and_map(dn, irq);
714710e1	115	if (!parent_irq) {
a5042de2	116	pr_err("failed to map interrupt %d\n", irq);
714710e1	117	return -EINVAL;
a5042de2 FF	118	}
a5042de2 FF	119
c76acf4d KC	120	/* For multiple parent IRQs with multiple words, this looks like:
c76acf4d KC	121	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
0aef3997 FF	122	*
	123	* We need to associate a given parent interrupt with its corresponding
	124	* map_mask in order to mask the status register with it because we
	125	* have the same handler being called for multiple parent interrupts.
	126	*
	127	* This is typically something needed on BCM7xxx (STB chips).
c76acf4d	128	*/
7b7230e7 KC	129	for (idx = 0; idx < data->n_words; idx++) {
7b7230e7 KC	130	if (data->map_mask_prop) {
0aef3997	131	l1_data->irq_map_mask[idx] \|=
7b7230e7 KC	132	be32_to_cpup(data->map_mask_prop +
	133	irq * data->n_words + idx);
	134	} else {
0aef3997	135	l1_data->irq_map_mask[idx] = 0xffffffff;
7b7230e7	136	}
0aef3997	137	valid_mask[idx] \|= l1_data->irq_map_mask[idx];
7b7230e7	138	}
a5042de2	139
0aef3997	140	l1_data->b = data;
a5042de2	141
0aef3997 FF	142	irq_set_chained_handler_and_data(parent_irq,
0aef3997 FF	143	bcm7120_l2_intc_irq_handle, l1_data);
f4ccb745 JC	144	if (data->can_wake)
	145	enable_irq_wake(parent_irq);
	146
a5042de2 FF	147	return 0;
	148	}
	149
ca40f1b2 KC	150	static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
	151	struct bcm7120_l2_intc_data *data)
	152	{
	153	int ret;
	154
	155	data->map_base[0] = of_iomap(dn, 0);
	156	if (!data->map_base[0]) {
	157	pr_err("unable to map registers\n");
	158	return -ENOMEM;
	159	}
	160
	161	data->pair_base[0] = data->map_base[0];
	162	data->en_offset[0] = IRQEN;
	163	data->stat_offset[0] = IRQSTAT;
	164	data->n_words = 1;
	165
	166	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	167	data->irq_fwd_mask, data->n_words);
	168	if (ret != 0 && ret != -EINVAL) {
	169	/* property exists but has the wrong number of words */
	170	pr_err("invalid brcm,int-fwd-mask property\n");
	171	return -EINVAL;
	172	}
	173
	174	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	175	if (!data->map_mask_prop \|\|
	176	(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
	177	pr_err("invalid brcm,int-map-mask property\n");
	178	return -EINVAL;
	179	}
	180
	181	return 0;
	182	}
	183
7b7230e7 KC	184	static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
	185	struct bcm7120_l2_intc_data *data)
	186	{
	187	unsigned int gc_idx;
	188
	189	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
	190	unsigned int map_idx = gc_idx * 2;
	191	void __iomem *en = of_iomap(dn, map_idx + 0);
	192	void __iomem *stat = of_iomap(dn, map_idx + 1);
	193	void __iomem *base = min(en, stat);
	194
	195	data->map_base[map_idx + 0] = en;
	196	data->map_base[map_idx + 1] = stat;
	197
	198	if (!base)
	199	break;
	200
	201	data->pair_base[gc_idx] = base;
	202	data->en_offset[gc_idx] = en - base;
	203	data->stat_offset[gc_idx] = stat - base;
	204	}
	205
	206	if (!gc_idx) {
	207	pr_err("unable to map registers\n");
	208	return -EINVAL;
	209	}
	210
	211	data->n_words = gc_idx;
	212	return 0;
	213	}
	214
dde7e6d1	215	static int __init bcm7120_l2_intc_probe(struct device_node *dn,
ca40f1b2 KC	216	struct device_node *parent,
	217	int (iomap_regs_fn)(struct device_node ,
	218	struct bcm7120_l2_intc_data *),
	219	const char *intc_name)
a5042de2 FF	220	{
	221	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	222	struct bcm7120_l2_intc_data *data;
3ac268d5	223	struct platform_device *pdev;
a5042de2 FF	224	struct irq_chip_generic *gc;
a5042de2 FF	225	struct irq_chip_type *ct;
ca40f1b2	226	int ret = 0;
c17261fa	227	unsigned int idx, irq, flags;
0aef3997	228	u32 valid_mask[MAX_WORDS] = { };
a5042de2 FF	229
	230	data = kzalloc(sizeof(*data), GFP_KERNEL);
	231	if (!data)
	232	return -ENOMEM;
	233
3ac268d5 FF	234	pdev = of_find_device_by_node(dn);
	235	if (!pdev) {
	236	ret = -ENODEV;
	237	goto out_free_data;
	238	}
	239
	240	data->num_parent_irqs = platform_irq_count(pdev);
c3fbab77	241	put_device(&pdev->dev);
ca40f1b2	242	if (data->num_parent_irqs <= 0) {
a5042de2 FF	243	pr_err("invalid number of parent interrupts\n");
	244	ret = -ENOMEM;
	245	goto out_unmap;
	246	}
	247
0aef3997 FF	248	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
	249	GFP_KERNEL);
	250	if (!data->l1_data) {
	251	ret = -ENOMEM;
	252	goto out_free_l1_data;
	253	}
	254
ca40f1b2 KC	255	ret = iomap_regs_fn(dn, data);
ca40f1b2 KC	256	if (ret < 0)
0aef3997	257	goto out_free_l1_data;
ca40f1b2	258
f4ccb745 JC	259	data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
f4ccb745 JC	260
ca40f1b2	261	for (irq = 0; irq < data->num_parent_irqs; irq++) {
0aef3997	262	ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
a5042de2	263	if (ret)
0aef3997	264	goto out_free_l1_data;
a5042de2 FF	265	}
a5042de2 FF	266
c76acf4d KC	267	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	268	&irq_generic_chip_ops, NULL);
a5042de2 FF	269	if (!data->domain) {
a5042de2 FF	270	ret = -ENOMEM;
0aef3997	271	goto out_free_l1_data;
a5042de2 FF	272	}
a5042de2 FF	273
c17261fa KC	274	/* MIPS chips strapped for BE will automagically configure the
	275	* peripheral registers for CPU-native byte order.
	276	*/
	277	flags = IRQ_GC_INIT_MASK_CACHE;
	278	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	279	flags \|= IRQ_GC_BE_IO;
	280
c76acf4d	281	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
c17261fa	282	dn->full_name, handle_level_irq, clr, 0, flags);
a5042de2 FF	283	if (ret) {
	284	pr_err("failed to allocate generic irq chip\n");
	285	goto out_free_domain;
	286	}
	287
c76acf4d KC	288	for (idx = 0; idx < data->n_words; idx++) {
	289	irq = idx * IRQS_PER_WORD;
	290	gc = irq_get_domain_generic_chip(data->domain, irq);
	291
0aef3997	292	gc->unused = 0xffffffff & ~valid_mask[idx];
c76acf4d KC	293	gc->private = data;
	294	ct = gc->chip_types;
	295
5b5468cf KC	296	gc->reg_base = data->pair_base[idx];
	297	ct->regs.mask = data->en_offset[idx];
	298
b304605f FF	299	/* gc->reg_base is defined and so is gc->writel */
	300	irq_reg_writel(gc, data->irq_fwd_mask[idx],
	301	data->en_offset[idx]);
	302
c76acf4d KC	303	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	304	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	305	ct->chip.irq_ack = irq_gc_noop;
fd537766 BN	306	gc->suspend = bcm7120_l2_intc_suspend;
	307	gc->resume = bcm7120_l2_intc_resume;
	308
	309	/*
	310	* Initialize mask-cache, in case we need it for
	311	* saving/restoring fwd mask even w/o any child interrupts
	312	* installed
	313	*/
	314	gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
c76acf4d KC	315
	316	if (data->can_wake) {
	317	/* This IRQ chip can wake the system, set all
a359f757	318	* relevant child interrupts in wake_enabled mask
c76acf4d KC	319	*/
	320	gc->wake_enabled = 0xffffffff;
	321	gc->wake_enabled &= ~gc->unused;
	322	ct->chip.irq_set_wake = irq_gc_set_wake;
	323	}
a5042de2 FF	324	}
a5042de2 FF	325
082ce27f FF	326	pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
	327	intc_name, dn, data->num_parent_irqs);
	328
a5042de2 FF	329	return 0;
	330
	331	out_free_domain:
	332	irq_domain_remove(data->domain);
0aef3997 FF	333	out_free_l1_data:
0aef3997 FF	334	kfree(data->l1_data);
a5042de2	335	out_unmap:
5b5468cf KC	336	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
	337	if (data->map_base[idx])
	338	iounmap(data->map_base[idx]);
c76acf4d	339	}
3ac268d5	340	out_free_data:
a5042de2 FF	341	kfree(data);
	342	return ret;
	343	}
ca40f1b2	344
dde7e6d1 BD	345	static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
dde7e6d1 BD	346	struct device_node *parent)
ca40f1b2 KC	347	{
	348	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
	349	"BCM7120 L2");
	350	}
	351
dde7e6d1 BD	352	static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
dde7e6d1 BD	353	struct device_node *parent)
7b7230e7 KC	354	{
	355	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
	356	"BCM3380 L2");
	357	}
	358
3ac268d5 FF	359	IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2)
	360	IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120)
	361	IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380)
	362	IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2)
	363	MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver");
	364	MODULE_LICENSE("GPL v2");