[linux-2.6-block.git] / drivers / irqchip / irq-bcm7120-l2.c

/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define MAX_MAPPINGS	(MAX_WORDS * 2)
#define IRQS_PER_WORD	32

struct bcm7120_l1_intc_data {
	struct bcm7120_l2_intc_data *b;
	u32 irq_map_mask[MAX_WORDS];
};

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *map_base[MAX_MAPPINGS];
	void __iomem *pair_base[MAX_WORDS];
	int en_offset[MAX_WORDS];
	int stat_offset[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	struct bcm7120_l1_intc_data *l1_data;
	int num_parent_irqs;
	const __be32 *map_mask_prop;
};

static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
{
	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
	struct bcm7120_l2_intc_data *b = data->b;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
					    gc->mask_cache &
					    data->irq_map_mask[idx];
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(b->domain,
					   base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
{
	struct bcm7120_l2_intc_data *b = gc->private;
	struct irq_chip_type *ct = gc->chip_types;

	irq_gc_lock(gc);
	if (b->can_wake)
		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
			       ct->regs.mask);
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
{
	struct irq_chip_type *ct = gc->chip_types;

	/* Restore the saved mask */
	irq_gc_lock(gc);
	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq, u32 *valid_mask)
{
	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (!parent_irq) {
		pr_err("failed to map interrupt %d\n", irq);
		return -EINVAL;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 *
	 * We need to associate a given parent interrupt with its corresponding
	 * map_mask in order to mask the status register with it because we
	 * have the same handler being called for multiple parent interrupts.
	 *
	 * This is typically something needed on BCM7xxx (STB chips).
	 */
	for (idx = 0; idx < data->n_words; idx++) {
		if (data->map_mask_prop) {
			l1_data->irq_map_mask[idx] |=
				be32_to_cpup(data->map_mask_prop +
					     irq * data->n_words + idx);
		} else {
			l1_data->irq_map_mask[idx] = 0xffffffff;
		}
		valid_mask[idx] |= l1_data->irq_map_mask[idx];
	}

	l1_data->b = data;

	irq_set_chained_handler_and_data(parent_irq,
					 bcm7120_l2_intc_irq_handle, l1_data);
	return 0;
}

static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	int ret;

	data->map_base[0] = of_iomap(dn, 0);
	if (!data->map_base[0]) {
		pr_err("unable to map registers\n");
		return -ENOMEM;
	}

	data->pair_base[0] = data->map_base[0];
	data->en_offset[0] = IRQEN;
	data->stat_offset[0] = IRQSTAT;
	data->n_words = 1;

	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	if (!data->map_mask_prop ||
	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		return -EINVAL;
	}

	return 0;
}

static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	unsigned int gc_idx;

	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
		unsigned int map_idx = gc_idx * 2;
		void __iomem *en = of_iomap(dn, map_idx + 0);
		void __iomem *stat = of_iomap(dn, map_idx + 1);
		void __iomem *base = min(en, stat);

		data->map_base[map_idx + 0] = en;
		data->map_base[map_idx + 1] = stat;

		if (!base)
			break;

		data->pair_base[gc_idx] = base;
		data->en_offset[gc_idx] = en - base;
		data->stat_offset[gc_idx] = stat - base;
	}

	if (!gc_idx) {
		pr_err("unable to map registers\n");
		return -EINVAL;
	}

	data->n_words = gc_idx;
	return 0;
}

int __init bcm7120_l2_intc_probe(struct device_node *dn,
				 struct device_node *parent,
				 int (*iomap_regs_fn)(struct device_node *,
					struct bcm7120_l2_intc_data *),
				 const char *intc_name)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret = 0;
	unsigned int idx, irq, flags;
	u32 valid_mask[MAX_WORDS] = { };

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->num_parent_irqs = of_irq_count(dn);
	if (data->num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
				GFP_KERNEL);
	if (!data->l1_data) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	ret = iomap_regs_fn(dn, data);
	if (ret < 0)
		goto out_free_l1_data;

	for (idx = 0; idx < data->n_words; idx++) {
		__raw_writel(data->irq_fwd_mask[idx],
			     data->pair_base[idx] +
			     data->en_offset[idx]);
	}

	for (irq = 0; irq < data->num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
		if (ret)
			goto out_free_l1_data;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = IRQ_GC_INIT_MASK_CACHE;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		data->can_wake = true;

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~valid_mask[idx];
		gc->private = data;
		ct = gc->chip_types;

		gc->reg_base = data->pair_base[idx];
		ct->regs.mask = data->en_offset[idx];

		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		gc->suspend = bcm7120_l2_intc_suspend;
		gc->resume = bcm7120_l2_intc_resume;

		/*
		 * Initialize mask-cache, in case we need it for
		 * saving/restoring fwd mask even w/o any child interrupts
		 * installed
		 */
		gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
			intc_name, data->map_base[0], data->num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_free_l1_data:
	kfree(data->l1_data);
out_unmap:
	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
		if (data->map_base[idx])
			iounmap(data->map_base[idx]);
	}
	kfree(data);
	return ret;
}

int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
				     "BCM7120 L2");
}

int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
				     "BCM3380 L2");
}

IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
		bcm7120_l2_intc_probe_7120);

IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
		bcm7120_l2_intc_probe_3380);
Commit	Line	Data
a5042de2 FF	1	/*
	2	* Broadcom BCM7120 style Level 2 interrupt controller driver
	3	*
	4	* Copyright (C) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
c17261fa	16	#include <linux/kconfig.h>
7b7230e7	17	#include <linux/kernel.h>
a5042de2 FF	18	#include <linux/platform_device.h>
	19	#include <linux/of.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/io.h>
	26	#include <linux/irqdomain.h>
	27	#include <linux/reboot.h>
c76acf4d	28	#include <linux/bitops.h>
41a83e06	29	#include <linux/irqchip.h>
a5042de2 FF	30	#include <linux/irqchip/chained_irq.h>
a5042de2 FF	31
a5042de2 FF	32	/* Register offset in the L2 interrupt controller */
	33	#define IRQEN 0x00
	34	#define IRQSTAT 0x04
	35
c76acf4d	36	#define MAX_WORDS 4
ca40f1b2	37	#define MAX_MAPPINGS (MAX_WORDS * 2)
c76acf4d KC	38	#define IRQS_PER_WORD 32
c76acf4d KC	39
0aef3997 FF	40	struct bcm7120_l1_intc_data {
	41	struct bcm7120_l2_intc_data *b;
	42	u32 irq_map_mask[MAX_WORDS];
	43	};
	44
a5042de2	45	struct bcm7120_l2_intc_data {
c76acf4d	46	unsigned int n_words;
5b5468cf KC	47	void __iomem *map_base[MAX_MAPPINGS];
	48	void __iomem *pair_base[MAX_WORDS];
	49	int en_offset[MAX_WORDS];
	50	int stat_offset[MAX_WORDS];
a5042de2 FF	51	struct irq_domain *domain;
a5042de2 FF	52	bool can_wake;
c76acf4d	53	u32 irq_fwd_mask[MAX_WORDS];
0aef3997	54	struct bcm7120_l1_intc_data *l1_data;
ca40f1b2 KC	55	int num_parent_irqs;
ca40f1b2 KC	56	const __be32 *map_mask_prop;
a5042de2 FF	57	};
a5042de2 FF	58
bd0b9ac4	59	static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
a5042de2	60	{
0aef3997 FF	61	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
0aef3997 FF	62	struct bcm7120_l2_intc_data *b = data->b;
a5042de2	63	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	64	unsigned int idx;
a5042de2 FF	65
	66	chained_irq_enter(chip, desc);
	67
c76acf4d KC	68	for (idx = 0; idx < b->n_words; idx++) {
	69	int base = idx * IRQS_PER_WORD;
	70	struct irq_chip_generic *gc =
	71	irq_get_domain_generic_chip(b->domain, base);
	72	unsigned long pending;
	73	int hwirq;
	74
	75	irq_gc_lock(gc);
5b5468cf	76	pending = irq_reg_readl(gc, b->stat_offset[idx]) &
0aef3997 FF	77	gc->mask_cache &
0aef3997 FF	78	data->irq_map_mask[idx];
c76acf4d KC	79	irq_gc_unlock(gc);
	80
	81	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	82	generic_handle_irq(irq_find_mapping(b->domain,
	83	base + hwirq));
	84	}
a5042de2 FF	85	}
a5042de2 FF	86
a5042de2 FF	87	chained_irq_exit(chip, desc);
	88	}
	89
fd537766	90	static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
a5042de2	91	{
a5042de2	92	struct bcm7120_l2_intc_data *b = gc->private;
fd537766	93	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	94
a5042de2 FF	95	irq_gc_lock(gc);
c17261fa	96	if (b->can_wake)
5b5468cf KC	97	irq_reg_writel(gc, gc->mask_cache \| gc->wake_active,
5b5468cf KC	98	ct->regs.mask);
a5042de2 FF	99	irq_gc_unlock(gc);
	100	}
	101
fd537766	102	static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
a5042de2	103	{
fd537766	104	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	105
	106	/* Restore the saved mask */
	107	irq_gc_lock(gc);
5b5468cf	108	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
a5042de2 FF	109	irq_gc_unlock(gc);
	110	}
	111
	112	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	113	struct bcm7120_l2_intc_data *data,
0aef3997	114	int irq, u32 *valid_mask)
a5042de2	115	{
0aef3997	116	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
a5042de2	117	int parent_irq;
c76acf4d	118	unsigned int idx;
a5042de2 FF	119
a5042de2 FF	120	parent_irq = irq_of_parse_and_map(dn, irq);
714710e1	121	if (!parent_irq) {
a5042de2	122	pr_err("failed to map interrupt %d\n", irq);
714710e1	123	return -EINVAL;
a5042de2 FF	124	}
a5042de2 FF	125
c76acf4d KC	126	/* For multiple parent IRQs with multiple words, this looks like:
c76acf4d KC	127	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
0aef3997 FF	128	*
	129	* We need to associate a given parent interrupt with its corresponding
	130	* map_mask in order to mask the status register with it because we
	131	* have the same handler being called for multiple parent interrupts.
	132	*
	133	* This is typically something needed on BCM7xxx (STB chips).
c76acf4d	134	*/
7b7230e7 KC	135	for (idx = 0; idx < data->n_words; idx++) {
7b7230e7 KC	136	if (data->map_mask_prop) {
0aef3997	137	l1_data->irq_map_mask[idx] \|=
7b7230e7 KC	138	be32_to_cpup(data->map_mask_prop +
	139	irq * data->n_words + idx);
	140	} else {
0aef3997	141	l1_data->irq_map_mask[idx] = 0xffffffff;
7b7230e7	142	}
0aef3997	143	valid_mask[idx] \|= l1_data->irq_map_mask[idx];
7b7230e7	144	}
a5042de2	145
0aef3997	146	l1_data->b = data;
a5042de2	147
0aef3997 FF	148	irq_set_chained_handler_and_data(parent_irq,
0aef3997 FF	149	bcm7120_l2_intc_irq_handle, l1_data);
a5042de2 FF	150	return 0;
	151	}
	152
ca40f1b2 KC	153	static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
	154	struct bcm7120_l2_intc_data *data)
	155	{
	156	int ret;
	157
	158	data->map_base[0] = of_iomap(dn, 0);
	159	if (!data->map_base[0]) {
	160	pr_err("unable to map registers\n");
	161	return -ENOMEM;
	162	}
	163
	164	data->pair_base[0] = data->map_base[0];
	165	data->en_offset[0] = IRQEN;
	166	data->stat_offset[0] = IRQSTAT;
	167	data->n_words = 1;
	168
	169	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	170	data->irq_fwd_mask, data->n_words);
	171	if (ret != 0 && ret != -EINVAL) {
	172	/* property exists but has the wrong number of words */
	173	pr_err("invalid brcm,int-fwd-mask property\n");
	174	return -EINVAL;
	175	}
	176
	177	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	178	if (!data->map_mask_prop \|\|
	179	(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
	180	pr_err("invalid brcm,int-map-mask property\n");
	181	return -EINVAL;
	182	}
	183
	184	return 0;
	185	}
	186
7b7230e7 KC	187	static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
	188	struct bcm7120_l2_intc_data *data)
	189	{
	190	unsigned int gc_idx;
	191
	192	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
	193	unsigned int map_idx = gc_idx * 2;
	194	void __iomem *en = of_iomap(dn, map_idx + 0);
	195	void __iomem *stat = of_iomap(dn, map_idx + 1);
	196	void __iomem *base = min(en, stat);
	197
	198	data->map_base[map_idx + 0] = en;
	199	data->map_base[map_idx + 1] = stat;
	200
	201	if (!base)
	202	break;
	203
	204	data->pair_base[gc_idx] = base;
	205	data->en_offset[gc_idx] = en - base;
	206	data->stat_offset[gc_idx] = stat - base;
	207	}
	208
	209	if (!gc_idx) {
	210	pr_err("unable to map registers\n");
	211	return -EINVAL;
	212	}
	213
	214	data->n_words = gc_idx;
	215	return 0;
	216	}
	217
ca40f1b2 KC	218	int __init bcm7120_l2_intc_probe(struct device_node *dn,
	219	struct device_node *parent,
	220	int (iomap_regs_fn)(struct device_node ,
	221	struct bcm7120_l2_intc_data *),
	222	const char *intc_name)
a5042de2 FF	223	{
	224	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	225	struct bcm7120_l2_intc_data *data;
	226	struct irq_chip_generic *gc;
	227	struct irq_chip_type *ct;
ca40f1b2	228	int ret = 0;
c17261fa	229	unsigned int idx, irq, flags;
0aef3997	230	u32 valid_mask[MAX_WORDS] = { };
a5042de2 FF	231
	232	data = kzalloc(sizeof(*data), GFP_KERNEL);
	233	if (!data)
	234	return -ENOMEM;
	235
ca40f1b2 KC	236	data->num_parent_irqs = of_irq_count(dn);
ca40f1b2 KC	237	if (data->num_parent_irqs <= 0) {
a5042de2 FF	238	pr_err("invalid number of parent interrupts\n");
	239	ret = -ENOMEM;
	240	goto out_unmap;
	241	}
	242
0aef3997 FF	243	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
	244	GFP_KERNEL);
	245	if (!data->l1_data) {
	246	ret = -ENOMEM;
	247	goto out_free_l1_data;
	248	}
	249
ca40f1b2 KC	250	ret = iomap_regs_fn(dn, data);
ca40f1b2 KC	251	if (ret < 0)
0aef3997	252	goto out_free_l1_data;
ca40f1b2 KC	253
	254	for (idx = 0; idx < data->n_words; idx++) {
	255	__raw_writel(data->irq_fwd_mask[idx],
	256	data->pair_base[idx] +
	257	data->en_offset[idx]);
a5042de2 FF	258	}
a5042de2 FF	259
ca40f1b2	260	for (irq = 0; irq < data->num_parent_irqs; irq++) {
0aef3997	261	ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
a5042de2	262	if (ret)
0aef3997	263	goto out_free_l1_data;
a5042de2 FF	264	}
a5042de2 FF	265
c76acf4d KC	266	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	267	&irq_generic_chip_ops, NULL);
a5042de2 FF	268	if (!data->domain) {
a5042de2 FF	269	ret = -ENOMEM;
0aef3997	270	goto out_free_l1_data;
a5042de2 FF	271	}
a5042de2 FF	272
c17261fa KC	273	/* MIPS chips strapped for BE will automagically configure the
	274	* peripheral registers for CPU-native byte order.
	275	*/
	276	flags = IRQ_GC_INIT_MASK_CACHE;
	277	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	278	flags \|= IRQ_GC_BE_IO;
	279
c76acf4d	280	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
c17261fa	281	dn->full_name, handle_level_irq, clr, 0, flags);
a5042de2 FF	282	if (ret) {
	283	pr_err("failed to allocate generic irq chip\n");
	284	goto out_free_domain;
	285	}
	286
c76acf4d	287	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
a5042de2	288	data->can_wake = true;
c76acf4d KC	289
	290	for (idx = 0; idx < data->n_words; idx++) {
	291	irq = idx * IRQS_PER_WORD;
	292	gc = irq_get_domain_generic_chip(data->domain, irq);
	293
0aef3997	294	gc->unused = 0xffffffff & ~valid_mask[idx];
c76acf4d KC	295	gc->private = data;
	296	ct = gc->chip_types;
	297
5b5468cf KC	298	gc->reg_base = data->pair_base[idx];
	299	ct->regs.mask = data->en_offset[idx];
	300
c76acf4d KC	301	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	302	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	303	ct->chip.irq_ack = irq_gc_noop;
fd537766 BN	304	gc->suspend = bcm7120_l2_intc_suspend;
	305	gc->resume = bcm7120_l2_intc_resume;
	306
	307	/*
	308	* Initialize mask-cache, in case we need it for
	309	* saving/restoring fwd mask even w/o any child interrupts
	310	* installed
	311	*/
	312	gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
c76acf4d KC	313
	314	if (data->can_wake) {
	315	/* This IRQ chip can wake the system, set all
	316	* relevant child interupts in wake_enabled mask
	317	*/
	318	gc->wake_enabled = 0xffffffff;
	319	gc->wake_enabled &= ~gc->unused;
	320	ct->chip.irq_set_wake = irq_gc_set_wake;
	321	}
a5042de2 FF	322	}
a5042de2 FF	323
ca40f1b2 KC	324	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
ca40f1b2 KC	325	intc_name, data->map_base[0], data->num_parent_irqs);
a5042de2 FF	326
	327	return 0;
	328
	329	out_free_domain:
	330	irq_domain_remove(data->domain);
0aef3997 FF	331	out_free_l1_data:
0aef3997 FF	332	kfree(data->l1_data);
a5042de2	333	out_unmap:
5b5468cf KC	334	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
	335	if (data->map_base[idx])
	336	iounmap(data->map_base[idx]);
c76acf4d	337	}
a5042de2 FF	338	kfree(data);
	339	return ret;
	340	}
ca40f1b2 KC	341
	342	int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
	343	struct device_node *parent)
	344	{
	345	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
	346	"BCM7120 L2");
	347	}
	348
7b7230e7 KC	349	int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
	350	struct device_node *parent)
	351	{
	352	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
	353	"BCM3380 L2");
	354	}
	355
a4fcbb86	356	IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
ca40f1b2	357	bcm7120_l2_intc_probe_7120);
7b7230e7 KC	358
	359	IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
	360	bcm7120_l2_intc_probe_3380);