[linux-block.git] / drivers / irqchip / irq-bcm7038-l1.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Broadcom BCM7038 style Level 1 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 * Author: Kevin Cernekee
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/syscore_ops.h>

#define IRQS_PER_WORD		32
#define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 4)
#define MAX_WORDS		8

struct bcm7038_l1_cpu;

struct bcm7038_l1_chip {
	raw_spinlock_t		lock;
	unsigned int		n_words;
	struct irq_domain	*domain;
	struct bcm7038_l1_cpu	*cpus[NR_CPUS];
#ifdef CONFIG_PM_SLEEP
	struct list_head	list;
	u32			wake_mask[MAX_WORDS];
#endif
	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
};

struct bcm7038_l1_cpu {
	void __iomem		*map_base;
	u32			mask_cache[0];
};

/*
 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
 *
 * 7038:
 *   0x1000_1400: W0_STATUS
 *   0x1000_1404: W1_STATUS
 *   0x1000_1408: W0_MASK_STATUS
 *   0x1000_140c: W1_MASK_STATUS
 *   0x1000_1410: W0_MASK_SET
 *   0x1000_1414: W1_MASK_SET
 *   0x1000_1418: W0_MASK_CLEAR
 *   0x1000_141c: W1_MASK_CLEAR
 *
 * 7445:
 *   0xf03e_1500: W0_STATUS
 *   0xf03e_1504: W1_STATUS
 *   0xf03e_1508: W2_STATUS
 *   0xf03e_150c: W3_STATUS
 *   0xf03e_1510: W4_STATUS
 *   0xf03e_1514: W0_MASK_STATUS
 *   0xf03e_1518: W1_MASK_STATUS
 *   [...]
 */

static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
				      unsigned int word)
{
	return (0 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
					   unsigned int word)
{
	return (1 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
					unsigned int word)
{
	return (2 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
					unsigned int word)
{
	return (3 * intc->n_words + word) * sizeof(u32);
}

static inline u32 l1_readl(void __iomem *reg)
{
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		return ioread32be(reg);
	else
		return readl(reg);
}

static inline void l1_writel(u32 val, void __iomem *reg)
{
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		iowrite32be(val, reg);
	else
		writel(val, reg);
}

static void bcm7038_l1_irq_handle(struct irq_desc *desc)
{
	struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
	struct bcm7038_l1_cpu *cpu;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

#ifdef CONFIG_SMP
	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
#else
	cpu = intc->cpus[0];
#endif

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < intc->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		unsigned long pending, flags;
		int hwirq;

		raw_spin_lock_irqsave(&intc->lock, flags);
		pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
			  ~cpu->mask_cache[idx];
		raw_spin_unlock_irqrestore(&intc->lock, flags);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(intc->domain,
							    base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
			reg_mask_clr(intc, word));
}

static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	intc->cpus[cpu_idx]->mask_cache[word] |= mask;
	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
			reg_mask_set(intc, word));
}

static void bcm7038_l1_unmask(struct irq_data *d)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

static void bcm7038_l1_mask(struct irq_data *d)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

static int bcm7038_l1_set_affinity(struct irq_data *d,
				   const struct cpumask *dest,
				   bool force)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;
	irq_hw_number_t hw = d->hwirq;
	u32 word = hw / IRQS_PER_WORD;
	u32 mask = BIT(hw % IRQS_PER_WORD);
	unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
	bool was_disabled;

	raw_spin_lock_irqsave(&intc->lock, flags);

	was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
			  mask);
	__bcm7038_l1_mask(d, intc->affinity[hw]);
	intc->affinity[hw] = first_cpu;
	if (!was_disabled)
		__bcm7038_l1_unmask(d, first_cpu);

	raw_spin_unlock_irqrestore(&intc->lock, flags);
	irq_data_update_effective_affinity(d, cpumask_of(first_cpu));

	return 0;
}

#ifdef CONFIG_SMP
static void bcm7038_l1_cpu_offline(struct irq_data *d)
{
	struct cpumask *mask = irq_data_get_affinity_mask(d);
	int cpu = smp_processor_id();
	cpumask_t new_affinity;

	/* This CPU was not on the affinity mask */
	if (!cpumask_test_cpu(cpu, mask))
		return;

	if (cpumask_weight(mask) > 1) {
		/*
		 * Multiple CPU affinity, remove this CPU from the affinity
		 * mask
		 */
		cpumask_copy(&new_affinity, mask);
		cpumask_clear_cpu(cpu, &new_affinity);
	} else {
		/* Only CPU, put on the lowest online CPU */
		cpumask_clear(&new_affinity);
		cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
	}
	irq_set_affinity_locked(d, &new_affinity, false);
}
#endif

static int __init bcm7038_l1_init_one(struct device_node *dn,
				      unsigned int idx,
				      struct bcm7038_l1_chip *intc)
{
	struct resource res;
	resource_size_t sz;
	struct bcm7038_l1_cpu *cpu;
	unsigned int i, n_words, parent_irq;

	if (of_address_to_resource(dn, idx, &res))
		return -EINVAL;
	sz = resource_size(&res);
	n_words = sz / REG_BYTES_PER_IRQ_WORD;

	if (n_words > MAX_WORDS)
		return -EINVAL;
	else if (!intc->n_words)
		intc->n_words = n_words;
	else if (intc->n_words != n_words)
		return -EINVAL;

	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
					GFP_KERNEL);
	if (!cpu)
		return -ENOMEM;

	cpu->map_base = ioremap(res.start, sz);
	if (!cpu->map_base)
		return -ENOMEM;

	for (i = 0; i < n_words; i++) {
		l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
		cpu->mask_cache[i] = 0xffffffff;
	}

	parent_irq = irq_of_parse_and_map(dn, idx);
	if (!parent_irq) {
		pr_err("failed to map parent interrupt %d\n", parent_irq);
		return -EINVAL;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		enable_irq_wake(parent_irq);

	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
					 intc);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
/*
 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
 * used because the struct chip_type suspend/resume hooks are not called
 * unless chip_type is hooked onto a generic_chip. Since this driver does
 * not use generic_chip, we need to manually hook our resume/suspend to
 * syscore_ops.
 */
static LIST_HEAD(bcm7038_l1_intcs_list);
static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);

static int bcm7038_l1_suspend(void)
{
	struct bcm7038_l1_chip *intc;
	int boot_cpu, word;

	/* Wakeup interrupt should only come from the boot cpu */
	boot_cpu = cpu_logical_map(0);

	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
		for (word = 0; word < intc->n_words; word++) {
			l1_writel(~intc->wake_mask[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
			l1_writel(intc->wake_mask[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
		}
	}

	return 0;
}

static void bcm7038_l1_resume(void)
{
	struct bcm7038_l1_chip *intc;
	int boot_cpu, word;

	boot_cpu = cpu_logical_map(0);

	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
		for (word = 0; word < intc->n_words; word++) {
			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
		}
	}
}

static struct syscore_ops bcm7038_l1_syscore_ops = {
	.suspend	= bcm7038_l1_suspend,
	.resume		= bcm7038_l1_resume,
};

static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	raw_spin_lock_irqsave(&intc->lock, flags);
	if (on)
		intc->wake_mask[word] |= mask;
	else
		intc->wake_mask[word] &= ~mask;
	raw_spin_unlock_irqrestore(&intc->lock, flags);

	return 0;
}
#endif

static struct irq_chip bcm7038_l1_irq_chip = {
	.name			= "bcm7038-l1",
	.irq_mask		= bcm7038_l1_mask,
	.irq_unmask		= bcm7038_l1_unmask,
	.irq_set_affinity	= bcm7038_l1_set_affinity,
#ifdef CONFIG_SMP
	.irq_cpu_offline	= bcm7038_l1_cpu_offline,
#endif
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake		= bcm7038_l1_set_wake,
#endif
};

static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
			  irq_hw_number_t hw_irq)
{
	irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
	irq_set_chip_data(virq, d->host_data);
	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
	return 0;
}

static const struct irq_domain_ops bcm7038_l1_domain_ops = {
	.xlate			= irq_domain_xlate_onecell,
	.map			= bcm7038_l1_map,
};

int __init bcm7038_l1_of_init(struct device_node *dn,
			      struct device_node *parent)
{
	struct bcm7038_l1_chip *intc;
	int idx, ret;

	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	if (!intc)
		return -ENOMEM;

	raw_spin_lock_init(&intc->lock);
	for_each_possible_cpu(idx) {
		ret = bcm7038_l1_init_one(dn, idx, intc);
		if (ret < 0) {
			if (idx)
				break;
			pr_err("failed to remap intc L1 registers\n");
			goto out_free;
		}
	}

	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
					     &bcm7038_l1_domain_ops,
					     intc);
	if (!intc->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

#ifdef CONFIG_PM_SLEEP
	/* Add bcm7038_l1_chip into a list */
	raw_spin_lock(&bcm7038_l1_intcs_lock);
	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
	raw_spin_unlock(&bcm7038_l1_intcs_lock);

	if (list_is_singular(&bcm7038_l1_intcs_list))
		register_syscore_ops(&bcm7038_l1_syscore_ops);
#endif

	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
		dn, IRQS_PER_WORD * intc->n_words);

	return 0;

out_unmap:
	for_each_possible_cpu(idx) {
		struct bcm7038_l1_cpu *cpu = intc->cpus[idx];

		if (cpu) {
			if (cpu->map_base)
				iounmap(cpu->map_base);
			kfree(cpu);
		}
	}
out_free:
	kfree(intc);
	return ret;
}

IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
5f7f0317 KC	2	/*
	3	* Broadcom BCM7038 style Level 1 interrupt controller driver
	4	*
	5	* Copyright (C) 2014 Broadcom Corporation
	6	* Author: Kevin Cernekee
5f7f0317 KC	7	*/
	8
	9	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	10
	11	#include <linux/bitops.h>
5f7f0317 KC	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqdomain.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_platform.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/slab.h>
	26	#include <linux/smp.h>
	27	#include <linux/types.h>
41a83e06	28	#include <linux/irqchip.h>
5f7f0317	29	#include <linux/irqchip/chained_irq.h>
6468fc18	30	#include <linux/syscore_ops.h>
5f7f0317	31
5f7f0317 KC	32	#define IRQS_PER_WORD 32
	33	#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
	34	#define MAX_WORDS 8
	35
	36	struct bcm7038_l1_cpu;
	37
	38	struct bcm7038_l1_chip {
	39	raw_spinlock_t lock;
	40	unsigned int n_words;
	41	struct irq_domain *domain;
	42	struct bcm7038_l1_cpu *cpus[NR_CPUS];
6468fc18 JC	43	#ifdef CONFIG_PM_SLEEP
	44	struct list_head list;
	45	u32 wake_mask[MAX_WORDS];
	46	#endif
5f7f0317 KC	47	u8 affinity[MAX_WORDS * IRQS_PER_WORD];
	48	};
	49
	50	struct bcm7038_l1_cpu {
	51	void __iomem *map_base;
	52	u32 mask_cache[0];
	53	};
	54
	55	/*
	56	* STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
	57	*
	58	* 7038:
	59	* 0x1000_1400: W0_STATUS
	60	* 0x1000_1404: W1_STATUS
	61	* 0x1000_1408: W0_MASK_STATUS
	62	* 0x1000_140c: W1_MASK_STATUS
	63	* 0x1000_1410: W0_MASK_SET
	64	* 0x1000_1414: W1_MASK_SET
	65	* 0x1000_1418: W0_MASK_CLEAR
	66	* 0x1000_141c: W1_MASK_CLEAR
	67	*
	68	* 7445:
	69	* 0xf03e_1500: W0_STATUS
	70	* 0xf03e_1504: W1_STATUS
	71	* 0xf03e_1508: W2_STATUS
	72	* 0xf03e_150c: W3_STATUS
	73	* 0xf03e_1510: W4_STATUS
	74	* 0xf03e_1514: W0_MASK_STATUS
	75	* 0xf03e_1518: W1_MASK_STATUS
	76	* [...]
	77	*/
	78
	79	static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
	80	unsigned int word)
	81	{
	82	return (0 * intc->n_words + word) * sizeof(u32);
	83	}
	84
	85	static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
	86	unsigned int word)
	87	{
	88	return (1 * intc->n_words + word) * sizeof(u32);
	89	}
	90
	91	static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
	92	unsigned int word)
	93	{
	94	return (2 * intc->n_words + word) * sizeof(u32);
	95	}
	96
	97	static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
	98	unsigned int word)
	99	{
	100	return (3 * intc->n_words + word) * sizeof(u32);
	101	}
	102
	103	static inline u32 l1_readl(void __iomem *reg)
	104	{
	105	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	106	return ioread32be(reg);
	107	else
	108	return readl(reg);
	109	}
	110
111	static inline void l1_writel(u32 val, void __iomem *reg)
112	{
113	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
114	iowrite32be(val, reg);
115	else
116	writel(val, reg);
117	}
118
bd0b9ac4	119	static void bcm7038_l1_irq_handle(struct irq_desc *desc)
5f7f0317 KC	120	{
	121	struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
	122	struct bcm7038_l1_cpu *cpu;
	123	struct irq_chip *chip = irq_desc_get_chip(desc);
	124	unsigned int idx;
	125
	126	#ifdef CONFIG_SMP
	127	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
	128	#else
	129	cpu = intc->cpus[0];
	130	#endif
	131
	132	chained_irq_enter(chip, desc);
	133
	134	for (idx = 0; idx < intc->n_words; idx++) {
	135	int base = idx * IRQS_PER_WORD;
	136	unsigned long pending, flags;
	137	int hwirq;
	138
	139	raw_spin_lock_irqsave(&intc->lock, flags);
	140	pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
	141	~cpu->mask_cache[idx];
	142	raw_spin_unlock_irqrestore(&intc->lock, flags);
	143
	144	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	145	generic_handle_irq(irq_find_mapping(intc->domain,
	146	base + hwirq));
	147	}
	148	}
	149
	150	chained_irq_exit(chip, desc);
	151	}
	152
	153	static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
	154	{
	155	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	156	u32 word = d->hwirq / IRQS_PER_WORD;
	157	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	158
	159	intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
	160	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
	161	reg_mask_clr(intc, word));
	162	}
	163
	164	static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
	165	{
	166	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	167	u32 word = d->hwirq / IRQS_PER_WORD;
	168	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	169
	170	intc->cpus[cpu_idx]->mask_cache[word] \|= mask;
	171	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
	172	reg_mask_set(intc, word));
	173	}
	174
	175	static void bcm7038_l1_unmask(struct irq_data *d)
	176	{
	177	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	178	unsigned long flags;
	179
	180	raw_spin_lock_irqsave(&intc->lock, flags);
	181	__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
	182	raw_spin_unlock_irqrestore(&intc->lock, flags);
	183	}
184
185	static void bcm7038_l1_mask(struct irq_data *d)
186	{
187	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
188	unsigned long flags;
189
190	raw_spin_lock_irqsave(&intc->lock, flags);
191	__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
192	raw_spin_unlock_irqrestore(&intc->lock, flags);
193	}
194
195	static int bcm7038_l1_set_affinity(struct irq_data *d,
196	const struct cpumask *dest,
197	bool force)
198	{
199	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
200	unsigned long flags;
201	irq_hw_number_t hw = d->hwirq;
202	u32 word = hw / IRQS_PER_WORD;
203	u32 mask = BIT(hw % IRQS_PER_WORD);
204	unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
205	bool was_disabled;
206
207	raw_spin_lock_irqsave(&intc->lock, flags);
208
209	was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
210	mask);
211	__bcm7038_l1_mask(d, intc->affinity[hw]);
212	intc->affinity[hw] = first_cpu;
213	if (!was_disabled)
214	__bcm7038_l1_unmask(d, first_cpu);
215
216	raw_spin_unlock_irqrestore(&intc->lock, flags);
b8d9884a MZ	217	irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
b8d9884a MZ	218
5f7f0317 KC	219	return 0;
	220	}
	221
0702bc4d	222	#ifdef CONFIG_SMP
34c53579 FF	223	static void bcm7038_l1_cpu_offline(struct irq_data *d)
	224	{
	225	struct cpumask *mask = irq_data_get_affinity_mask(d);
	226	int cpu = smp_processor_id();
	227	cpumask_t new_affinity;
	228
	229	/* This CPU was not on the affinity mask */
	230	if (!cpumask_test_cpu(cpu, mask))
	231	return;
	232
	233	if (cpumask_weight(mask) > 1) {
	234	/*
	235	* Multiple CPU affinity, remove this CPU from the affinity
	236	* mask
	237	*/
	238	cpumask_copy(&new_affinity, mask);
	239	cpumask_clear_cpu(cpu, &new_affinity);
	240	} else {
	241	/* Only CPU, put on the lowest online CPU */
	242	cpumask_clear(&new_affinity);
	243	cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
	244	}
	245	irq_set_affinity_locked(d, &new_affinity, false);
	246	}
0702bc4d	247	#endif
34c53579	248
5f7f0317 KC	249	static int __init bcm7038_l1_init_one(struct device_node *dn,
	250	unsigned int idx,
	251	struct bcm7038_l1_chip *intc)
	252	{
	253	struct resource res;
	254	resource_size_t sz;
	255	struct bcm7038_l1_cpu *cpu;
	256	unsigned int i, n_words, parent_irq;
	257
	258	if (of_address_to_resource(dn, idx, &res))
	259	return -EINVAL;
	260	sz = resource_size(&res);
	261	n_words = sz / REG_BYTES_PER_IRQ_WORD;
	262
	263	if (n_words > MAX_WORDS)
	264	return -EINVAL;
	265	else if (!intc->n_words)
	266	intc->n_words = n_words;
	267	else if (intc->n_words != n_words)
	268	return -EINVAL;
	269
	270	cpu = intc->cpus[idx] = kzalloc(sizeof(cpu) + n_words sizeof(u32),
	271	GFP_KERNEL);
	272	if (!cpu)
	273	return -ENOMEM;
	274
	275	cpu->map_base = ioremap(res.start, sz);
	276	if (!cpu->map_base)
	277	return -ENOMEM;
	278
	279	for (i = 0; i < n_words; i++) {
	280	l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
	281	cpu->mask_cache[i] = 0xffffffff;
	282	}
	283
	284	parent_irq = irq_of_parse_and_map(dn, idx);
	285	if (!parent_irq) {
	286	pr_err("failed to map parent interrupt %d\n", parent_irq);
	287	return -EINVAL;
	288	}
27eebb60 FF	289
	290	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
	291	enable_irq_wake(parent_irq);
	292
3a7946ee TG	293	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
3a7946ee TG	294	intc);
5f7f0317 KC	295
	296	return 0;
	297	}
	298
6468fc18 JC	299	#ifdef CONFIG_PM_SLEEP
	300	/*
	301	* We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
	302	* used because the struct chip_type suspend/resume hooks are not called
	303	* unless chip_type is hooked onto a generic_chip. Since this driver does
	304	* not use generic_chip, we need to manually hook our resume/suspend to
	305	* syscore_ops.
	306	*/
	307	static LIST_HEAD(bcm7038_l1_intcs_list);
	308	static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
	309
	310	static int bcm7038_l1_suspend(void)
	311	{
	312	struct bcm7038_l1_chip *intc;
	313	int boot_cpu, word;
	314
	315	/* Wakeup interrupt should only come from the boot cpu */
	316	boot_cpu = cpu_logical_map(0);
	317
	318	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
	319	for (word = 0; word < intc->n_words; word++) {
	320	l1_writel(~intc->wake_mask[word],
	321	intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
	322	l1_writel(intc->wake_mask[word],
	323	intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
	324	}
	325	}
	326
	327	return 0;
	328	}
	329
	330	static void bcm7038_l1_resume(void)
	331	{
	332	struct bcm7038_l1_chip *intc;
	333	int boot_cpu, word;
	334
	335	boot_cpu = cpu_logical_map(0);
	336
	337	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
	338	for (word = 0; word < intc->n_words; word++) {
	339	l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
	340	intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
	341	l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
	342	intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
	343	}
	344	}
	345	}
	346
	347	static struct syscore_ops bcm7038_l1_syscore_ops = {
	348	.suspend = bcm7038_l1_suspend,
	349	.resume = bcm7038_l1_resume,
	350	};
	351
	352	static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
	353	{
	354	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	355	unsigned long flags;
	356	u32 word = d->hwirq / IRQS_PER_WORD;
	357	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	358
	359	raw_spin_lock_irqsave(&intc->lock, flags);
	360	if (on)
	361	intc->wake_mask[word] \|= mask;
	362	else
363	intc->wake_mask[word] &= ~mask;
364	raw_spin_unlock_irqrestore(&intc->lock, flags);
365
366	return 0;
367	}
368	#endif
369
5f7f0317 KC	370	static struct irq_chip bcm7038_l1_irq_chip = {
	371	.name = "bcm7038-l1",
	372	.irq_mask = bcm7038_l1_mask,
	373	.irq_unmask = bcm7038_l1_unmask,
	374	.irq_set_affinity = bcm7038_l1_set_affinity,
0702bc4d	375	#ifdef CONFIG_SMP
34c53579	376	.irq_cpu_offline = bcm7038_l1_cpu_offline,
0702bc4d	377	#endif
6468fc18 JC	378	#ifdef CONFIG_PM_SLEEP
	379	.irq_set_wake = bcm7038_l1_set_wake,
	380	#endif
5f7f0317 KC	381	};
	382
	383	static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
	384	irq_hw_number_t hw_irq)
	385	{
	386	irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
	387	irq_set_chip_data(virq, d->host_data);
b8d9884a	388	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
5f7f0317 KC	389	return 0;
	390	}
	391
	392	static const struct irq_domain_ops bcm7038_l1_domain_ops = {
	393	.xlate = irq_domain_xlate_onecell,
	394	.map = bcm7038_l1_map,
	395	};
	396
	397	int __init bcm7038_l1_of_init(struct device_node *dn,
	398	struct device_node *parent)
	399	{
	400	struct bcm7038_l1_chip *intc;
	401	int idx, ret;
	402
	403	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	404	if (!intc)
	405	return -ENOMEM;
	406
	407	raw_spin_lock_init(&intc->lock);
	408	for_each_possible_cpu(idx) {
	409	ret = bcm7038_l1_init_one(dn, idx, intc);
	410	if (ret < 0) {
	411	if (idx)
	412	break;
	413	pr_err("failed to remap intc L1 registers\n");
	414	goto out_free;
	415	}
	416	}
	417
	418	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
	419	&bcm7038_l1_domain_ops,
	420	intc);
	421	if (!intc->domain) {
	422	ret = -ENOMEM;
	423	goto out_unmap;
	424	}
	425
6468fc18 JC	426	#ifdef CONFIG_PM_SLEEP
	427	/* Add bcm7038_l1_chip into a list */
	428	raw_spin_lock(&bcm7038_l1_intcs_lock);
	429	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
	430	raw_spin_unlock(&bcm7038_l1_intcs_lock);
	431
	432	if (list_is_singular(&bcm7038_l1_intcs_list))
	433	register_syscore_ops(&bcm7038_l1_syscore_ops);
	434	#endif
	435
082ce27f FF	436	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
	437	dn, IRQS_PER_WORD * intc->n_words);
	438
5f7f0317 KC	439	return 0;
	440
	441	out_unmap:
	442	for_each_possible_cpu(idx) {
	443	struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
	444
	445	if (cpu) {
	446	if (cpu->map_base)
	447	iounmap(cpu->map_base);
	448	kfree(cpu);
	449	}
	450	}
	451	out_free:
	452	kfree(intc);
	453	return ret;
	454	}
	455
	456	IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);