[linux-block.git] / drivers / irqchip / irq-bcm7038-l1.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Broadcom BCM7038 style Level 1 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 * Author: Kevin Cernekee
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/syscore_ops.h>

#define IRQS_PER_WORD		32
#define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 4)
#define MAX_WORDS		8

struct bcm7038_l1_cpu;

struct bcm7038_l1_chip {
	raw_spinlock_t		lock;
	unsigned int		n_words;
	struct irq_domain	*domain;
	struct bcm7038_l1_cpu	*cpus[NR_CPUS];
#ifdef CONFIG_PM_SLEEP
	struct list_head	list;
	u32			wake_mask[MAX_WORDS];
#endif
	u32			irq_fwd_mask[MAX_WORDS];
	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
};

struct bcm7038_l1_cpu {
	void __iomem		*map_base;
	u32			mask_cache[];
};

/*
 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
 *
 * 7038:
 *   0x1000_1400: W0_STATUS
 *   0x1000_1404: W1_STATUS
 *   0x1000_1408: W0_MASK_STATUS
 *   0x1000_140c: W1_MASK_STATUS
 *   0x1000_1410: W0_MASK_SET
 *   0x1000_1414: W1_MASK_SET
 *   0x1000_1418: W0_MASK_CLEAR
 *   0x1000_141c: W1_MASK_CLEAR
 *
 * 7445:
 *   0xf03e_1500: W0_STATUS
 *   0xf03e_1504: W1_STATUS
 *   0xf03e_1508: W2_STATUS
 *   0xf03e_150c: W3_STATUS
 *   0xf03e_1510: W4_STATUS
 *   0xf03e_1514: W0_MASK_STATUS
 *   0xf03e_1518: W1_MASK_STATUS
 *   [...]
 */

static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
				      unsigned int word)
{
	return (0 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
					   unsigned int word)
{
	return (1 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
					unsigned int word)
{
	return (2 * intc->n_words + word) * sizeof(u32);
}

static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
					unsigned int word)
{
	return (3 * intc->n_words + word) * sizeof(u32);
}

static inline u32 l1_readl(void __iomem *reg)
{
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		return ioread32be(reg);
	else
		return readl(reg);
}

static inline void l1_writel(u32 val, void __iomem *reg)
{
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		iowrite32be(val, reg);
	else
		writel(val, reg);
}

static void bcm7038_l1_irq_handle(struct irq_desc *desc)
{
	struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
	struct bcm7038_l1_cpu *cpu;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
#else
	cpu = intc->cpus[0];
#endif

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < intc->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		unsigned long pending, flags;
		int hwirq;

		raw_spin_lock_irqsave(&intc->lock, flags);
		pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
			  ~cpu->mask_cache[idx];
		raw_spin_unlock_irqrestore(&intc->lock, flags);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
			generic_handle_domain_irq(intc->domain, base + hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
			reg_mask_clr(intc, word));
}

static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	intc->cpus[cpu_idx]->mask_cache[word] |= mask;
	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
			reg_mask_set(intc, word));
}

static void bcm7038_l1_unmask(struct irq_data *d)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

static void bcm7038_l1_mask(struct irq_data *d)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

#if defined(CONFIG_MIPS) && defined(CONFIG_SMP)
static int bcm7038_l1_set_affinity(struct irq_data *d,
				   const struct cpumask *dest,
				   bool force)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;
	irq_hw_number_t hw = d->hwirq;
	u32 word = hw / IRQS_PER_WORD;
	u32 mask = BIT(hw % IRQS_PER_WORD);
	unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
	bool was_disabled;

	raw_spin_lock_irqsave(&intc->lock, flags);

	was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
			  mask);
	__bcm7038_l1_mask(d, intc->affinity[hw]);
	intc->affinity[hw] = first_cpu;
	if (!was_disabled)
		__bcm7038_l1_unmask(d, first_cpu);

	raw_spin_unlock_irqrestore(&intc->lock, flags);
	irq_data_update_effective_affinity(d, cpumask_of(first_cpu));

	return 0;
}
#endif

static int __init bcm7038_l1_init_one(struct device_node *dn,
				      unsigned int idx,
				      struct bcm7038_l1_chip *intc)
{
	struct resource res;
	resource_size_t sz;
	struct bcm7038_l1_cpu *cpu;
	unsigned int i, n_words, parent_irq;
	int ret;

	if (of_address_to_resource(dn, idx, &res))
		return -EINVAL;
	sz = resource_size(&res);
	n_words = sz / REG_BYTES_PER_IRQ_WORD;

	if (n_words > MAX_WORDS)
		return -EINVAL;
	else if (!intc->n_words)
		intc->n_words = n_words;
	else if (intc->n_words != n_words)
		return -EINVAL;

	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
					 intc->irq_fwd_mask, n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
					GFP_KERNEL);
	if (!cpu)
		return -ENOMEM;

	cpu->map_base = ioremap(res.start, sz);
	if (!cpu->map_base)
		return -ENOMEM;

	for (i = 0; i < n_words; i++) {
		l1_writel(~intc->irq_fwd_mask[i],
			  cpu->map_base + reg_mask_set(intc, i));
		l1_writel(intc->irq_fwd_mask[i],
			  cpu->map_base + reg_mask_clr(intc, i));
		cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
	}

	parent_irq = irq_of_parse_and_map(dn, idx);
	if (!parent_irq) {
		pr_err("failed to map parent interrupt %d\n", parent_irq);
		return -EINVAL;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		enable_irq_wake(parent_irq);

	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
					 intc);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
/*
 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
 * used because the struct chip_type suspend/resume hooks are not called
 * unless chip_type is hooked onto a generic_chip. Since this driver does
 * not use generic_chip, we need to manually hook our resume/suspend to
 * syscore_ops.
 */
static LIST_HEAD(bcm7038_l1_intcs_list);
static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);

static int bcm7038_l1_suspend(void)
{
	struct bcm7038_l1_chip *intc;
	int boot_cpu, word;
	u32 val;

	/* Wakeup interrupt should only come from the boot cpu */
#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
	boot_cpu = cpu_logical_map(0);
#else
	boot_cpu = 0;
#endif

	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
		for (word = 0; word < intc->n_words; word++) {
			val = intc->wake_mask[word] | intc->irq_fwd_mask[word];
			l1_writel(~val,
				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
			l1_writel(val,
				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
		}
	}

	return 0;
}

static void bcm7038_l1_resume(void)
{
	struct bcm7038_l1_chip *intc;
	int boot_cpu, word;

#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
	boot_cpu = cpu_logical_map(0);
#else
	boot_cpu = 0;
#endif

	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
		for (word = 0; word < intc->n_words; word++) {
			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
		}
	}
}

static struct syscore_ops bcm7038_l1_syscore_ops = {
	.suspend	= bcm7038_l1_suspend,
	.resume		= bcm7038_l1_resume,
};

static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
{
	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);

	raw_spin_lock_irqsave(&intc->lock, flags);
	if (on)
		intc->wake_mask[word] |= mask;
	else
		intc->wake_mask[word] &= ~mask;
	raw_spin_unlock_irqrestore(&intc->lock, flags);

	return 0;
}
#endif

static struct irq_chip bcm7038_l1_irq_chip = {
	.name			= "bcm7038-l1",
	.irq_mask		= bcm7038_l1_mask,
	.irq_unmask		= bcm7038_l1_unmask,
#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
	.irq_set_affinity	= bcm7038_l1_set_affinity,
#endif
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake		= bcm7038_l1_set_wake,
#endif
};

static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
			  irq_hw_number_t hw_irq)
{
	struct bcm7038_l1_chip *intc = d->host_data;
	u32 mask = BIT(hw_irq % IRQS_PER_WORD);
	u32 word = hw_irq / IRQS_PER_WORD;

	if (intc->irq_fwd_mask[word] & mask)
		return -EPERM;

	irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
	irq_set_chip_data(virq, d->host_data);
	irqd_set_single_target(irq_get_irq_data(virq));
	return 0;
}

static const struct irq_domain_ops bcm7038_l1_domain_ops = {
	.xlate			= irq_domain_xlate_onecell,
	.map			= bcm7038_l1_map,
};

static int __init bcm7038_l1_of_init(struct device_node *dn,
			      struct device_node *parent)
{
	struct bcm7038_l1_chip *intc;
	int idx, ret;

	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	if (!intc)
		return -ENOMEM;

	raw_spin_lock_init(&intc->lock);
	for_each_possible_cpu(idx) {
		ret = bcm7038_l1_init_one(dn, idx, intc);
		if (ret < 0) {
			if (idx)
				break;
			pr_err("failed to remap intc L1 registers\n");
			goto out_free;
		}
	}

	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
					     &bcm7038_l1_domain_ops,
					     intc);
	if (!intc->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

#ifdef CONFIG_PM_SLEEP
	/* Add bcm7038_l1_chip into a list */
	raw_spin_lock(&bcm7038_l1_intcs_lock);
	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
	raw_spin_unlock(&bcm7038_l1_intcs_lock);

	if (list_is_singular(&bcm7038_l1_intcs_list))
		register_syscore_ops(&bcm7038_l1_syscore_ops);
#endif

	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
		dn, IRQS_PER_WORD * intc->n_words);

	return 0;

out_unmap:
	for_each_possible_cpu(idx) {
		struct bcm7038_l1_cpu *cpu = intc->cpus[idx];

		if (cpu) {
			if (cpu->map_base)
				iounmap(cpu->map_base);
			kfree(cpu);
		}
	}
out_free:
	kfree(intc);
	return ret;
}

IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1)
IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_of_init)
IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1)
MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
5f7f0317 KC	2	/*
	3	* Broadcom BCM7038 style Level 1 interrupt controller driver
	4	*
	5	* Copyright (C) 2014 Broadcom Corporation
	6	* Author: Kevin Cernekee
5f7f0317 KC	7	*/
	8
	9	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	10
	11	#include <linux/bitops.h>
5f7f0317 KC	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqdomain.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_platform.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/slab.h>
	26	#include <linux/smp.h>
	27	#include <linux/types.h>
41a83e06	28	#include <linux/irqchip.h>
5f7f0317	29	#include <linux/irqchip/chained_irq.h>
6468fc18	30	#include <linux/syscore_ops.h>
5f7f0317	31
5f7f0317 KC	32	#define IRQS_PER_WORD 32
	33	#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
	34	#define MAX_WORDS 8
	35
	36	struct bcm7038_l1_cpu;
	37
	38	struct bcm7038_l1_chip {
	39	raw_spinlock_t lock;
	40	unsigned int n_words;
	41	struct irq_domain *domain;
	42	struct bcm7038_l1_cpu *cpus[NR_CPUS];
6468fc18 JC	43	#ifdef CONFIG_PM_SLEEP
	44	struct list_head list;
	45	u32 wake_mask[MAX_WORDS];
	46	#endif
96de80c1	47	u32 irq_fwd_mask[MAX_WORDS];
5f7f0317 KC	48	u8 affinity[MAX_WORDS * IRQS_PER_WORD];
	49	};
	50
	51	struct bcm7038_l1_cpu {
	52	void __iomem *map_base;
b2e1cbfd	53	u32 mask_cache[];
5f7f0317 KC	54	};
	55
	56	/*
	57	* STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
	58	*
	59	* 7038:
	60	* 0x1000_1400: W0_STATUS
	61	* 0x1000_1404: W1_STATUS
	62	* 0x1000_1408: W0_MASK_STATUS
	63	* 0x1000_140c: W1_MASK_STATUS
	64	* 0x1000_1410: W0_MASK_SET
	65	* 0x1000_1414: W1_MASK_SET
	66	* 0x1000_1418: W0_MASK_CLEAR
	67	* 0x1000_141c: W1_MASK_CLEAR
	68	*
	69	* 7445:
	70	* 0xf03e_1500: W0_STATUS
	71	* 0xf03e_1504: W1_STATUS
	72	* 0xf03e_1508: W2_STATUS
	73	* 0xf03e_150c: W3_STATUS
	74	* 0xf03e_1510: W4_STATUS
	75	* 0xf03e_1514: W0_MASK_STATUS
	76	* 0xf03e_1518: W1_MASK_STATUS
	77	* [...]
	78	*/
	79
	80	static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
	81	unsigned int word)
	82	{
	83	return (0 * intc->n_words + word) * sizeof(u32);
	84	}
	85
	86	static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
	87	unsigned int word)
	88	{
	89	return (1 * intc->n_words + word) * sizeof(u32);
	90	}
	91
	92	static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
	93	unsigned int word)
	94	{
	95	return (2 * intc->n_words + word) * sizeof(u32);
	96	}
	97
	98	static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
	99	unsigned int word)
	100	{
	101	return (3 * intc->n_words + word) * sizeof(u32);
	102	}
	103
	104	static inline u32 l1_readl(void __iomem *reg)
	105	{
	106	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	107	return ioread32be(reg);
	108	else
	109	return readl(reg);
	110	}
	111
	112	static inline void l1_writel(u32 val, void __iomem *reg)
	113	{
	114	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	115	iowrite32be(val, reg);
	116	else
	117	writel(val, reg);
118	}
119
bd0b9ac4	120	static void bcm7038_l1_irq_handle(struct irq_desc *desc)
5f7f0317 KC	121	{
	122	struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
	123	struct bcm7038_l1_cpu *cpu;
	124	struct irq_chip *chip = irq_desc_get_chip(desc);
	125	unsigned int idx;
	126
35eb2ef5	127	#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
5f7f0317 KC	128	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
	129	#else
	130	cpu = intc->cpus[0];
	131	#endif
	132
	133	chained_irq_enter(chip, desc);
	134
	135	for (idx = 0; idx < intc->n_words; idx++) {
	136	int base = idx * IRQS_PER_WORD;
	137	unsigned long pending, flags;
	138	int hwirq;
	139
	140	raw_spin_lock_irqsave(&intc->lock, flags);
	141	pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
	142	~cpu->mask_cache[idx];
	143	raw_spin_unlock_irqrestore(&intc->lock, flags);
	144
046a6ee2 MZ	145	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
046a6ee2 MZ	146	generic_handle_domain_irq(intc->domain, base + hwirq);
5f7f0317 KC	147	}
	148
	149	chained_irq_exit(chip, desc);
	150	}
	151
	152	static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
	153	{
	154	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	155	u32 word = d->hwirq / IRQS_PER_WORD;
	156	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	157
	158	intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
	159	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
	160	reg_mask_clr(intc, word));
	161	}
	162
	163	static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
	164	{
	165	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	166	u32 word = d->hwirq / IRQS_PER_WORD;
	167	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	168
	169	intc->cpus[cpu_idx]->mask_cache[word] \|= mask;
	170	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
	171	reg_mask_set(intc, word));
	172	}
	173
	174	static void bcm7038_l1_unmask(struct irq_data *d)
	175	{
	176	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	177	unsigned long flags;
	178
	179	raw_spin_lock_irqsave(&intc->lock, flags);
	180	__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
	181	raw_spin_unlock_irqrestore(&intc->lock, flags);
	182	}
	183
	184	static void bcm7038_l1_mask(struct irq_data *d)
	185	{
	186	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	187	unsigned long flags;
	188
	189	raw_spin_lock_irqsave(&intc->lock, flags);
	190	__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
	191	raw_spin_unlock_irqrestore(&intc->lock, flags);
	192	}
	193
3578fd47	194	#if defined(CONFIG_MIPS) && defined(CONFIG_SMP)
5f7f0317 KC	195	static int bcm7038_l1_set_affinity(struct irq_data *d,
	196	const struct cpumask *dest,
	197	bool force)
	198	{
	199	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	200	unsigned long flags;
	201	irq_hw_number_t hw = d->hwirq;
	202	u32 word = hw / IRQS_PER_WORD;
	203	u32 mask = BIT(hw % IRQS_PER_WORD);
	204	unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
	205	bool was_disabled;
	206
	207	raw_spin_lock_irqsave(&intc->lock, flags);
	208
	209	was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
	210	mask);
	211	__bcm7038_l1_mask(d, intc->affinity[hw]);
	212	intc->affinity[hw] = first_cpu;
	213	if (!was_disabled)
	214	__bcm7038_l1_unmask(d, first_cpu);
	215
	216	raw_spin_unlock_irqrestore(&intc->lock, flags);
b8d9884a MZ	217	irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
b8d9884a MZ	218
5f7f0317 KC	219	return 0;
5f7f0317 KC	220	}
3578fd47	221	#endif
5f7f0317 KC	222
	223	static int __init bcm7038_l1_init_one(struct device_node *dn,
	224	unsigned int idx,
	225	struct bcm7038_l1_chip *intc)
	226	{
	227	struct resource res;
	228	resource_size_t sz;
	229	struct bcm7038_l1_cpu *cpu;
	230	unsigned int i, n_words, parent_irq;
96de80c1	231	int ret;
5f7f0317 KC	232
	233	if (of_address_to_resource(dn, idx, &res))
	234	return -EINVAL;
	235	sz = resource_size(&res);
	236	n_words = sz / REG_BYTES_PER_IRQ_WORD;
	237
	238	if (n_words > MAX_WORDS)
	239	return -EINVAL;
	240	else if (!intc->n_words)
	241	intc->n_words = n_words;
	242	else if (intc->n_words != n_words)
	243	return -EINVAL;
	244
96de80c1 FF	245	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
	246	intc->irq_fwd_mask, n_words);
	247	if (ret != 0 && ret != -EINVAL) {
	248	/* property exists but has the wrong number of words */
	249	pr_err("invalid brcm,int-fwd-mask property\n");
	250	return -EINVAL;
	251	}
	252
5f7f0317 KC	253	cpu = intc->cpus[idx] = kzalloc(sizeof(cpu) + n_words sizeof(u32),
	254	GFP_KERNEL);
	255	if (!cpu)
	256	return -ENOMEM;
	257
	258	cpu->map_base = ioremap(res.start, sz);
	259	if (!cpu->map_base)
	260	return -ENOMEM;
	261
	262	for (i = 0; i < n_words; i++) {
96de80c1 FF	263	l1_writel(~intc->irq_fwd_mask[i],
	264	cpu->map_base + reg_mask_set(intc, i));
	265	l1_writel(intc->irq_fwd_mask[i],
	266	cpu->map_base + reg_mask_clr(intc, i));
	267	cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
5f7f0317 KC	268	}
	269
	270	parent_irq = irq_of_parse_and_map(dn, idx);
	271	if (!parent_irq) {
	272	pr_err("failed to map parent interrupt %d\n", parent_irq);
	273	return -EINVAL;
	274	}
27eebb60 FF	275
	276	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
	277	enable_irq_wake(parent_irq);
	278
3a7946ee TG	279	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
3a7946ee TG	280	intc);
5f7f0317 KC	281
	282	return 0;
	283	}
	284
6468fc18 JC	285	#ifdef CONFIG_PM_SLEEP
	286	/*
	287	* We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
	288	* used because the struct chip_type suspend/resume hooks are not called
	289	* unless chip_type is hooked onto a generic_chip. Since this driver does
	290	* not use generic_chip, we need to manually hook our resume/suspend to
	291	* syscore_ops.
	292	*/
	293	static LIST_HEAD(bcm7038_l1_intcs_list);
	294	static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
	295
	296	static int bcm7038_l1_suspend(void)
	297	{
	298	struct bcm7038_l1_chip *intc;
	299	int boot_cpu, word;
96de80c1	300	u32 val;
6468fc18 JC	301
6468fc18 JC	302	/* Wakeup interrupt should only come from the boot cpu */
35eb2ef5	303	#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
6468fc18	304	boot_cpu = cpu_logical_map(0);
9808357f FF	305	#else
	306	boot_cpu = 0;
	307	#endif
6468fc18 JC	308
	309	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
	310	for (word = 0; word < intc->n_words; word++) {
96de80c1 FF	311	val = intc->wake_mask[word] \| intc->irq_fwd_mask[word];
96de80c1 FF	312	l1_writel(~val,
6468fc18	313	intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
96de80c1	314	l1_writel(val,
6468fc18 JC	315	intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
	316	}
	317	}
	318
	319	return 0;
	320	}
	321
	322	static void bcm7038_l1_resume(void)
	323	{
	324	struct bcm7038_l1_chip *intc;
	325	int boot_cpu, word;
	326
35eb2ef5	327	#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
6468fc18	328	boot_cpu = cpu_logical_map(0);
9808357f FF	329	#else
	330	boot_cpu = 0;
	331	#endif
6468fc18 JC	332
	333	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
	334	for (word = 0; word < intc->n_words; word++) {
	335	l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
	336	intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
	337	l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
	338	intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
	339	}
	340	}
	341	}
	342
	343	static struct syscore_ops bcm7038_l1_syscore_ops = {
	344	.suspend = bcm7038_l1_suspend,
	345	.resume = bcm7038_l1_resume,
	346	};
	347
	348	static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
	349	{
	350	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
	351	unsigned long flags;
	352	u32 word = d->hwirq / IRQS_PER_WORD;
	353	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	354
	355	raw_spin_lock_irqsave(&intc->lock, flags);
	356	if (on)
	357	intc->wake_mask[word] \|= mask;
	358	else
	359	intc->wake_mask[word] &= ~mask;
	360	raw_spin_unlock_irqrestore(&intc->lock, flags);
	361
	362	return 0;
	363	}
	364	#endif
	365
5f7f0317 KC	366	static struct irq_chip bcm7038_l1_irq_chip = {
	367	.name = "bcm7038-l1",
	368	.irq_mask = bcm7038_l1_mask,
	369	.irq_unmask = bcm7038_l1_unmask,
3578fd47	370	#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
5f7f0317	371	.irq_set_affinity = bcm7038_l1_set_affinity,
3578fd47	372	#endif
6468fc18 JC	373	#ifdef CONFIG_PM_SLEEP
	374	.irq_set_wake = bcm7038_l1_set_wake,
	375	#endif
5f7f0317 KC	376	};
	377
	378	static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
	379	irq_hw_number_t hw_irq)
	380	{
96de80c1 FF	381	struct bcm7038_l1_chip *intc = d->host_data;
	382	u32 mask = BIT(hw_irq % IRQS_PER_WORD);
	383	u32 word = hw_irq / IRQS_PER_WORD;
	384
	385	if (intc->irq_fwd_mask[word] & mask)
	386	return -EPERM;
	387
5f7f0317 KC	388	irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
5f7f0317 KC	389	irq_set_chip_data(virq, d->host_data);
4b551920	390	irqd_set_single_target(irq_get_irq_data(virq));
5f7f0317 KC	391	return 0;
	392	}
	393
	394	static const struct irq_domain_ops bcm7038_l1_domain_ops = {
	395	.xlate = irq_domain_xlate_onecell,
	396	.map = bcm7038_l1_map,
	397	};
	398
8f374923	399	static int __init bcm7038_l1_of_init(struct device_node *dn,
5f7f0317 KC	400	struct device_node *parent)
	401	{
	402	struct bcm7038_l1_chip *intc;
	403	int idx, ret;
	404
	405	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	406	if (!intc)
	407	return -ENOMEM;
	408
	409	raw_spin_lock_init(&intc->lock);
	410	for_each_possible_cpu(idx) {
	411	ret = bcm7038_l1_init_one(dn, idx, intc);
	412	if (ret < 0) {
	413	if (idx)
	414	break;
	415	pr_err("failed to remap intc L1 registers\n");
	416	goto out_free;
	417	}
	418	}
	419
	420	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
	421	&bcm7038_l1_domain_ops,
	422	intc);
	423	if (!intc->domain) {
	424	ret = -ENOMEM;
	425	goto out_unmap;
	426	}
	427
6468fc18 JC	428	#ifdef CONFIG_PM_SLEEP
	429	/* Add bcm7038_l1_chip into a list */
	430	raw_spin_lock(&bcm7038_l1_intcs_lock);
	431	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
	432	raw_spin_unlock(&bcm7038_l1_intcs_lock);
	433
	434	if (list_is_singular(&bcm7038_l1_intcs_list))
	435	register_syscore_ops(&bcm7038_l1_syscore_ops);
	436	#endif
	437
082ce27f FF	438	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
	439	dn, IRQS_PER_WORD * intc->n_words);
	440
5f7f0317 KC	441	return 0;
	442
	443	out_unmap:
	444	for_each_possible_cpu(idx) {
	445	struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
	446
	447	if (cpu) {
	448	if (cpu->map_base)
	449	iounmap(cpu->map_base);
	450	kfree(cpu);
	451	}
	452	}
	453	out_free:
	454	kfree(intc);
	455	return ret;
	456	}
	457
c057c799 FF	458	IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1)
	459	IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_of_init)
	460	IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1)
	461	MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller");
	462	MODULE_LICENSE("GPL v2");