[linux-2.6-block.git] / drivers / irqchip / irq-bcm6345-l1.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Broadcom BCM6345 style Level 1 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 * Copyright 2015 Simon Arlott
 *
 * This is based on the BCM7038 (which supports SMP) but with a single
 * enable register instead of separate mask/set/clear registers.
 *
 * The BCM3380 has a similar mask/status register layout, but each pair
 * of words is at separate locations (and SMP is not supported).
 *
 * ENABLE/STATUS words are packed next to each other for each CPU:
 *
 * BCM6368:
 *   0x1000_0020: CPU0_W0_ENABLE
 *   0x1000_0024: CPU0_W1_ENABLE
 *   0x1000_0028: CPU0_W0_STATUS		IRQs 31-63
 *   0x1000_002c: CPU0_W1_STATUS		IRQs 0-31
 *   0x1000_0030: CPU1_W0_ENABLE
 *   0x1000_0034: CPU1_W1_ENABLE
 *   0x1000_0038: CPU1_W0_STATUS		IRQs 31-63
 *   0x1000_003c: CPU1_W1_STATUS		IRQs 0-31
 *
 * BCM63168:
 *   0x1000_0020: CPU0_W0_ENABLE
 *   0x1000_0024: CPU0_W1_ENABLE
 *   0x1000_0028: CPU0_W2_ENABLE
 *   0x1000_002c: CPU0_W3_ENABLE
 *   0x1000_0030: CPU0_W0_STATUS	IRQs 96-127
 *   0x1000_0034: CPU0_W1_STATUS	IRQs 64-95
 *   0x1000_0038: CPU0_W2_STATUS	IRQs 32-63
 *   0x1000_003c: CPU0_W3_STATUS	IRQs 0-31
 *   0x1000_0040: CPU1_W0_ENABLE
 *   0x1000_0044: CPU1_W1_ENABLE
 *   0x1000_0048: CPU1_W2_ENABLE
 *   0x1000_004c: CPU1_W3_ENABLE
 *   0x1000_0050: CPU1_W0_STATUS	IRQs 96-127
 *   0x1000_0054: CPU1_W1_STATUS	IRQs 64-95
 *   0x1000_0058: CPU1_W2_STATUS	IRQs 32-63
 *   0x1000_005c: CPU1_W3_STATUS	IRQs 0-31
 *
 * IRQs are numbered in CPU native endian order
 * (which is big-endian in these examples)
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

#define IRQS_PER_WORD		32
#define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 2)

struct bcm6345_l1_cpu;

struct bcm6345_l1_chip {
	raw_spinlock_t		lock;
	unsigned int		n_words;
	struct irq_domain	*domain;
	struct cpumask		cpumask;
	struct bcm6345_l1_cpu	*cpus[NR_CPUS];
};

struct bcm6345_l1_cpu {
	void __iomem		*map_base;
	unsigned int		parent_irq;
	u32			enable_cache[];
};

static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
					   unsigned int word)
{
#ifdef __BIG_ENDIAN
	return (1 * intc->n_words - word - 1) * sizeof(u32);
#else
	return (0 * intc->n_words + word) * sizeof(u32);
#endif
}

static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
				      unsigned int word)
{
#ifdef __BIG_ENDIAN
	return (2 * intc->n_words - word - 1) * sizeof(u32);
#else
	return (1 * intc->n_words + word) * sizeof(u32);
#endif
}

static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
					struct irq_data *d)
{
	return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
}

static void bcm6345_l1_irq_handle(struct irq_desc *desc)
{
	struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
	struct bcm6345_l1_cpu *cpu;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

#ifdef CONFIG_SMP
	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
#else
	cpu = intc->cpus[0];
#endif

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < intc->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		unsigned long pending;
		irq_hw_number_t hwirq;
		unsigned int irq;

		pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
		pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			irq = irq_linear_revmap(intc->domain, base + hwirq);
			if (irq)
				do_IRQ(irq);
			else
				spurious_interrupt();
		}
	}

	chained_irq_exit(chip, desc);
}

static inline void __bcm6345_l1_unmask(struct irq_data *d)
{
	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	unsigned int cpu_idx = cpu_for_irq(intc, d);

	intc->cpus[cpu_idx]->enable_cache[word] |= mask;
	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
}

static inline void __bcm6345_l1_mask(struct irq_data *d)
{
	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	unsigned int cpu_idx = cpu_for_irq(intc, d);

	intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
}

static void bcm6345_l1_unmask(struct irq_data *d)
{
	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm6345_l1_unmask(d);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

static void bcm6345_l1_mask(struct irq_data *d)
{
	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
	unsigned long flags;

	raw_spin_lock_irqsave(&intc->lock, flags);
	__bcm6345_l1_mask(d);
	raw_spin_unlock_irqrestore(&intc->lock, flags);
}

static int bcm6345_l1_set_affinity(struct irq_data *d,
				   const struct cpumask *dest,
				   bool force)
{
	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
	u32 word = d->hwirq / IRQS_PER_WORD;
	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
	unsigned int old_cpu = cpu_for_irq(intc, d);
	unsigned int new_cpu;
	struct cpumask valid;
	unsigned long flags;
	bool enabled;

	if (!cpumask_and(&valid, &intc->cpumask, dest))
		return -EINVAL;

	new_cpu = cpumask_any_and(&valid, cpu_online_mask);
	if (new_cpu >= nr_cpu_ids)
		return -EINVAL;

	dest = cpumask_of(new_cpu);

	raw_spin_lock_irqsave(&intc->lock, flags);
	if (old_cpu != new_cpu) {
		enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
		if (enabled)
			__bcm6345_l1_mask(d);
		cpumask_copy(irq_data_get_affinity_mask(d), dest);
		if (enabled)
			__bcm6345_l1_unmask(d);
	} else {
		cpumask_copy(irq_data_get_affinity_mask(d), dest);
	}
	raw_spin_unlock_irqrestore(&intc->lock, flags);

	irq_data_update_effective_affinity(d, cpumask_of(new_cpu));

	return IRQ_SET_MASK_OK_NOCOPY;
}

static int __init bcm6345_l1_init_one(struct device_node *dn,
				      unsigned int idx,
				      struct bcm6345_l1_chip *intc)
{
	struct resource res;
	resource_size_t sz;
	struct bcm6345_l1_cpu *cpu;
	unsigned int i, n_words;

	if (of_address_to_resource(dn, idx, &res))
		return -EINVAL;
	sz = resource_size(&res);
	n_words = sz / REG_BYTES_PER_IRQ_WORD;

	if (!intc->n_words)
		intc->n_words = n_words;
	else if (intc->n_words != n_words)
		return -EINVAL;

	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
					GFP_KERNEL);
	if (!cpu)
		return -ENOMEM;

	cpu->map_base = ioremap(res.start, sz);
	if (!cpu->map_base)
		return -ENOMEM;

	for (i = 0; i < n_words; i++) {
		cpu->enable_cache[i] = 0;
		__raw_writel(0, cpu->map_base + reg_enable(intc, i));
	}

	cpu->parent_irq = irq_of_parse_and_map(dn, idx);
	if (!cpu->parent_irq) {
		pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
		return -EINVAL;
	}
	irq_set_chained_handler_and_data(cpu->parent_irq,
						bcm6345_l1_irq_handle, intc);

	return 0;
}

static struct irq_chip bcm6345_l1_irq_chip = {
	.name			= "bcm6345-l1",
	.irq_mask		= bcm6345_l1_mask,
	.irq_unmask		= bcm6345_l1_unmask,
	.irq_set_affinity	= bcm6345_l1_set_affinity,
};

static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
			  irq_hw_number_t hw_irq)
{
	irq_set_chip_and_handler(virq,
		&bcm6345_l1_irq_chip, handle_percpu_irq);
	irq_set_chip_data(virq, d->host_data);
	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
	return 0;
}

static const struct irq_domain_ops bcm6345_l1_domain_ops = {
	.xlate			= irq_domain_xlate_onecell,
	.map			= bcm6345_l1_map,
};

static int __init bcm6345_l1_of_init(struct device_node *dn,
			      struct device_node *parent)
{
	struct bcm6345_l1_chip *intc;
	unsigned int idx;
	int ret;

	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	if (!intc)
		return -ENOMEM;

	for_each_possible_cpu(idx) {
		ret = bcm6345_l1_init_one(dn, idx, intc);
		if (ret)
			pr_err("failed to init intc L1 for cpu %d: %d\n",
				idx, ret);
		else
			cpumask_set_cpu(idx, &intc->cpumask);
	}

	if (!cpumask_weight(&intc->cpumask)) {
		ret = -ENODEV;
		goto out_free;
	}

	raw_spin_lock_init(&intc->lock);

	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
					     &bcm6345_l1_domain_ops,
					     intc);
	if (!intc->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
			IRQS_PER_WORD * intc->n_words);
	for_each_cpu(idx, &intc->cpumask) {
		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];

		pr_info("  CPU%u at MMIO 0x%p (irq = %d)\n", idx,
				cpu->map_base, cpu->parent_irq);
	}

	return 0;

out_unmap:
	for_each_possible_cpu(idx) {
		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];

		if (cpu) {
			if (cpu->map_base)
				iounmap(cpu->map_base);
			kfree(cpu);
		}
	}
out_free:
	kfree(intc);
	return ret;
}

IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
c7c42ec2 SA	2	/*
	3	* Broadcom BCM6345 style Level 1 interrupt controller driver
	4	*
	5	* Copyright (C) 2014 Broadcom Corporation
	6	* Copyright 2015 Simon Arlott
	7	*
c7c42ec2 SA	8	* This is based on the BCM7038 (which supports SMP) but with a single
	9	* enable register instead of separate mask/set/clear registers.
	10	*
	11	* The BCM3380 has a similar mask/status register layout, but each pair
	12	* of words is at separate locations (and SMP is not supported).
	13	*
	14	* ENABLE/STATUS words are packed next to each other for each CPU:
	15	*
	16	* BCM6368:
	17	* 0x1000_0020: CPU0_W0_ENABLE
	18	* 0x1000_0024: CPU0_W1_ENABLE
	19	* 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
	20	* 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
	21	* 0x1000_0030: CPU1_W0_ENABLE
	22	* 0x1000_0034: CPU1_W1_ENABLE
	23	* 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
	24	* 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
	25	*
	26	* BCM63168:
	27	* 0x1000_0020: CPU0_W0_ENABLE
	28	* 0x1000_0024: CPU0_W1_ENABLE
	29	* 0x1000_0028: CPU0_W2_ENABLE
	30	* 0x1000_002c: CPU0_W3_ENABLE
	31	* 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
	32	* 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
	33	* 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
	34	* 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
	35	* 0x1000_0040: CPU1_W0_ENABLE
	36	* 0x1000_0044: CPU1_W1_ENABLE
	37	* 0x1000_0048: CPU1_W2_ENABLE
	38	* 0x1000_004c: CPU1_W3_ENABLE
	39	* 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
	40	* 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
	41	* 0x1000_0058: CPU1_W2_STATUS IRQs 32-63
	42	* 0x1000_005c: CPU1_W3_STATUS IRQs 0-31
	43	*
	44	* IRQs are numbered in CPU native endian order
	45	* (which is big-endian in these examples)
	46	*/
	47
	48	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	49
	50	#include <linux/bitops.h>
	51	#include <linux/cpumask.h>
c7c42ec2 SA	52	#include <linux/kernel.h>
	53	#include <linux/init.h>
	54	#include <linux/interrupt.h>
	55	#include <linux/io.h>
	56	#include <linux/ioport.h>
	57	#include <linux/irq.h>
	58	#include <linux/irqdomain.h>
	59	#include <linux/module.h>
	60	#include <linux/of.h>
	61	#include <linux/of_irq.h>
	62	#include <linux/of_address.h>
	63	#include <linux/of_platform.h>
	64	#include <linux/platform_device.h>
	65	#include <linux/slab.h>
	66	#include <linux/smp.h>
	67	#include <linux/types.h>
	68	#include <linux/irqchip.h>
	69	#include <linux/irqchip/chained_irq.h>
	70
	71	#define IRQS_PER_WORD 32
	72	#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2)
	73
	74	struct bcm6345_l1_cpu;
	75
	76	struct bcm6345_l1_chip {
	77	raw_spinlock_t lock;
	78	unsigned int n_words;
	79	struct irq_domain *domain;
	80	struct cpumask cpumask;
	81	struct bcm6345_l1_cpu *cpus[NR_CPUS];
	82	};
	83
	84	struct bcm6345_l1_cpu {
	85	void __iomem *map_base;
	86	unsigned int parent_irq;
	87	u32 enable_cache[];
	88	};
	89
	90	static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
	91	unsigned int word)
	92	{
	93	#ifdef __BIG_ENDIAN
	94	return (1 * intc->n_words - word - 1) * sizeof(u32);
	95	#else
	96	return (0 * intc->n_words + word) * sizeof(u32);
	97	#endif
	98	}
	99
	100	static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
	101	unsigned int word)
	102	{
	103	#ifdef __BIG_ENDIAN
	104	return (2 * intc->n_words - word - 1) * sizeof(u32);
	105	#else
	106	return (1 * intc->n_words + word) * sizeof(u32);
	107	#endif
	108	}
	109
	110	static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
	111	struct irq_data *d)
	112	{
	113	return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
	114	}
	115
116	static void bcm6345_l1_irq_handle(struct irq_desc *desc)
117	{
118	struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
119	struct bcm6345_l1_cpu *cpu;
120	struct irq_chip *chip = irq_desc_get_chip(desc);
121	unsigned int idx;
122
123	#ifdef CONFIG_SMP
124	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
125	#else
126	cpu = intc->cpus[0];
127	#endif
128
129	chained_irq_enter(chip, desc);
130
131	for (idx = 0; idx < intc->n_words; idx++) {
132	int base = idx * IRQS_PER_WORD;
133	unsigned long pending;
134	irq_hw_number_t hwirq;
135	unsigned int irq;
136
137	pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
138	pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
139
140	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
141	irq = irq_linear_revmap(intc->domain, base + hwirq);
142	if (irq)
143	do_IRQ(irq);
144	else
145	spurious_interrupt();
146	}
147	}
148
149	chained_irq_exit(chip, desc);
150	}
151
152	static inline void __bcm6345_l1_unmask(struct irq_data *d)
153	{
154	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
155	u32 word = d->hwirq / IRQS_PER_WORD;
156	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
157	unsigned int cpu_idx = cpu_for_irq(intc, d);
158
159	intc->cpus[cpu_idx]->enable_cache[word] \|= mask;
160	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
161	intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
162	}
163
164	static inline void __bcm6345_l1_mask(struct irq_data *d)
165	{
166	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
167	u32 word = d->hwirq / IRQS_PER_WORD;
168	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
169	unsigned int cpu_idx = cpu_for_irq(intc, d);
170
171	intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
172	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
173	intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
174	}
175
176	static void bcm6345_l1_unmask(struct irq_data *d)
177	{
178	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
179	unsigned long flags;
180
181	raw_spin_lock_irqsave(&intc->lock, flags);
182	__bcm6345_l1_unmask(d);
183	raw_spin_unlock_irqrestore(&intc->lock, flags);
184	}
185
186	static void bcm6345_l1_mask(struct irq_data *d)
187	{
188	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
189	unsigned long flags;
190
191	raw_spin_lock_irqsave(&intc->lock, flags);
192	__bcm6345_l1_mask(d);
193	raw_spin_unlock_irqrestore(&intc->lock, flags);
194	}
195
196	static int bcm6345_l1_set_affinity(struct irq_data *d,
197	const struct cpumask *dest,
198	bool force)
199	{
200	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
201	u32 word = d->hwirq / IRQS_PER_WORD;
202	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
203	unsigned int old_cpu = cpu_for_irq(intc, d);
204	unsigned int new_cpu;
205	struct cpumask valid;
206	unsigned long flags;
207	bool enabled;
208
209	if (!cpumask_and(&valid, &intc->cpumask, dest))
210	return -EINVAL;
211
212	new_cpu = cpumask_any_and(&valid, cpu_online_mask);
213	if (new_cpu >= nr_cpu_ids)
214	return -EINVAL;
215
216	dest = cpumask_of(new_cpu);
217
218	raw_spin_lock_irqsave(&intc->lock, flags);
219	if (old_cpu != new_cpu) {
220	enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
221	if (enabled)
222	__bcm6345_l1_mask(d);
223	cpumask_copy(irq_data_get_affinity_mask(d), dest);
224	if (enabled)
225	__bcm6345_l1_unmask(d);
226	} else {
227	cpumask_copy(irq_data_get_affinity_mask(d), dest);
228	}
229	raw_spin_unlock_irqrestore(&intc->lock, flags);
230
d0ed5e8e MZ	231	irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
d0ed5e8e MZ	232
c7c42ec2 SA	233	return IRQ_SET_MASK_OK_NOCOPY;
	234	}
	235
	236	static int __init bcm6345_l1_init_one(struct device_node *dn,
	237	unsigned int idx,
	238	struct bcm6345_l1_chip *intc)
	239	{
	240	struct resource res;
	241	resource_size_t sz;
	242	struct bcm6345_l1_cpu *cpu;
	243	unsigned int i, n_words;
	244
	245	if (of_address_to_resource(dn, idx, &res))
	246	return -EINVAL;
	247	sz = resource_size(&res);
	248	n_words = sz / REG_BYTES_PER_IRQ_WORD;
	249
	250	if (!intc->n_words)
	251	intc->n_words = n_words;
	252	else if (intc->n_words != n_words)
	253	return -EINVAL;
	254
	255	cpu = intc->cpus[idx] = kzalloc(sizeof(cpu) + n_words sizeof(u32),
	256	GFP_KERNEL);
	257	if (!cpu)
	258	return -ENOMEM;
	259
	260	cpu->map_base = ioremap(res.start, sz);
	261	if (!cpu->map_base)
	262	return -ENOMEM;
	263
	264	for (i = 0; i < n_words; i++) {
	265	cpu->enable_cache[i] = 0;
	266	__raw_writel(0, cpu->map_base + reg_enable(intc, i));
	267	}
	268
	269	cpu->parent_irq = irq_of_parse_and_map(dn, idx);
	270	if (!cpu->parent_irq) {
	271	pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
	272	return -EINVAL;
	273	}
	274	irq_set_chained_handler_and_data(cpu->parent_irq,
	275	bcm6345_l1_irq_handle, intc);
	276
	277	return 0;
	278	}
	279
	280	static struct irq_chip bcm6345_l1_irq_chip = {
	281	.name = "bcm6345-l1",
	282	.irq_mask = bcm6345_l1_mask,
	283	.irq_unmask = bcm6345_l1_unmask,
	284	.irq_set_affinity = bcm6345_l1_set_affinity,
	285	};
	286
	287	static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
	288	irq_hw_number_t hw_irq)
	289	{
	290	irq_set_chip_and_handler(virq,
	291	&bcm6345_l1_irq_chip, handle_percpu_irq);
	292	irq_set_chip_data(virq, d->host_data);
d0ed5e8e	293	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
c7c42ec2 SA	294	return 0;
	295	}
	296
	297	static const struct irq_domain_ops bcm6345_l1_domain_ops = {
	298	.xlate = irq_domain_xlate_onecell,
	299	.map = bcm6345_l1_map,
	300	};
	301
	302	static int __init bcm6345_l1_of_init(struct device_node *dn,
	303	struct device_node *parent)
	304	{
	305	struct bcm6345_l1_chip *intc;
	306	unsigned int idx;
	307	int ret;
	308
	309	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
	310	if (!intc)
	311	return -ENOMEM;
	312
	313	for_each_possible_cpu(idx) {
	314	ret = bcm6345_l1_init_one(dn, idx, intc);
	315	if (ret)
	316	pr_err("failed to init intc L1 for cpu %d: %d\n",
	317	idx, ret);
	318	else
	319	cpumask_set_cpu(idx, &intc->cpumask);
	320	}
	321
	322	if (!cpumask_weight(&intc->cpumask)) {
	323	ret = -ENODEV;
	324	goto out_free;
	325	}
	326
	327	raw_spin_lock_init(&intc->lock);
	328
	329	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
	330	&bcm6345_l1_domain_ops,
	331	intc);
	332	if (!intc->domain) {
	333	ret = -ENOMEM;
	334	goto out_unmap;
	335	}
	336
	337	pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
	338	IRQS_PER_WORD * intc->n_words);
	339	for_each_cpu(idx, &intc->cpumask) {
	340	struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
	341
	342	pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx,
	343	cpu->map_base, cpu->parent_irq);
	344	}
	345
	346	return 0;
	347
	348	out_unmap:
	349	for_each_possible_cpu(idx) {
	350	struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
	351
	352	if (cpu) {
	353	if (cpu->map_base)
	354	iounmap(cpu->map_base);
	355	kfree(cpu);
	356	}
	357	}
358	out_free:
359	kfree(intc);
360	return ret;
361	}
362
363	IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);