[linux-2.6-block.git] / drivers / irqchip / irq-bcm2836.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
 *
 * Copyright 2015 Broadcom
 */

#include <linux/cpu.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/irq-bcm2836.h>

#include <asm/exception.h>

struct bcm2836_arm_irqchip_intc {
	struct irq_domain *domain;
	void __iomem *base;
};

static struct bcm2836_arm_irqchip_intc intc  __read_mostly;

static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
						 unsigned int bit,
						 int cpu)
{
	void __iomem *reg = intc.base + reg_offset + 4 * cpu;

	writel(readl(reg) & ~BIT(bit), reg);
}

static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
						   unsigned int bit,
						 int cpu)
{
	void __iomem *reg = intc.base + reg_offset + 4 * cpu;

	writel(readl(reg) | BIT(bit), reg);
}

static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
{
	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
					     d->hwirq - LOCAL_IRQ_CNTPSIRQ,
					     smp_processor_id());
}

static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
{
	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
					       d->hwirq - LOCAL_IRQ_CNTPSIRQ,
					       smp_processor_id());
}

static struct irq_chip bcm2836_arm_irqchip_timer = {
	.name		= "bcm2836-timer",
	.irq_mask	= bcm2836_arm_irqchip_mask_timer_irq,
	.irq_unmask	= bcm2836_arm_irqchip_unmask_timer_irq,
};

static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
{
	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
}

static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
{
	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
}

static struct irq_chip bcm2836_arm_irqchip_pmu = {
	.name		= "bcm2836-pmu",
	.irq_mask	= bcm2836_arm_irqchip_mask_pmu_irq,
	.irq_unmask	= bcm2836_arm_irqchip_unmask_pmu_irq,
};

static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
{
}

static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
{
}

static struct irq_chip bcm2836_arm_irqchip_gpu = {
	.name		= "bcm2836-gpu",
	.irq_mask	= bcm2836_arm_irqchip_mask_gpu_irq,
	.irq_unmask	= bcm2836_arm_irqchip_unmask_gpu_irq,
};

static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
{
}

static struct irq_chip bcm2836_arm_irqchip_dummy = {
	.name		= "bcm2836-dummy",
	.irq_eoi	= bcm2836_arm_irqchip_dummy_op,
};

static int bcm2836_map(struct irq_domain *d, unsigned int irq,
		       irq_hw_number_t hw)
{
	struct irq_chip *chip;

	switch (hw) {
	case LOCAL_IRQ_MAILBOX0:
		chip = &bcm2836_arm_irqchip_dummy;
		break;
	case LOCAL_IRQ_CNTPSIRQ:
	case LOCAL_IRQ_CNTPNSIRQ:
	case LOCAL_IRQ_CNTHPIRQ:
	case LOCAL_IRQ_CNTVIRQ:
		chip = &bcm2836_arm_irqchip_timer;
		break;
	case LOCAL_IRQ_GPU_FAST:
		chip = &bcm2836_arm_irqchip_gpu;
		break;
	case LOCAL_IRQ_PMU_FAST:
		chip = &bcm2836_arm_irqchip_pmu;
		break;
	default:
		pr_warn_once("Unexpected hw irq: %lu\n", hw);
		return -EINVAL;
	}

	irq_set_percpu_devid(irq);
	irq_domain_set_info(d, irq, hw, chip, d->host_data,
			    handle_percpu_devid_irq, NULL, NULL);
	irq_set_status_flags(irq, IRQ_NOAUTOEN);

	return 0;
}

static void
__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
{
	int cpu = smp_processor_id();
	u32 stat;

	stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
	if (stat) {
		u32 hwirq = ffs(stat) - 1;

		generic_handle_domain_irq(intc.domain, hwirq);
	}
}

#ifdef CONFIG_SMP
static struct irq_domain *ipi_domain;

static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int cpu = smp_processor_id();
	u32 mbox_val;

	chained_irq_enter(chip, desc);

	mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
	if (mbox_val) {
		int hwirq = ffs(mbox_val) - 1;
		generic_handle_domain_irq(ipi_domain, hwirq);
	}

	chained_irq_exit(chip, desc);
}

static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
{
	int cpu = smp_processor_id();

	writel_relaxed(BIT(d->hwirq),
		       intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
}

static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
					      const struct cpumask *mask)
{
	int cpu;
	void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;

	/*
	 * Ensure that stores to normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	smp_wmb();

	for_each_cpu(cpu, mask)
		writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
}

static struct irq_chip bcm2836_arm_irqchip_ipi = {
	.name		= "IPI",
	.irq_mask	= bcm2836_arm_irqchip_dummy_op,
	.irq_unmask	= bcm2836_arm_irqchip_dummy_op,
	.irq_ack	= bcm2836_arm_irqchip_ipi_ack,
	.ipi_send_mask	= bcm2836_arm_irqchip_ipi_send_mask,
};

static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
					 unsigned int virq,
					 unsigned int nr_irqs, void *args)
{
	int i;

	for (i = 0; i < nr_irqs; i++) {
		irq_set_percpu_devid(virq + i);
		irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
				    d->host_data,
				    handle_percpu_devid_irq,
				    NULL, NULL);
	}

	return 0;
}

static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
					 unsigned int virq,
					 unsigned int nr_irqs)
{
	/* Not freeing IPIs */
}

static const struct irq_domain_ops ipi_domain_ops = {
	.alloc	= bcm2836_arm_irqchip_ipi_alloc,
	.free	= bcm2836_arm_irqchip_ipi_free,
};

static int bcm2836_cpu_starting(unsigned int cpu)
{
	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
					       cpu);
	return 0;
}

static int bcm2836_cpu_dying(unsigned int cpu)
{
	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
					     cpu);
	return 0;
}

#define BITS_PER_MBOX	32

static void __init bcm2836_arm_irqchip_smp_init(void)
{
	struct irq_fwspec ipi_fwspec = {
		.fwnode		= intc.domain->fwnode,
		.param_count	= 1,
		.param		= {
			[0]	= LOCAL_IRQ_MAILBOX0,
		},
	};
	int base_ipi, mux_irq;

	mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
	if (WARN_ON(mux_irq <= 0))
		return;

	ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
					      BITS_PER_MBOX, &ipi_domain_ops,
					      NULL);
	if (WARN_ON(!ipi_domain))
		return;

	ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);

	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
					   NUMA_NO_NODE, NULL,
					   false, NULL);

	if (WARN_ON(!base_ipi))
		return;

	set_smp_ipi_range(base_ipi, BITS_PER_MBOX);

	irq_set_chained_handler_and_data(mux_irq,
					 bcm2836_arm_irqchip_handle_ipi, NULL);

	/* Unmask IPIs to the boot CPU. */
	cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
			  "irqchip/bcm2836:starting", bcm2836_cpu_starting,
			  bcm2836_cpu_dying);
}
#else
#define bcm2836_arm_irqchip_smp_init()	do { } while(0)
#endif

static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = bcm2836_map,
};

/*
 * The LOCAL_IRQ_CNT* timer firings are based off of the external
 * oscillator with some scaling.  The firmware sets up CNTFRQ to
 * report 19.2Mhz, but doesn't set up the scaling registers.
 */
static void bcm2835_init_local_timer_frequency(void)
{
	/*
	 * Set the timer to source from the 19.2Mhz crystal clock (bit
	 * 8 unset), and only increment by 1 instead of 2 (bit 9
	 * unset).
	 */
	writel(0, intc.base + LOCAL_CONTROL);

	/*
	 * Set the timer prescaler to 1:1 (timer freq = input freq *
	 * 2**31 / prescaler)
	 */
	writel(0x80000000, intc.base + LOCAL_PRESCALER);
}

static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
						      struct device_node *parent)
{
	intc.base = of_iomap(node, 0);
	if (!intc.base) {
		panic("%pOF: unable to map local interrupt registers\n", node);
	}

	bcm2835_init_local_timer_frequency();

	intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
					    &bcm2836_arm_irqchip_intc_ops,
					    NULL);
	if (!intc.domain)
		panic("%pOF: unable to create IRQ domain\n", node);

	irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);

	bcm2836_arm_irqchip_smp_init();

	set_handle_irq(bcm2836_arm_irqchip_handle_irq);
	return 0;
}

IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
		bcm2836_arm_irqchip_l1_intc_of_init);
Commit	Line	Data
7728819c	1	// SPDX-License-Identifier: GPL-2.0+
1a15aaa9 EA	2	/*
	3	* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
	4	*
	5	* Copyright 2015 Broadcom
1a15aaa9 EA	6	*/
	7
	8	#include <linux/cpu.h>
	9	#include <linux/of_address.h>
	10	#include <linux/of_irq.h>
	11	#include <linux/irqchip.h>
	12	#include <linux/irqdomain.h>
0809ae72	13	#include <linux/irqchip/chained_irq.h>
88bbe85d	14	#include <linux/irqchip/irq-bcm2836.h>
401667bb	15
88bbe85d	16	#include <asm/exception.h>
1a15aaa9 EA	17
	18	struct bcm2836_arm_irqchip_intc {
	19	struct irq_domain *domain;
	20	void __iomem *base;
	21	};
	22
	23	static struct bcm2836_arm_irqchip_intc intc __read_mostly;
	24
	25	static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
	26	unsigned int bit,
	27	int cpu)
	28	{
	29	void __iomem reg = intc.base + reg_offset + 4 cpu;
	30
	31	writel(readl(reg) & ~BIT(bit), reg);
	32	}
	33
	34	static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
	35	unsigned int bit,
	36	int cpu)
	37	{
	38	void __iomem reg = intc.base + reg_offset + 4 cpu;
	39
	40	writel(readl(reg) \| BIT(bit), reg);
	41	}
	42
	43	static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
	44	{
	45	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
	46	d->hwirq - LOCAL_IRQ_CNTPSIRQ,
	47	smp_processor_id());
	48	}
	49
	50	static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
	51	{
	52	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
	53	d->hwirq - LOCAL_IRQ_CNTPSIRQ,
	54	smp_processor_id());
	55	}
	56
	57	static struct irq_chip bcm2836_arm_irqchip_timer = {
	58	.name = "bcm2836-timer",
	59	.irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
	60	.irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
	61	};
	62
	63	static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
	64	{
	65	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
	66	}
	67
	68	static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
	69	{
	70	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
	71	}
	72
	73	static struct irq_chip bcm2836_arm_irqchip_pmu = {
	74	.name = "bcm2836-pmu",
	75	.irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
	76	.irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
	77	};
	78
	79	static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
	80	{
81	}
82
83	static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
84	{
85	}
86
87	static struct irq_chip bcm2836_arm_irqchip_gpu = {
88	.name = "bcm2836-gpu",
89	.irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
90	.irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
91	};
92
0809ae72 MZ	93	static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
	94	{
	95	}
	96
	97	static struct irq_chip bcm2836_arm_irqchip_dummy = {
	98	.name = "bcm2836-dummy",
	99	.irq_eoi = bcm2836_arm_irqchip_dummy_op,
	100	};
	101
ad83c7cb SW	102	static int bcm2836_map(struct irq_domain *d, unsigned int irq,
	103	irq_hw_number_t hw)
	104	{
	105	struct irq_chip *chip;
	106
	107	switch (hw) {
0809ae72 MZ	108	case LOCAL_IRQ_MAILBOX0:
	109	chip = &bcm2836_arm_irqchip_dummy;
	110	break;
ad83c7cb SW	111	case LOCAL_IRQ_CNTPSIRQ:
	112	case LOCAL_IRQ_CNTPNSIRQ:
	113	case LOCAL_IRQ_CNTHPIRQ:
	114	case LOCAL_IRQ_CNTVIRQ:
	115	chip = &bcm2836_arm_irqchip_timer;
	116	break;
	117	case LOCAL_IRQ_GPU_FAST:
	118	chip = &bcm2836_arm_irqchip_gpu;
	119	break;
	120	case LOCAL_IRQ_PMU_FAST:
	121	chip = &bcm2836_arm_irqchip_pmu;
	122	break;
	123	default:
	124	pr_warn_once("Unexpected hw irq: %lu\n", hw);
	125	return -EINVAL;
	126	}
1a15aaa9 EA	127
1a15aaa9 EA	128	irq_set_percpu_devid(irq);
ad83c7cb SW	129	irq_domain_set_info(d, irq, hw, chip, d->host_data,
ad83c7cb SW	130	handle_percpu_devid_irq, NULL, NULL);
1a15aaa9	131	irq_set_status_flags(irq, IRQ_NOAUTOEN);
ad83c7cb SW	132
ad83c7cb SW	133	return 0;
1a15aaa9 EA	134	}
	135
	136	static void
	137	__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
	138	{
	139	int cpu = smp_processor_id();
	140	u32 stat;
	141
	142	stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
0809ae72	143	if (stat) {
1a15aaa9 EA	144	u32 hwirq = ffs(stat) - 1;
1a15aaa9 EA	145
0953fb26	146	generic_handle_domain_irq(intc.domain, hwirq);
1a15aaa9 EA	147	}
	148	}
	149
	150	#ifdef CONFIG_SMP
0809ae72 MZ	151	static struct irq_domain *ipi_domain;
	152
	153	static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
	154	{
	155	struct irq_chip *chip = irq_desc_get_chip(desc);
	156	int cpu = smp_processor_id();
	157	u32 mbox_val;
	158
	159	chained_irq_enter(chip, desc);
	160
	161	mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
	162	if (mbox_val) {
	163	int hwirq = ffs(mbox_val) - 1;
046a6ee2	164	generic_handle_domain_irq(ipi_domain, hwirq);
0809ae72 MZ	165	}
	166
	167	chained_irq_exit(chip, desc);
	168	}
	169
d7f39c40	170	static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
0809ae72 MZ	171	{
	172	int cpu = smp_processor_id();
	173
	174	writel_relaxed(BIT(d->hwirq),
	175	intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
	176	}
	177
	178	static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
	179	const struct cpumask *mask)
1a15aaa9 EA	180	{
	181	int cpu;
	182	void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
	183
	184	/*
	185	* Ensure that stores to normal memory are visible to the
	186	* other CPUs before issuing the IPI.
	187	*/
a1dcbd11	188	smp_wmb();
1a15aaa9	189
0809ae72 MZ	190	for_each_cpu(cpu, mask)
	191	writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
	192	}
	193
	194	static struct irq_chip bcm2836_arm_irqchip_ipi = {
	195	.name = "IPI",
c3330399 MZ	196	.irq_mask = bcm2836_arm_irqchip_dummy_op,
c3330399 MZ	197	.irq_unmask = bcm2836_arm_irqchip_dummy_op,
d7f39c40	198	.irq_ack = bcm2836_arm_irqchip_ipi_ack,
0809ae72 MZ	199	.ipi_send_mask = bcm2836_arm_irqchip_ipi_send_mask,
	200	};
	201
	202	static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
	203	unsigned int virq,
	204	unsigned int nr_irqs, void *args)
	205	{
	206	int i;
	207
	208	for (i = 0; i < nr_irqs; i++) {
	209	irq_set_percpu_devid(virq + i);
	210	irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
	211	d->host_data,
ffdad793	212	handle_percpu_devid_irq,
0809ae72	213	NULL, NULL);
1a15aaa9	214	}
0809ae72 MZ	215
0809ae72 MZ	216	return 0;
1a15aaa9 EA	217	}
1a15aaa9 EA	218
0809ae72 MZ	219	static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
	220	unsigned int virq,
	221	unsigned int nr_irqs)
	222	{
	223	/* Not freeing IPIs */
	224	}
	225
	226	static const struct irq_domain_ops ipi_domain_ops = {
	227	.alloc = bcm2836_arm_irqchip_ipi_alloc,
	228	.free = bcm2836_arm_irqchip_ipi_free,
	229	};
	230
7ca04bc2	231	static int bcm2836_cpu_starting(unsigned int cpu)
1a15aaa9	232	{
7ca04bc2 SAS	233	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
	234	cpu);
	235	return 0;
1a15aaa9 EA	236	}
1a15aaa9 EA	237
7ca04bc2 SAS	238	static int bcm2836_cpu_dying(unsigned int cpu)
	239	{
	240	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
	241	cpu);
	242	return 0;
	243	}
1a15aaa9	244
0809ae72	245	#define BITS_PER_MBOX 32
1a15aaa9	246
57733e00	247	static void __init bcm2836_arm_irqchip_smp_init(void)
1a15aaa9	248	{
0809ae72 MZ	249	struct irq_fwspec ipi_fwspec = {
	250	.fwnode = intc.domain->fwnode,
	251	.param_count = 1,
	252	.param = {
	253	[0] = LOCAL_IRQ_MAILBOX0,
	254	},
	255	};
	256	int base_ipi, mux_irq;
	257
	258	mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
	259	if (WARN_ON(mux_irq <= 0))
	260	return;
	261
	262	ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
	263	BITS_PER_MBOX, &ipi_domain_ops,
	264	NULL);
	265	if (WARN_ON(!ipi_domain))
	266	return;
	267
	268	ipi_domain->flags \|= IRQ_DOMAIN_FLAG_IPI_SINGLE;
	269	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
	270
	271	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
	272	NUMA_NO_NODE, NULL,
	273	false, NULL);
	274
	275	if (WARN_ON(!base_ipi))
	276	return;
	277
	278	set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
	279
	280	irq_set_chained_handler_and_data(mux_irq,
	281	bcm2836_arm_irqchip_handle_ipi, NULL);
	282
1a15aaa9	283	/* Unmask IPIs to the boot CPU. */
7ca04bc2	284	cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
73c1b41e	285	"irqchip/bcm2836:starting", bcm2836_cpu_starting,
7ca04bc2	286	bcm2836_cpu_dying);
1a15aaa9	287	}
0809ae72 MZ	288	#else
	289	#define bcm2836_arm_irqchip_smp_init() do { } while(0)
	290	#endif
	291
	292	static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
	293	.xlate = irq_domain_xlate_onetwocell,
	294	.map = bcm2836_map,
	295	};
1a15aaa9	296
401667bb EA	297	/*
	298	* The LOCAL_IRQ_CNT* timer firings are based off of the external
	299	* oscillator with some scaling. The firmware sets up CNTFRQ to
	300	* report 19.2Mhz, but doesn't set up the scaling registers.
	301	*/
	302	static void bcm2835_init_local_timer_frequency(void)
	303	{
	304	/*
	305	* Set the timer to source from the 19.2Mhz crystal clock (bit
	306	* 8 unset), and only increment by 1 instead of 2 (bit 9
	307	* unset).
	308	*/
	309	writel(0, intc.base + LOCAL_CONTROL);
	310
	311	/*
	312	* Set the timer prescaler to 1:1 (timer freq = input freq *
	313	* 2**31 / prescaler)
	314	*/
	315	writel(0x80000000, intc.base + LOCAL_PRESCALER);
	316	}
	317
1a15aaa9 EA	318	static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
	319	struct device_node *parent)
	320	{
	321	intc.base = of_iomap(node, 0);
	322	if (!intc.base) {
e81f54c6	323	panic("%pOF: unable to map local interrupt registers\n", node);
1a15aaa9 EA	324	}
1a15aaa9 EA	325
401667bb EA	326	bcm2835_init_local_timer_frequency();
401667bb EA	327
1a15aaa9 EA	328	intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
	329	&bcm2836_arm_irqchip_intc_ops,
	330	NULL);
	331	if (!intc.domain)
e81f54c6	332	panic("%pOF: unable to create IRQ domain\n", node);
1a15aaa9	333
0809ae72 MZ	334	irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
0809ae72 MZ	335
1a15aaa9 EA	336	bcm2836_arm_irqchip_smp_init();
	337
	338	set_handle_irq(bcm2836_arm_irqchip_handle_irq);
	339	return 0;
	340	}
	341
	342	IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
	343	bcm2836_arm_irqchip_l1_intc_of_init);