[linux-2.6-block.git] / drivers / irqchip / irq-bcm2835.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2010 Broadcom
 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
 *
 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
 *
 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
 * to look in the bank 1 status register for more information.
 *
 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
 * status register, but bank 0 bit 8 is _not_ set.
 *
 * Quirk 2: You can't mask the register 1/2 pending interrupts
 *
 * In a proper cascaded interrupt controller, the interrupt lines with
 * cascaded interrupt controllers on them are just normal interrupt lines.
 * You can mask the interrupts and get on with things. With this controller
 * you can't do that.
 *
 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
 *
 * Those interrupts that have shortcuts can only be masked/unmasked in
 * their respective banks' enable/disable registers. Doing so in the bank 0
 * enable/disable registers has no effect.
 *
 * The FIQ control register:
 *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
 *  Bit    7: Enable FIQ generation
 *  Bits  8+: Unused
 *
 * An interrupt must be disabled before configuring it for FIQ generation
 * otherwise both handlers will fire at the same time!
 */

#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>

#include <asm/exception.h>

/* Put the bank and irq (32 bits) into the hwirq */
#define MAKE_HWIRQ(b, n)	((b << 5) | (n))
#define HWIRQ_BANK(i)		(i >> 5)
#define HWIRQ_BIT(i)		BIT(i & 0x1f)

#define NR_IRQS_BANK0		8
#define BANK0_HWIRQ_MASK	0xff
/* Shortcuts can't be disabled so any unknown new ones need to be masked */
#define SHORTCUT1_MASK		0x00007c00
#define SHORTCUT2_MASK		0x001f8000
#define SHORTCUT_SHIFT		10
#define BANK1_HWIRQ		BIT(8)
#define BANK2_HWIRQ		BIT(9)
#define BANK0_VALID_MASK	(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
					| SHORTCUT1_MASK | SHORTCUT2_MASK)

#define REG_FIQ_CONTROL		0x0c

#define NR_BANKS		3
#define IRQS_PER_BANK		32

static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
static const int bank_irqs[] __initconst = { 8, 32, 32 };

static const int shortcuts[] = {
	7, 9, 10, 18, 19,		/* Bank 1 */
	21, 22, 23, 24, 25, 30		/* Bank 2 */
};

struct armctrl_ic {
	void __iomem *base;
	void __iomem *pending[NR_BANKS];
	void __iomem *enable[NR_BANKS];
	void __iomem *disable[NR_BANKS];
	struct irq_domain *domain;
};

static struct armctrl_ic intc __read_mostly;
static void __exception_irq_entry bcm2835_handle_irq(
	struct pt_regs *regs);
static void bcm2836_chained_handle_irq(struct irq_desc *desc);

static void armctrl_mask_irq(struct irq_data *d)
{
	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
}

static void armctrl_unmask_irq(struct irq_data *d)
{
	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
}

static struct irq_chip armctrl_chip = {
	.name = "ARMCTRL-level",
	.irq_mask = armctrl_mask_irq,
	.irq_unmask = armctrl_unmask_irq
};

static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
	const u32 *intspec, unsigned int intsize,
	unsigned long *out_hwirq, unsigned int *out_type)
{
	if (WARN_ON(intsize != 2))
		return -EINVAL;

	if (WARN_ON(intspec[0] >= NR_BANKS))
		return -EINVAL;

	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
		return -EINVAL;

	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
		return -EINVAL;

	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
	*out_type = IRQ_TYPE_NONE;
	return 0;
}

static const struct irq_domain_ops armctrl_ops = {
	.xlate = armctrl_xlate
};

static int __init armctrl_of_init(struct device_node *node,
				  struct device_node *parent,
				  bool is_2836)
{
	void __iomem *base;
	int irq, b, i;

	base = of_iomap(node, 0);
	if (!base)
		panic("%pOF: unable to map IC registers\n", node);

	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
			&armctrl_ops, NULL);
	if (!intc.domain)
		panic("%pOF: unable to create IRQ domain\n", node);

	for (b = 0; b < NR_BANKS; b++) {
		intc.pending[b] = base + reg_pending[b];
		intc.enable[b] = base + reg_enable[b];
		intc.disable[b] = base + reg_disable[b];

		for (i = 0; i < bank_irqs[b]; i++) {
			irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
			BUG_ON(irq <= 0);
			irq_set_chip_and_handler(irq, &armctrl_chip,
				handle_level_irq);
			irq_set_probe(irq);
		}
	}

	if (is_2836) {
		int parent_irq = irq_of_parse_and_map(node, 0);

		if (!parent_irq) {
			panic("%pOF: unable to get parent interrupt.\n",
			      node);
		}
		irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
	} else {
		set_handle_irq(bcm2835_handle_irq);
	}

	return 0;
}

static int __init bcm2835_armctrl_of_init(struct device_node *node,
					  struct device_node *parent)
{
	return armctrl_of_init(node, parent, false);
}

static int __init bcm2836_armctrl_of_init(struct device_node *node,
					  struct device_node *parent)
{
	return armctrl_of_init(node, parent, true);
}


/*
 * Handle each interrupt across the entire interrupt controller.  This reads the
 * status register before handling each interrupt, which is necessary given that
 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 */

static u32 armctrl_translate_bank(int bank)
{
	u32 stat = readl_relaxed(intc.pending[bank]);

	return MAKE_HWIRQ(bank, ffs(stat) - 1);
}

static u32 armctrl_translate_shortcut(int bank, u32 stat)
{
	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
}

static u32 get_next_armctrl_hwirq(void)
{
	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;

	if (stat == 0)
		return ~0;
	else if (stat & BANK0_HWIRQ_MASK)
		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
	else if (stat & SHORTCUT1_MASK)
		return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
	else if (stat & SHORTCUT2_MASK)
		return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
	else if (stat & BANK1_HWIRQ)
		return armctrl_translate_bank(1);
	else if (stat & BANK2_HWIRQ)
		return armctrl_translate_bank(2);
	else
		BUG();
}

static void __exception_irq_entry bcm2835_handle_irq(
	struct pt_regs *regs)
{
	u32 hwirq;

	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
		handle_domain_irq(intc.domain, hwirq, regs);
}

static void bcm2836_chained_handle_irq(struct irq_desc *desc)
{
	u32 hwirq;

	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
		generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
}

IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
		bcm2835_armctrl_of_init);
IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
		bcm2836_armctrl_of_init);
Commit	Line	Data
7728819c	1	// SPDX-License-Identifier: GPL-2.0+
89214f00 SA	2	/*
	3	* Copyright 2010 Broadcom
	4	* Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
	5	*
89214f00 SA	6	* Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
	7	*
	8	* If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
	9	* on bank 0 is set to signify that an interrupt in bank 1 has fired, and
	10	* to look in the bank 1 status register for more information.
	11	*
	12	* If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
	13	* shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
	14	* status register, but bank 0 bit 8 is _not_ set.
	15	*
	16	* Quirk 2: You can't mask the register 1/2 pending interrupts
	17	*
	18	* In a proper cascaded interrupt controller, the interrupt lines with
	19	* cascaded interrupt controllers on them are just normal interrupt lines.
	20	* You can mask the interrupts and get on with things. With this controller
	21	* you can't do that.
	22	*
	23	* Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
	24	*
	25	* Those interrupts that have shortcuts can only be masked/unmasked in
	26	* their respective banks' enable/disable registers. Doing so in the bank 0
	27	* enable/disable registers has no effect.
	28	*
	29	* The FIQ control register:
	30	* Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
	31	* Bit 7: Enable FIQ generation
	32	* Bits 8+: Unused
	33	*
	34	* An interrupt must be disabled before configuring it for FIQ generation
	35	* otherwise both handlers will fire at the same time!
	36	*/
	37
	38	#include <linux/io.h>
	39	#include <linux/slab.h>
	40	#include <linux/of_address.h>
	41	#include <linux/of_irq.h>
41a83e06	42	#include <linux/irqchip.h>
89214f00	43	#include <linux/irqdomain.h>
89214f00 SA	44
89214f00 SA	45	#include <asm/exception.h>
5702941e	46
89214f00 SA	47	/* Put the bank and irq (32 bits) into the hwirq */
	48	#define MAKE_HWIRQ(b, n) ((b << 5) \| (n))
	49	#define HWIRQ_BANK(i) (i >> 5)
	50	#define HWIRQ_BIT(i) BIT(i & 0x1f)
	51
	52	#define NR_IRQS_BANK0 8
	53	#define BANK0_HWIRQ_MASK 0xff
	54	/* Shortcuts can't be disabled so any unknown new ones need to be masked */
	55	#define SHORTCUT1_MASK 0x00007c00
	56	#define SHORTCUT2_MASK 0x001f8000
	57	#define SHORTCUT_SHIFT 10
	58	#define BANK1_HWIRQ BIT(8)
	59	#define BANK2_HWIRQ BIT(9)
	60	#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK \| BANK1_HWIRQ \| BANK2_HWIRQ \
	61	\| SHORTCUT1_MASK \| SHORTCUT2_MASK)
	62
	63	#define REG_FIQ_CONTROL 0x0c
	64
	65	#define NR_BANKS 3
	66	#define IRQS_PER_BANK 32
	67
c376023b NP	68	static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
	69	static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
	70	static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
	71	static const int bank_irqs[] __initconst = { 8, 32, 32 };
89214f00 SA	72
	73	static const int shortcuts[] = {
	74	7, 9, 10, 18, 19, /* Bank 1 */
	75	21, 22, 23, 24, 25, 30 /* Bank 2 */
	76	};
	77
	78	struct armctrl_ic {
	79	void __iomem *base;
	80	void __iomem *pending[NR_BANKS];
	81	void __iomem *enable[NR_BANKS];
	82	void __iomem *disable[NR_BANKS];
	83	struct irq_domain *domain;
	84	};
	85
	86	static struct armctrl_ic intc __read_mostly;
8783dd3a	87	static void __exception_irq_entry bcm2835_handle_irq(
5702941e	88	struct pt_regs *regs);
bd0b9ac4	89	static void bcm2836_chained_handle_irq(struct irq_desc *desc);
89214f00 SA	90
	91	static void armctrl_mask_irq(struct irq_data *d)
	92	{
	93	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
	94	}
	95
	96	static void armctrl_unmask_irq(struct irq_data *d)
	97	{
	98	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
	99	}
	100
	101	static struct irq_chip armctrl_chip = {
	102	.name = "ARMCTRL-level",
	103	.irq_mask = armctrl_mask_irq,
	104	.irq_unmask = armctrl_unmask_irq
	105	};
	106
	107	static int armctrl_xlate(struct irq_domain d, struct device_node ctrlr,
	108	const u32 *intspec, unsigned int intsize,
	109	unsigned long out_hwirq, unsigned int out_type)
	110	{
	111	if (WARN_ON(intsize != 2))
	112	return -EINVAL;
	113
	114	if (WARN_ON(intspec[0] >= NR_BANKS))
	115	return -EINVAL;
	116
	117	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
	118	return -EINVAL;
	119
	120	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
	121	return -EINVAL;
	122
	123	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
	124	*out_type = IRQ_TYPE_NONE;
	125	return 0;
	126	}
	127
96009736	128	static const struct irq_domain_ops armctrl_ops = {
89214f00 SA	129	.xlate = armctrl_xlate
	130	};
	131
	132	static int __init armctrl_of_init(struct device_node *node,
a493f339 EA	133	struct device_node *parent,
a493f339 EA	134	bool is_2836)
89214f00 SA	135	{
	136	void __iomem *base;
	137	int irq, b, i;
	138
	139	base = of_iomap(node, 0);
	140	if (!base)
e81f54c6	141	panic("%pOF: unable to map IC registers\n", node);
89214f00 SA	142
	143	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
	144	&armctrl_ops, NULL);
	145	if (!intc.domain)
e81f54c6	146	panic("%pOF: unable to create IRQ domain\n", node);
89214f00 SA	147
	148	for (b = 0; b < NR_BANKS; b++) {
	149	intc.pending[b] = base + reg_pending[b];
	150	intc.enable[b] = base + reg_enable[b];
	151	intc.disable[b] = base + reg_disable[b];
	152
	153	for (i = 0; i < bank_irqs[b]; i++) {
	154	irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
	155	BUG_ON(irq <= 0);
	156	irq_set_chip_and_handler(irq, &armctrl_chip,
	157	handle_level_irq);
d17cab44	158	irq_set_probe(irq);
89214f00 SA	159	}
89214f00 SA	160	}
89214f00	161
a493f339 EA	162	if (is_2836) {
	163	int parent_irq = irq_of_parse_and_map(node, 0);
	164
	165	if (!parent_irq) {
e81f54c6 RH	166	panic("%pOF: unable to get parent interrupt.\n",
e81f54c6 RH	167	node);
a493f339 EA	168	}
	169	irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
	170	} else {
	171	set_handle_irq(bcm2835_handle_irq);
	172	}
	173
5702941e	174	return 0;
89214f00 SA	175	}
89214f00 SA	176
a493f339 EA	177	static int __init bcm2835_armctrl_of_init(struct device_node *node,
	178	struct device_node *parent)
	179	{
	180	return armctrl_of_init(node, parent, false);
	181	}
	182
	183	static int __init bcm2836_armctrl_of_init(struct device_node *node,
	184	struct device_node *parent)
	185	{
	186	return armctrl_of_init(node, parent, true);
	187	}
	188
	189
89214f00 SA	190	/*
	191	* Handle each interrupt across the entire interrupt controller. This reads the
	192	* status register before handling each interrupt, which is necessary given that
	193	* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
	194	*/
	195
de58e52f	196	static u32 armctrl_translate_bank(int bank)
89214f00	197	{
de58e52f	198	u32 stat = readl_relaxed(intc.pending[bank]);
89214f00	199
de58e52f EA	200	return MAKE_HWIRQ(bank, ffs(stat) - 1);
	201	}
	202
	203	static u32 armctrl_translate_shortcut(int bank, u32 stat)
	204	{
	205	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
89214f00 SA	206	}
89214f00 SA	207
de58e52f	208	static u32 get_next_armctrl_hwirq(void)
89214f00	209	{
de58e52f EA	210	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
	211
	212	if (stat == 0)
	213	return ~0;
	214	else if (stat & BANK0_HWIRQ_MASK)
	215	return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
	216	else if (stat & SHORTCUT1_MASK)
	217	return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
	218	else if (stat & SHORTCUT2_MASK)
	219	return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
	220	else if (stat & BANK1_HWIRQ)
	221	return armctrl_translate_bank(1);
	222	else if (stat & BANK2_HWIRQ)
	223	return armctrl_translate_bank(2);
	224	else
	225	BUG();
89214f00 SA	226	}
89214f00 SA	227
8783dd3a	228	static void __exception_irq_entry bcm2835_handle_irq(
89214f00 SA	229	struct pt_regs *regs)
89214f00 SA	230	{
de58e52f EA	231	u32 hwirq;
	232
	233	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
d7e3528e	234	handle_domain_irq(intc.domain, hwirq, regs);
89214f00	235	}
5702941e	236
bd0b9ac4	237	static void bcm2836_chained_handle_irq(struct irq_desc *desc)
a493f339 EA	238	{
	239	u32 hwirq;
	240
	241	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
	242	generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
	243	}
	244
	245	IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
	246	bcm2835_armctrl_of_init);
	247	IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
	248	bcm2836_armctrl_of_init);