[linux-2.6-block.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

#include "irqchip.h"

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
#define ARMADA_375_PPI_CAUSE			(0x10)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)
#define ARMADA_370_XP_FABRIC_IRQ		(3)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
static u32 doorbell_mask_reg;
static int parent_irq;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

static inline bool is_percpu_irq(irq_hw_number_t irq)
{
	switch (irq) {
	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
	case ARMADA_370_XP_FABRIC_IRQ:
		return true;
	default:
		return false;
	}
}

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static int armada_370_xp_alloc_msi(void)
{
	int hwirq;

	mutex_lock(&msi_used_lock);
	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	if (hwirq >= PCI_MSI_DOORBELL_NR)
		hwirq = -ENOSPC;
	else
		set_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);

	return hwirq;
}

static void armada_370_xp_free_msi(int hwirq)
{
	mutex_lock(&msi_used_lock);
	if (!test_bit(hwirq, msi_used))
		pr_err("trying to free unused MSI#%d\n", hwirq);
	else
		clear_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);
}

static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
				       struct pci_dev *pdev,
				       struct msi_desc *desc)
{
	struct msi_msg msg;
	int virq, hwirq;

	/* We support MSI, but not MSI-X */
	if (desc->msi_attrib.is_msix)
		return -EINVAL;

	hwirq = armada_370_xp_alloc_msi();
	if (hwirq < 0)
		return hwirq;

	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	if (!virq) {
		armada_370_xp_free_msi(hwirq);
		return -EINVAL;
	}

	irq_set_msi_desc(virq, desc);

	msg.address_lo = msi_doorbell_addr;
	msg.address_hi = 0;
	msg.data = 0xf00 | (hwirq + 16);

	pci_write_msi_msg(virq, &msg);
	return 0;
}

static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
					   unsigned int irq)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned long hwirq = d->hwirq;

	irq_dispose_mapping(irq);
	armada_370_xp_free_msi(hwirq);
}

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "armada_370_xp_msi_irq",
	.irq_enable = pci_msi_unmask_irq,
	.irq_disable = pci_msi_mask_irq,
	.irq_mask = pci_msi_mask_irq,
	.irq_unmask = pci_msi_unmask_irq,
};

static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
				 handle_simple_irq);
	set_irq_flags(virq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	.map = armada_370_xp_msi_map,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	struct msi_controller *msi_chip;
	u32 reg;
	int ret;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	if (!msi_chip)
		return -ENOMEM;

	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	msi_chip->of_node = node;

	armada_370_xp_msi_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_irq_ops,
				      NULL);
	if (!armada_370_xp_msi_domain) {
		kfree(msi_chip);
		return -ENOMEM;
	}

	ret = of_pci_msi_chip_add(msi_chip);
	if (ret < 0) {
		irq_domain_remove(armada_370_xp_msi_domain);
		kfree(msi_chip);
		return ret;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	unsigned long reg, mask;
	int cpu;

	/* Select a single core from the affinity mask which is online */
	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	mask = 1UL << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);
	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	raw_spin_unlock(&irq_controller_lock);

	return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "armada_370_xp_irq",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (!is_percpu_irq(hw))
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (is_percpu_irq(hw)) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

static void armada_xp_mpic_smp_cpu_init(void)
{
	u32 control;
	int nr_irqs, i;

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);

	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

static void armada_xp_mpic_perf_init(void)
{
	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	/* Enable Performance Counter Overflow interrupts */
	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
}

#ifdef CONFIG_SMP
static void armada_mpic_send_doorbell(const struct cpumask *mask,
				      unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
					 unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		armada_xp_mpic_smp_cpu_init();
	}

	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	.notifier_call = armada_xp_mpic_secondary_init,
	.priority = 100,
};

static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
					unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
	}

	return NOTIFY_OK;
}

static struct notifier_block mpic_cascaded_cpu_notifier = {
	.notifier_call = mpic_cascaded_secondary_init,
	.priority = 100,
};
#endif /* CONFIG_SMP */

static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

#ifdef CONFIG_PCI_MSI
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
{
	u32 msimask, msinr;

	msimask = readl_relaxed(per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
		& PCI_MSI_DOORBELL_MASK;

	writel(~msimask, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	for (msinr = PCI_MSI_DOORBELL_START;
	     msinr < PCI_MSI_DOORBELL_END; msinr++) {
		int irq;

		if (!(msimask & BIT(msinr)))
			continue;

		if (is_chained) {
			irq = irq_find_mapping(armada_370_xp_msi_domain,
					       msinr - 16);
			generic_handle_irq(irq);
		} else {
			irq = msinr - 16;
			handle_domain_irq(armada_370_xp_msi_domain,
					  irq, regs);
		}
	}
}
#else
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
#endif

static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
						  struct irq_desc *desc)
{
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned long irqmap, irqn, irqsrc, cpuid;
	unsigned int cascade_irq;

	chained_irq_enter(chip, desc);

	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
	cpuid = cpu_logical_map(smp_processor_id());

	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
		irqsrc = readl_relaxed(main_int_base +
				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));

		/* Check if the interrupt is not masked on current CPU.
		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
		 */
		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
			continue;

		if (irqn == 1) {
			armada_370_xp_handle_msi_irq(NULL, true);
			continue;
		}

		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
		generic_handle_irq(cascade_irq);
	}

	chained_irq_exit(chip, desc);
}

static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			handle_domain_irq(armada_370_xp_mpic_domain,
					  irqnr, regs);
			continue;
		}

		/* MSI handling */
		if (irqnr == 1)
			armada_370_xp_handle_msi_irq(regs, false);

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~ipimask, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int armada_370_xp_mpic_suspend(void)
{
	doorbell_mask_reg = readl(per_cpu_int_base +
				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	return 0;
}

static void armada_370_xp_mpic_resume(void)
{
	int nirqs;
	irq_hw_number_t irq;

	/* Re-enable interrupts */
	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	for (irq = 0; irq < nirqs; irq++) {
		struct irq_data *data;
		int virq;

		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
		if (virq == 0)
			continue;

		if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
			writel(irq, per_cpu_int_base +
			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
		else
			writel(irq, main_int_base +
			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);

		data = irq_get_irq_data(virq);
		if (!irqd_irq_disabled(data))
			armada_370_xp_irq_unmask(data);
	}

	/* Reconfigure doorbells for IPIs and MSIs */
	writel(doorbell_mask_reg,
	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	.suspend	= armada_370_xp_mpic_suspend,
	.resume		= armada_370_xp_mpic_resume,
};

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	int nr_irqs, i;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, nr_irqs,
				&armada_370_xp_mpic_irq_ops, NULL);

	BUG_ON(!armada_370_xp_mpic_domain);

	/* Setup for the boot CPU */
	armada_xp_mpic_perf_init();
	armada_xp_mpic_smp_cpu_init();

	armada_370_xp_msi_init(node, main_int_res.start);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (parent_irq <= 0) {
		irq_set_default_host(armada_370_xp_mpic_domain);
		set_handle_irq(armada_370_xp_handle_irq);
#ifdef CONFIG_SMP
		set_smp_cross_call(armada_mpic_send_doorbell);
		register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
#endif
	} else {
#ifdef CONFIG_SMP
		register_cpu_notifier(&mpic_cascaded_cpu_notifier);
#endif
		irq_set_chained_handler(parent_irq,
					armada_370_xp_mpic_handle_cascade_irq);
	}

	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
bc69b8ad	21	#include <linux/irqchip/chained_irq.h>
d7df84b3	22	#include <linux/cpu.h>
9ae6f740 TP	23	#include <linux/io.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
31f614ed	26	#include <linux/of_pci.h>
9ae6f740	27	#include <linux/irqdomain.h>
31f614ed	28	#include <linux/slab.h>
0f077eb5	29	#include <linux/syscore_ops.h>
31f614ed	30	#include <linux/msi.h>
9ae6f740 TP	31	#include <asm/mach/arch.h>
9ae6f740 TP	32	#include <asm/exception.h>
344e873e	33	#include <asm/smp_plat.h>
9339d432 TP	34	#include <asm/mach/irq.h>
	35
	36	#include "irqchip.h"
9ae6f740 TP	37
	38	/* Interrupt Controller Registers Map */
	39	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	40	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
28da06df MR	41	#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
28da06df MR	42	#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
9ae6f740	43
f3e16ccd	44	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	45	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	46	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	47	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
8cc3cfc5	48	#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
758e8366	49	#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) \| BIT(8)) << cpuid)
9ae6f740 TP	50
9ae6f740 TP	51	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
bc69b8ad	52	#define ARMADA_375_PPI_CAUSE (0x10)
9ae6f740	53
344e873e GC	54	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	55	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	56	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	57
3202bf01 GC	58	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	59
7f23f62f	60	#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
28da06df	61	#define ARMADA_370_XP_FABRIC_IRQ (3)
7f23f62f	62
5ec69017 TP	63	#define IPI_DOORBELL_START (0)
	64	#define IPI_DOORBELL_END (8)
	65	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	66	#define PCI_MSI_DOORBELL_START (16)
	67	#define PCI_MSI_DOORBELL_NR (16)
	68	#define PCI_MSI_DOORBELL_END (32)
	69	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	70
9ae6f740 TP	71	static void __iomem *per_cpu_int_base;
	72	static void __iomem *main_int_base;
	73	static struct irq_domain *armada_370_xp_mpic_domain;
0f077eb5	74	static u32 doorbell_mask_reg;
5724be84	75	static int parent_irq;
31f614ed TP	76	#ifdef CONFIG_PCI_MSI
	77	static struct irq_domain *armada_370_xp_msi_domain;
	78	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	79	static DEFINE_MUTEX(msi_used_lock);
	80	static phys_addr_t msi_doorbell_addr;
	81	#endif
9ae6f740	82
2c299de5 EG	83	static inline bool is_percpu_irq(irq_hw_number_t irq)
	84	{
	85	switch (irq) {
	86	case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
28da06df	87	case ARMADA_370_XP_FABRIC_IRQ:
2c299de5 EG	88	return true;
	89	default:
	90	return false;
	91	}
	92	}
	93
3202bf01 GC	94	/*
	95	* In SMP mode:
	96	* For shared global interrupts, mask/unmask global enable bit
097ef18d	97	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	98	*/
9ae6f740 TP	99	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	100	{
3202bf01 GC	101	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	102
2c299de5	103	if (!is_percpu_irq(hwirq))
3202bf01 GC	104	writel(hwirq, main_int_base +
	105	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	106	else
	107	writel(hwirq, per_cpu_int_base +
	108	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	109	}
	110
	111	static void armada_370_xp_irq_unmask(struct irq_data *d)
	112	{
3202bf01 GC	113	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	114
2c299de5	115	if (!is_percpu_irq(hwirq))
3202bf01 GC	116	writel(hwirq, main_int_base +
	117	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	118	else
	119	writel(hwirq, per_cpu_int_base +
	120	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	121	}
9ae6f740 TP	122
31f614ed TP	123	#ifdef CONFIG_PCI_MSI
	124
	125	static int armada_370_xp_alloc_msi(void)
	126	{
	127	int hwirq;
	128
	129	mutex_lock(&msi_used_lock);
	130	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	131	if (hwirq >= PCI_MSI_DOORBELL_NR)
	132	hwirq = -ENOSPC;
	133	else
	134	set_bit(hwirq, msi_used);
	135	mutex_unlock(&msi_used_lock);
	136
	137	return hwirq;
	138	}
	139
	140	static void armada_370_xp_free_msi(int hwirq)
	141	{
	142	mutex_lock(&msi_used_lock);
	143	if (!test_bit(hwirq, msi_used))
	144	pr_err("trying to free unused MSI#%d\n", hwirq);
	145	else
	146	clear_bit(hwirq, msi_used);
	147	mutex_unlock(&msi_used_lock);
	148	}
	149
c2791b80	150	static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
31f614ed TP	151	struct pci_dev *pdev,
	152	struct msi_desc *desc)
	153	{
	154	struct msi_msg msg;
da343fc7	155	int virq, hwirq;
31f614ed	156
3930115e AG	157	/* We support MSI, but not MSI-X */
	158	if (desc->msi_attrib.is_msix)
	159	return -EINVAL;
	160
31f614ed TP	161	hwirq = armada_370_xp_alloc_msi();
	162	if (hwirq < 0)
	163	return hwirq;
	164
	165	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	166	if (!virq) {
	167	armada_370_xp_free_msi(hwirq);
	168	return -EINVAL;
	169	}
	170
	171	irq_set_msi_desc(virq, desc);
	172
	173	msg.address_lo = msi_doorbell_addr;
	174	msg.address_hi = 0;
	175	msg.data = 0xf00 \| (hwirq + 16);
	176
83a18912	177	pci_write_msi_msg(virq, &msg);
31f614ed TP	178	return 0;
	179	}
	180
c2791b80	181	static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
31f614ed TP	182	unsigned int irq)
	183	{
	184	struct irq_data *d = irq_get_irq_data(irq);
ff3c6645 NG	185	unsigned long hwirq = d->hwirq;
ff3c6645 NG	186
31f614ed	187	irq_dispose_mapping(irq);
ff3c6645	188	armada_370_xp_free_msi(hwirq);
31f614ed TP	189	}
	190
	191	static struct irq_chip armada_370_xp_msi_irq_chip = {
	192	.name = "armada_370_xp_msi_irq",
280510f1 TG	193	.irq_enable = pci_msi_unmask_irq,
	194	.irq_disable = pci_msi_mask_irq,
	195	.irq_mask = pci_msi_mask_irq,
	196	.irq_unmask = pci_msi_unmask_irq,
31f614ed TP	197	};
	198
	199	static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
	200	irq_hw_number_t hw)
	201	{
	202	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
	203	handle_simple_irq);
	204	set_irq_flags(virq, IRQF_VALID);
	205
	206	return 0;
	207	}
	208
	209	static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	210	.map = armada_370_xp_msi_map,
	211	};
	212
	213	static int armada_370_xp_msi_init(struct device_node *node,
	214	phys_addr_t main_int_phys_base)
	215	{
c2791b80	216	struct msi_controller *msi_chip;
31f614ed TP	217	u32 reg;
	218	int ret;
	219
	220	msi_doorbell_addr = main_int_phys_base +
	221	ARMADA_370_XP_SW_TRIG_INT_OFFS;
	222
	223	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	224	if (!msi_chip)
	225	return -ENOMEM;
	226
	227	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	228	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	229	msi_chip->of_node = node;
	230
	231	armada_370_xp_msi_domain =
	232	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
	233	&armada_370_xp_msi_irq_ops,
	234	NULL);
	235	if (!armada_370_xp_msi_domain) {
	236	kfree(msi_chip);
	237	return -ENOMEM;
	238	}
	239
	240	ret = of_pci_msi_chip_add(msi_chip);
	241	if (ret < 0) {
	242	irq_domain_remove(armada_370_xp_msi_domain);
	243	kfree(msi_chip);
	244	return ret;
	245	}
	246
	247	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
	248	\| PCI_MSI_DOORBELL_MASK;
	249
	250	writel(reg, per_cpu_int_base +
	251	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	252
	253	/* Unmask IPI interrupt */
	254	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	255
	256	return 0;
	257	}
	258	#else
	259	static inline int armada_370_xp_msi_init(struct device_node *node,
	260	phys_addr_t main_int_phys_base)
	261	{
	262	return 0;
	263	}
	264	#endif
	265
344e873e	266	#ifdef CONFIG_SMP
19e61d41 AE	267	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
19e61d41 AE	268
344e873e GC	269	static int armada_xp_set_affinity(struct irq_data *d,
	270	const struct cpumask *mask_val, bool force)
	271	{
3202bf01	272	irq_hw_number_t hwirq = irqd_to_hwirq(d);
8cc3cfc5	273	unsigned long reg, mask;
3202bf01 GC	274	int cpu;
3202bf01 GC	275
8cc3cfc5 TG	276	/* Select a single core from the affinity mask which is online */
	277	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	278	mask = 1UL << cpu_logical_map(cpu);
3202bf01 GC	279
3202bf01 GC	280	raw_spin_lock(&irq_controller_lock);
3202bf01	281	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
8cc3cfc5	282	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) \| mask;
3202bf01	283	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
3202bf01 GC	284	raw_spin_unlock(&irq_controller_lock);
3202bf01 GC	285
1dacf194	286	return IRQ_SET_MASK_OK;
344e873e GC	287	}
	288	#endif
	289
9ae6f740 TP	290	static struct irq_chip armada_370_xp_irq_chip = {
	291	.name = "armada_370_xp_irq",
	292	.irq_mask = armada_370_xp_irq_mask,
	293	.irq_mask_ack = armada_370_xp_irq_mask,
	294	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	295	#ifdef CONFIG_SMP
	296	.irq_set_affinity = armada_xp_set_affinity,
	297	#endif
0d8e1d80	298	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
9ae6f740 TP	299	};
	300
	301	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	302	unsigned int virq, irq_hw_number_t hw)
	303	{
	304	armada_370_xp_irq_mask(irq_get_irq_data(virq));
2c299de5	305	if (!is_percpu_irq(hw))
600468d0 GC	306	writel(hw, per_cpu_int_base +
	307	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	308	else
	309	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	310	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	311
2c299de5	312	if (is_percpu_irq(hw)) {
3a6f08a3 GC	313	irq_set_percpu_devid(virq);
	314	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	315	handle_percpu_devid_irq);
	316
	317	} else {
	318	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	319	handle_level_irq);
	320	}
9ae6f740 TP	321	set_irq_flags(virq, IRQF_VALID \| IRQF_PROBE);
	322
	323	return 0;
	324	}
	325
d7df84b3	326	static void armada_xp_mpic_smp_cpu_init(void)
344e873e	327	{
b73842b7 TP	328	u32 control;
	329	int nr_irqs, i;
	330
	331	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	332	nr_irqs = (control >> 2) & 0x3ff;
	333
	334	for (i = 0; i < nr_irqs; i++)
	335	writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
	336
344e873e GC	337	/* Clear pending IPIs */
	338	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	339
	340	/* Enable first 8 IPIs */
5ec69017	341	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	342	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	343
	344	/* Unmask IPI interrupt */
	345	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	346	}
d7df84b3	347
28da06df MR	348	static void armada_xp_mpic_perf_init(void)
	349	{
	350	unsigned long cpuid = cpu_logical_map(smp_processor_id());
	351
	352	/* Enable Performance Counter Overflow interrupts */
	353	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	354	per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
	355	}
	356
933a24b0 EG	357	#ifdef CONFIG_SMP
	358	static void armada_mpic_send_doorbell(const struct cpumask *mask,
	359	unsigned int irq)
	360	{
	361	int cpu;
	362	unsigned long map = 0;
	363
	364	/* Convert our logical CPU mask into a physical one. */
	365	for_each_cpu(cpu, mask)
	366	map \|= 1 << cpu_logical_map(cpu);
	367
	368	/*
	369	* Ensure that stores to Normal memory are visible to the
	370	* other CPUs before issuing the IPI.
	371	*/
	372	dsb();
	373
	374	/* submit softirq */
	375	writel((map << 8) \| irq, main_int_base +
	376	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	377	}
	378
d7df84b3 TP	379	static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
	380	unsigned long action, void *hcpu)
	381	{
28da06df MR	382	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	383	armada_xp_mpic_perf_init();
d7df84b3	384	armada_xp_mpic_smp_cpu_init();
28da06df	385	}
5724be84	386
d7df84b3 TP	387	return NOTIFY_OK;
	388	}
	389
	390	static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	391	.notifier_call = armada_xp_mpic_secondary_init,
	392	.priority = 100,
	393	};
	394
5724be84 MR	395	static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
	396	unsigned long action, void *hcpu)
	397	{
28da06df MR	398	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	399	armada_xp_mpic_perf_init();
5724be84	400	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
28da06df	401	}
5724be84 MR	402
	403	return NOTIFY_OK;
	404	}
	405
	406	static struct notifier_block mpic_cascaded_cpu_notifier = {
	407	.notifier_call = mpic_cascaded_secondary_init,
	408	.priority = 100,
	409	};
344e873e GC	410	#endif /* CONFIG_SMP */
344e873e GC	411
96009736	412	static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
9ae6f740 TP	413	.map = armada_370_xp_mpic_irq_map,
	414	.xlate = irq_domain_xlate_onecell,
	415	};
	416
9b8cf779	417	#ifdef CONFIG_PCI_MSI
bc69b8ad	418	static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
9b8cf779 EG	419	{
	420	u32 msimask, msinr;
	421
	422	msimask = readl_relaxed(per_cpu_int_base +
	423	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	424	& PCI_MSI_DOORBELL_MASK;
	425
	426	writel(~msimask, per_cpu_int_base +
	427	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	428
	429	for (msinr = PCI_MSI_DOORBELL_START;
	430	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	431	int irq;
	432
	433	if (!(msimask & BIT(msinr)))
	434	continue;
	435
e89c6a06 MZ	436	if (is_chained) {
	437	irq = irq_find_mapping(armada_370_xp_msi_domain,
	438	msinr - 16);
bc69b8ad	439	generic_handle_irq(irq);
e89c6a06 MZ	440	} else {
	441	irq = msinr - 16;
	442	handle_domain_irq(armada_370_xp_msi_domain,
	443	irq, regs);
	444	}
9b8cf779 EG	445	}
	446	}
	447	#else
bc69b8ad	448	static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
9b8cf779 EG	449	#endif
9b8cf779 EG	450
bc69b8ad EG	451	static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
	452	struct irq_desc *desc)
	453	{
	454	struct irq_chip *chip = irq_get_chip(irq);
758e8366	455	unsigned long irqmap, irqn, irqsrc, cpuid;
bc69b8ad EG	456	unsigned int cascade_irq;
	457
	458	chained_irq_enter(chip, desc);
	459
	460	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
758e8366	461	cpuid = cpu_logical_map(smp_processor_id());
bc69b8ad EG	462
bc69b8ad EG	463	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
758e8366 GJ	464	irqsrc = readl_relaxed(main_int_base +
	465	ARMADA_370_XP_INT_SOURCE_CTL(irqn));
	466
	467	/* Check if the interrupt is not masked on current CPU.
	468	* Test IRQ (0-1) and FIQ (8-9) mask bits.
	469	*/
	470	if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
	471	continue;
	472
	473	if (irqn == 1) {
	474	armada_370_xp_handle_msi_irq(NULL, true);
	475	continue;
	476	}
	477
bc69b8ad EG	478	cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
	479	generic_handle_irq(cascade_irq);
	480	}
	481
	482	chained_irq_exit(chip, desc);
	483	}
	484
8783dd3a	485	static void __exception_irq_entry
9339d432	486	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	487	{
	488	u32 irqstat, irqnr;
	489
	490	do {
	491	irqstat = readl_relaxed(per_cpu_int_base +
	492	ARMADA_370_XP_CPU_INTACK_OFFS);
	493	irqnr = irqstat & 0x3FF;
	494
344e873e GC	495	if (irqnr > 1022)
	496	break;
	497
31f614ed	498	if (irqnr > 1) {
e89c6a06 MZ	499	handle_domain_irq(armada_370_xp_mpic_domain,
e89c6a06 MZ	500	irqnr, regs);
9ae6f740 TP	501	continue;
9ae6f740 TP	502	}
31f614ed	503
31f614ed	504	/* MSI handling */
9b8cf779	505	if (irqnr == 1)
bc69b8ad	506	armada_370_xp_handle_msi_irq(regs, false);
31f614ed	507
344e873e GC	508	#ifdef CONFIG_SMP
	509	/* IPI Handling */
	510	if (irqnr == 0) {
	511	u32 ipimask, ipinr;
	512
	513	ipimask = readl_relaxed(per_cpu_int_base +
	514	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	515	& IPI_DOORBELL_MASK;
344e873e	516
a6f089e9	517	writel(~ipimask, per_cpu_int_base +
344e873e GC	518	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	519
	520	/* Handle all pending doorbells */
5ec69017 TP	521	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	522	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	523	if (ipimask & (0x1 << ipinr))
	524	handle_IPI(ipinr, regs);
	525	}
	526	continue;
	527	}
	528	#endif
9ae6f740	529
9ae6f740 TP	530	} while (1);
	531	}
	532
0f077eb5 TP	533	static int armada_370_xp_mpic_suspend(void)
	534	{
	535	doorbell_mask_reg = readl(per_cpu_int_base +
	536	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	537	return 0;
	538	}
	539
	540	static void armada_370_xp_mpic_resume(void)
	541	{
	542	int nirqs;
	543	irq_hw_number_t irq;
	544
	545	/* Re-enable interrupts */
	546	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	547	for (irq = 0; irq < nirqs; irq++) {
	548	struct irq_data *data;
	549	int virq;
	550
	551	virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
	552	if (virq == 0)
	553	continue;
	554
	555	if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
	556	writel(irq, per_cpu_int_base +
	557	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	558	else
	559	writel(irq, main_int_base +
	560	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	561
	562	data = irq_get_irq_data(virq);
	563	if (!irqd_irq_disabled(data))
	564	armada_370_xp_irq_unmask(data);
	565	}
	566
	567	/* Reconfigure doorbells for IPIs and MSIs */
	568	writel(doorbell_mask_reg,
	569	per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	570	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
	571	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	572	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
	573	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	574	}
	575
	576	struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	577	.suspend = armada_370_xp_mpic_suspend,
	578	.resume = armada_370_xp_mpic_resume,
	579	};
	580
b313ada8 TP	581	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	582	struct device_node *parent)
9ae6f740	583	{
627dfcc2	584	struct resource main_int_res, per_cpu_int_res;
5724be84	585	int nr_irqs, i;
b313ada8 TP	586	u32 control;
b313ada8 TP	587
627dfcc2 TP	588	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	589	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	590
627dfcc2 TP	591	BUG_ON(!request_mem_region(main_int_res.start,
	592	resource_size(&main_int_res),
	593	node->full_name));
	594	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	595	resource_size(&per_cpu_int_res),
	596	node->full_name));
	597
	598	main_int_base = ioremap(main_int_res.start,
	599	resource_size(&main_int_res));
b313ada8	600	BUG_ON(!main_int_base);
627dfcc2 TP	601
	602	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	603	resource_size(&per_cpu_int_res));
b313ada8 TP	604	BUG_ON(!per_cpu_int_base);
	605
	606	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
b73842b7 TP	607	nr_irqs = (control >> 2) & 0x3ff;
	608
	609	for (i = 0; i < nr_irqs; i++)
	610	writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
b313ada8 TP	611
b313ada8 TP	612	armada_370_xp_mpic_domain =
b73842b7	613	irq_domain_add_linear(node, nr_irqs,
b313ada8 TP	614	&armada_370_xp_mpic_irq_ops, NULL);
b313ada8 TP	615
627dfcc2	616	BUG_ON(!armada_370_xp_mpic_domain);
b313ada8	617
933a24b0	618	/* Setup for the boot CPU */
28da06df	619	armada_xp_mpic_perf_init();
b313ada8	620	armada_xp_mpic_smp_cpu_init();
b313ada8	621
31f614ed TP	622	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	623
bc69b8ad EG	624	parent_irq = irq_of_parse_and_map(node, 0);
	625	if (parent_irq <= 0) {
	626	irq_set_default_host(armada_370_xp_mpic_domain);
	627	set_handle_irq(armada_370_xp_handle_irq);
ef37d337 TP	628	#ifdef CONFIG_SMP
ef37d337 TP	629	set_smp_cross_call(armada_mpic_send_doorbell);
d7df84b3	630	register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
ef37d337	631	#endif
bc69b8ad	632	} else {
5724be84 MR	633	#ifdef CONFIG_SMP
	634	register_cpu_notifier(&mpic_cascaded_cpu_notifier);
	635	#endif
bc69b8ad EG	636	irq_set_chained_handler(parent_irq,
	637	armada_370_xp_mpic_handle_cascade_irq);
	638	}
b313ada8	639
0f077eb5 TP	640	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
0f077eb5 TP	641
b313ada8	642	return 0;
9ae6f740	643	}
b313ada8	644
9339d432	645	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);