[linux-2.6-block.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS	(0x54)
#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
#define ARMADA_375_PPI_CAUSE			(0x10)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
static u32 doorbell_mask_reg;
static int parent_irq;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

static inline bool is_percpu_irq(irq_hw_number_t irq)
{
	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
		return true;

	return false;
}

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (!is_percpu_irq(hwirq))
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static int armada_370_xp_alloc_msi(void)
{
	int hwirq;

	mutex_lock(&msi_used_lock);
	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	if (hwirq >= PCI_MSI_DOORBELL_NR)
		hwirq = -ENOSPC;
	else
		set_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);

	return hwirq;
}

static void armada_370_xp_free_msi(int hwirq)
{
	mutex_lock(&msi_used_lock);
	if (!test_bit(hwirq, msi_used))
		pr_err("trying to free unused MSI#%d\n", hwirq);
	else
		clear_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);
}

static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
				       struct pci_dev *pdev,
				       struct msi_desc *desc)
{
	struct msi_msg msg;
	int virq, hwirq;

	/* We support MSI, but not MSI-X */
	if (desc->msi_attrib.is_msix)
		return -EINVAL;

	hwirq = armada_370_xp_alloc_msi();
	if (hwirq < 0)
		return hwirq;

	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	if (!virq) {
		armada_370_xp_free_msi(hwirq);
		return -EINVAL;
	}

	irq_set_msi_desc(virq, desc);

	msg.address_lo = msi_doorbell_addr;
	msg.address_hi = 0;
	msg.data = 0xf00 | (hwirq + 16);

	pci_write_msi_msg(virq, &msg);
	return 0;
}

static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
					   unsigned int irq)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned long hwirq = d->hwirq;

	irq_dispose_mapping(irq);
	armada_370_xp_free_msi(hwirq);
}

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "armada_370_xp_msi_irq",
	.irq_enable = pci_msi_unmask_irq,
	.irq_disable = pci_msi_mask_irq,
	.irq_mask = pci_msi_mask_irq,
	.irq_unmask = pci_msi_unmask_irq,
};

static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
				 handle_simple_irq);

	return 0;
}

static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	.map = armada_370_xp_msi_map,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	struct msi_controller *msi_chip;
	u32 reg;
	int ret;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	if (!msi_chip)
		return -ENOMEM;

	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	msi_chip->of_node = node;

	armada_370_xp_msi_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_irq_ops,
				      NULL);
	if (!armada_370_xp_msi_domain) {
		kfree(msi_chip);
		return -ENOMEM;
	}

	ret = of_pci_msi_chip_add(msi_chip);
	if (ret < 0) {
		irq_domain_remove(armada_370_xp_msi_domain);
		kfree(msi_chip);
		return ret;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	unsigned long reg, mask;
	int cpu;

	/* Select a single core from the affinity mask which is online */
	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	mask = 1UL << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);
	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	raw_spin_unlock(&irq_controller_lock);

	return IRQ_SET_MASK_OK;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "armada_370_xp_irq",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (!is_percpu_irq(hw))
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (is_percpu_irq(hw)) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	irq_set_probe(virq);
	irq_clear_status_flags(virq, IRQ_NOAUTOEN);

	return 0;
}

static void armada_xp_mpic_smp_cpu_init(void)
{
	u32 control;
	int nr_irqs, i;

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);

	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

static void armada_xp_mpic_perf_init(void)
{
	unsigned long cpuid = cpu_logical_map(smp_processor_id());

	/* Enable Performance Counter Overflow interrupts */
	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	       per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
}

#ifdef CONFIG_SMP
static void armada_mpic_send_doorbell(const struct cpumask *mask,
				      unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
					 unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		armada_xp_mpic_smp_cpu_init();
	}

	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	.notifier_call = armada_xp_mpic_secondary_init,
	.priority = 100,
};

static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
					unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) {
		armada_xp_mpic_perf_init();
		enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
	}

	return NOTIFY_OK;
}

static struct notifier_block mpic_cascaded_cpu_notifier = {
	.notifier_call = mpic_cascaded_secondary_init,
	.priority = 100,
};
#endif /* CONFIG_SMP */

static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

#ifdef CONFIG_PCI_MSI
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
{
	u32 msimask, msinr;

	msimask = readl_relaxed(per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
		& PCI_MSI_DOORBELL_MASK;

	writel(~msimask, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	for (msinr = PCI_MSI_DOORBELL_START;
	     msinr < PCI_MSI_DOORBELL_END; msinr++) {
		int irq;

		if (!(msimask & BIT(msinr)))
			continue;

		if (is_chained) {
			irq = irq_find_mapping(armada_370_xp_msi_domain,
					       msinr - 16);
			generic_handle_irq(irq);
		} else {
			irq = msinr - 16;
			handle_domain_irq(armada_370_xp_msi_domain,
					  irq, regs);
		}
	}
}
#else
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
#endif

static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned long irqmap, irqn, irqsrc, cpuid;
	unsigned int cascade_irq;

	chained_irq_enter(chip, desc);

	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
	cpuid = cpu_logical_map(smp_processor_id());

	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
		irqsrc = readl_relaxed(main_int_base +
				       ARMADA_370_XP_INT_SOURCE_CTL(irqn));

		/* Check if the interrupt is not masked on current CPU.
		 * Test IRQ (0-1) and FIQ (8-9) mask bits.
		 */
		if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
			continue;

		if (irqn == 1) {
			armada_370_xp_handle_msi_irq(NULL, true);
			continue;
		}

		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
		generic_handle_irq(cascade_irq);
	}

	chained_irq_exit(chip, desc);
}

static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			handle_domain_irq(armada_370_xp_mpic_domain,
					  irqnr, regs);
			continue;
		}

		/* MSI handling */
		if (irqnr == 1)
			armada_370_xp_handle_msi_irq(regs, false);

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~ipimask, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int armada_370_xp_mpic_suspend(void)
{
	doorbell_mask_reg = readl(per_cpu_int_base +
				  ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	return 0;
}

static void armada_370_xp_mpic_resume(void)
{
	int nirqs;
	irq_hw_number_t irq;

	/* Re-enable interrupts */
	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	for (irq = 0; irq < nirqs; irq++) {
		struct irq_data *data;
		int virq;

		virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
		if (virq == 0)
			continue;

		if (!is_percpu_irq(irq))
			writel(irq, per_cpu_int_base +
			       ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
		else
			writel(irq, main_int_base +
			       ARMADA_370_XP_INT_SET_ENABLE_OFFS);

		data = irq_get_irq_data(virq);
		if (!irqd_irq_disabled(data))
			armada_370_xp_irq_unmask(data);
	}

	/* Reconfigure doorbells for IPIs and MSIs */
	writel(doorbell_mask_reg,
	       per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	.suspend	= armada_370_xp_mpic_suspend,
	.resume		= armada_370_xp_mpic_resume,
};

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	int nr_irqs, i;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, nr_irqs,
				&armada_370_xp_mpic_irq_ops, NULL);

	BUG_ON(!armada_370_xp_mpic_domain);

	/* Setup for the boot CPU */
	armada_xp_mpic_perf_init();
	armada_xp_mpic_smp_cpu_init();

	armada_370_xp_msi_init(node, main_int_res.start);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (parent_irq <= 0) {
		irq_set_default_host(armada_370_xp_mpic_domain);
		set_handle_irq(armada_370_xp_handle_irq);
#ifdef CONFIG_SMP
		set_smp_cross_call(armada_mpic_send_doorbell);
		register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
#endif
	} else {
#ifdef CONFIG_SMP
		register_cpu_notifier(&mpic_cascaded_cpu_notifier);
#endif
		irq_set_chained_handler(parent_irq,
					armada_370_xp_mpic_handle_cascade_irq);
	}

	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
41a83e06	21	#include <linux/irqchip.h>
bc69b8ad	22	#include <linux/irqchip/chained_irq.h>
d7df84b3	23	#include <linux/cpu.h>
9ae6f740 TP	24	#include <linux/io.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_irq.h>
31f614ed	27	#include <linux/of_pci.h>
9ae6f740	28	#include <linux/irqdomain.h>
31f614ed	29	#include <linux/slab.h>
0f077eb5	30	#include <linux/syscore_ops.h>
31f614ed	31	#include <linux/msi.h>
9ae6f740 TP	32	#include <asm/mach/arch.h>
9ae6f740 TP	33	#include <asm/exception.h>
344e873e	34	#include <asm/smp_plat.h>
9339d432 TP	35	#include <asm/mach/irq.h>
9339d432 TP	36
9ae6f740 TP	37	/* Interrupt Controller Registers Map */
	38	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	39	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
28da06df MR	40	#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
28da06df MR	41	#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
9ae6f740	42
f3e16ccd	43	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	44	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	45	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	46	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
8cc3cfc5	47	#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
758e8366	48	#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) \| BIT(8)) << cpuid)
9ae6f740 TP	49
9ae6f740 TP	50	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
bc69b8ad	51	#define ARMADA_375_PPI_CAUSE (0x10)
9ae6f740	52
344e873e GC	53	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	54	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	55	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	56
3202bf01 GC	57	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	58
5ec69017 TP	59	#define IPI_DOORBELL_START (0)
	60	#define IPI_DOORBELL_END (8)
	61	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	62	#define PCI_MSI_DOORBELL_START (16)
	63	#define PCI_MSI_DOORBELL_NR (16)
	64	#define PCI_MSI_DOORBELL_END (32)
	65	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	66
9ae6f740 TP	67	static void __iomem *per_cpu_int_base;
	68	static void __iomem *main_int_base;
	69	static struct irq_domain *armada_370_xp_mpic_domain;
0f077eb5	70	static u32 doorbell_mask_reg;
5724be84	71	static int parent_irq;
31f614ed TP	72	#ifdef CONFIG_PCI_MSI
	73	static struct irq_domain *armada_370_xp_msi_domain;
	74	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	75	static DEFINE_MUTEX(msi_used_lock);
	76	static phys_addr_t msi_doorbell_addr;
	77	#endif
9ae6f740	78
2c299de5 EG	79	static inline bool is_percpu_irq(irq_hw_number_t irq)
2c299de5 EG	80	{
080481f9	81	if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
2c299de5	82	return true;
080481f9 MR	83
080481f9 MR	84	return false;
2c299de5 EG	85	}
2c299de5 EG	86
3202bf01 GC	87	/*
	88	* In SMP mode:
	89	* For shared global interrupts, mask/unmask global enable bit
097ef18d	90	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	91	*/
9ae6f740 TP	92	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	93	{
3202bf01 GC	94	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	95
2c299de5	96	if (!is_percpu_irq(hwirq))
3202bf01 GC	97	writel(hwirq, main_int_base +
	98	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	99	else
	100	writel(hwirq, per_cpu_int_base +
	101	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	102	}
	103
	104	static void armada_370_xp_irq_unmask(struct irq_data *d)
	105	{
3202bf01 GC	106	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	107
2c299de5	108	if (!is_percpu_irq(hwirq))
3202bf01 GC	109	writel(hwirq, main_int_base +
	110	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	111	else
	112	writel(hwirq, per_cpu_int_base +
	113	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	114	}
9ae6f740 TP	115
31f614ed TP	116	#ifdef CONFIG_PCI_MSI
	117
	118	static int armada_370_xp_alloc_msi(void)
	119	{
	120	int hwirq;
	121
	122	mutex_lock(&msi_used_lock);
	123	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	124	if (hwirq >= PCI_MSI_DOORBELL_NR)
	125	hwirq = -ENOSPC;
	126	else
	127	set_bit(hwirq, msi_used);
	128	mutex_unlock(&msi_used_lock);
	129
	130	return hwirq;
	131	}
	132
	133	static void armada_370_xp_free_msi(int hwirq)
	134	{
	135	mutex_lock(&msi_used_lock);
	136	if (!test_bit(hwirq, msi_used))
	137	pr_err("trying to free unused MSI#%d\n", hwirq);
	138	else
	139	clear_bit(hwirq, msi_used);
	140	mutex_unlock(&msi_used_lock);
	141	}
	142
c2791b80	143	static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
31f614ed TP	144	struct pci_dev *pdev,
	145	struct msi_desc *desc)
	146	{
	147	struct msi_msg msg;
da343fc7	148	int virq, hwirq;
31f614ed	149
3930115e AG	150	/* We support MSI, but not MSI-X */
	151	if (desc->msi_attrib.is_msix)
	152	return -EINVAL;
	153
31f614ed TP	154	hwirq = armada_370_xp_alloc_msi();
	155	if (hwirq < 0)
	156	return hwirq;
	157
	158	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	159	if (!virq) {
	160	armada_370_xp_free_msi(hwirq);
	161	return -EINVAL;
	162	}
	163
	164	irq_set_msi_desc(virq, desc);
	165
	166	msg.address_lo = msi_doorbell_addr;
	167	msg.address_hi = 0;
	168	msg.data = 0xf00 \| (hwirq + 16);
	169
83a18912	170	pci_write_msi_msg(virq, &msg);
31f614ed TP	171	return 0;
	172	}
	173
c2791b80	174	static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
31f614ed TP	175	unsigned int irq)
	176	{
	177	struct irq_data *d = irq_get_irq_data(irq);
ff3c6645 NG	178	unsigned long hwirq = d->hwirq;
ff3c6645 NG	179
31f614ed	180	irq_dispose_mapping(irq);
ff3c6645	181	armada_370_xp_free_msi(hwirq);
31f614ed TP	182	}
	183
	184	static struct irq_chip armada_370_xp_msi_irq_chip = {
	185	.name = "armada_370_xp_msi_irq",
280510f1 TG	186	.irq_enable = pci_msi_unmask_irq,
	187	.irq_disable = pci_msi_mask_irq,
	188	.irq_mask = pci_msi_mask_irq,
	189	.irq_unmask = pci_msi_unmask_irq,
31f614ed TP	190	};
	191
	192	static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
	193	irq_hw_number_t hw)
	194	{
	195	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
	196	handle_simple_irq);
31f614ed TP	197
	198	return 0;
	199	}
	200
	201	static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	202	.map = armada_370_xp_msi_map,
	203	};
	204
	205	static int armada_370_xp_msi_init(struct device_node *node,
	206	phys_addr_t main_int_phys_base)
	207	{
c2791b80	208	struct msi_controller *msi_chip;
31f614ed TP	209	u32 reg;
	210	int ret;
	211
	212	msi_doorbell_addr = main_int_phys_base +
	213	ARMADA_370_XP_SW_TRIG_INT_OFFS;
	214
	215	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	216	if (!msi_chip)
	217	return -ENOMEM;
	218
	219	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	220	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	221	msi_chip->of_node = node;
	222
	223	armada_370_xp_msi_domain =
	224	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
	225	&armada_370_xp_msi_irq_ops,
	226	NULL);
	227	if (!armada_370_xp_msi_domain) {
	228	kfree(msi_chip);
	229	return -ENOMEM;
	230	}
	231
	232	ret = of_pci_msi_chip_add(msi_chip);
	233	if (ret < 0) {
	234	irq_domain_remove(armada_370_xp_msi_domain);
	235	kfree(msi_chip);
	236	return ret;
	237	}
	238
	239	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
	240	\| PCI_MSI_DOORBELL_MASK;
	241
	242	writel(reg, per_cpu_int_base +
	243	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	244
	245	/* Unmask IPI interrupt */
	246	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	247
	248	return 0;
	249	}
	250	#else
	251	static inline int armada_370_xp_msi_init(struct device_node *node,
	252	phys_addr_t main_int_phys_base)
	253	{
	254	return 0;
	255	}
	256	#endif
	257
344e873e	258	#ifdef CONFIG_SMP
19e61d41 AE	259	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
19e61d41 AE	260
344e873e GC	261	static int armada_xp_set_affinity(struct irq_data *d,
	262	const struct cpumask *mask_val, bool force)
	263	{
3202bf01	264	irq_hw_number_t hwirq = irqd_to_hwirq(d);
8cc3cfc5	265	unsigned long reg, mask;
3202bf01 GC	266	int cpu;
3202bf01 GC	267
8cc3cfc5 TG	268	/* Select a single core from the affinity mask which is online */
	269	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	270	mask = 1UL << cpu_logical_map(cpu);
3202bf01 GC	271
3202bf01 GC	272	raw_spin_lock(&irq_controller_lock);
3202bf01	273	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
8cc3cfc5	274	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) \| mask;
3202bf01	275	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
3202bf01 GC	276	raw_spin_unlock(&irq_controller_lock);
3202bf01 GC	277
1dacf194	278	return IRQ_SET_MASK_OK;
344e873e GC	279	}
	280	#endif
	281
9ae6f740 TP	282	static struct irq_chip armada_370_xp_irq_chip = {
	283	.name = "armada_370_xp_irq",
	284	.irq_mask = armada_370_xp_irq_mask,
	285	.irq_mask_ack = armada_370_xp_irq_mask,
	286	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	287	#ifdef CONFIG_SMP
	288	.irq_set_affinity = armada_xp_set_affinity,
	289	#endif
0d8e1d80	290	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
9ae6f740 TP	291	};
	292
	293	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	294	unsigned int virq, irq_hw_number_t hw)
	295	{
	296	armada_370_xp_irq_mask(irq_get_irq_data(virq));
2c299de5	297	if (!is_percpu_irq(hw))
600468d0 GC	298	writel(hw, per_cpu_int_base +
	299	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	300	else
	301	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	302	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	303
2c299de5	304	if (is_percpu_irq(hw)) {
3a6f08a3 GC	305	irq_set_percpu_devid(virq);
	306	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	307	handle_percpu_devid_irq);
	308
	309	} else {
	310	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	311	handle_level_irq);
	312	}
d17cab44	313	irq_set_probe(virq);
353d6d6c	314	irq_clear_status_flags(virq, IRQ_NOAUTOEN);
9ae6f740 TP	315
	316	return 0;
	317	}
	318
d7df84b3	319	static void armada_xp_mpic_smp_cpu_init(void)
344e873e	320	{
b73842b7 TP	321	u32 control;
	322	int nr_irqs, i;
	323
	324	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	325	nr_irqs = (control >> 2) & 0x3ff;
	326
	327	for (i = 0; i < nr_irqs; i++)
	328	writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
	329
344e873e GC	330	/* Clear pending IPIs */
	331	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	332
	333	/* Enable first 8 IPIs */
5ec69017	334	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	335	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	336
	337	/* Unmask IPI interrupt */
	338	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	339	}
d7df84b3	340
28da06df MR	341	static void armada_xp_mpic_perf_init(void)
	342	{
	343	unsigned long cpuid = cpu_logical_map(smp_processor_id());
	344
	345	/* Enable Performance Counter Overflow interrupts */
	346	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
	347	per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
	348	}
	349
933a24b0 EG	350	#ifdef CONFIG_SMP
	351	static void armada_mpic_send_doorbell(const struct cpumask *mask,
	352	unsigned int irq)
	353	{
	354	int cpu;
	355	unsigned long map = 0;
	356
	357	/* Convert our logical CPU mask into a physical one. */
	358	for_each_cpu(cpu, mask)
	359	map \|= 1 << cpu_logical_map(cpu);
	360
	361	/*
	362	* Ensure that stores to Normal memory are visible to the
	363	* other CPUs before issuing the IPI.
	364	*/
	365	dsb();
	366
	367	/* submit softirq */
	368	writel((map << 8) \| irq, main_int_base +
	369	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	370	}
	371
d7df84b3 TP	372	static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
	373	unsigned long action, void *hcpu)
	374	{
28da06df MR	375	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	376	armada_xp_mpic_perf_init();
d7df84b3	377	armada_xp_mpic_smp_cpu_init();
28da06df	378	}
5724be84	379
d7df84b3 TP	380	return NOTIFY_OK;
	381	}
	382
	383	static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	384	.notifier_call = armada_xp_mpic_secondary_init,
	385	.priority = 100,
	386	};
	387
5724be84 MR	388	static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
	389	unsigned long action, void *hcpu)
	390	{
28da06df MR	391	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN) {
28da06df MR	392	armada_xp_mpic_perf_init();
5724be84	393	enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
28da06df	394	}
5724be84 MR	395
	396	return NOTIFY_OK;
	397	}
	398
	399	static struct notifier_block mpic_cascaded_cpu_notifier = {
	400	.notifier_call = mpic_cascaded_secondary_init,
	401	.priority = 100,
	402	};
344e873e GC	403	#endif /* CONFIG_SMP */
344e873e GC	404
96009736	405	static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
9ae6f740 TP	406	.map = armada_370_xp_mpic_irq_map,
	407	.xlate = irq_domain_xlate_onecell,
	408	};
	409
9b8cf779	410	#ifdef CONFIG_PCI_MSI
bc69b8ad	411	static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
9b8cf779 EG	412	{
	413	u32 msimask, msinr;
	414
	415	msimask = readl_relaxed(per_cpu_int_base +
	416	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	417	& PCI_MSI_DOORBELL_MASK;
	418
	419	writel(~msimask, per_cpu_int_base +
	420	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	421
	422	for (msinr = PCI_MSI_DOORBELL_START;
	423	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	424	int irq;
	425
	426	if (!(msimask & BIT(msinr)))
	427	continue;
	428
e89c6a06 MZ	429	if (is_chained) {
	430	irq = irq_find_mapping(armada_370_xp_msi_domain,
	431	msinr - 16);
bc69b8ad	432	generic_handle_irq(irq);
e89c6a06 MZ	433	} else {
	434	irq = msinr - 16;
	435	handle_domain_irq(armada_370_xp_msi_domain,
	436	irq, regs);
	437	}
9b8cf779 EG	438	}
	439	}
	440	#else
bc69b8ad	441	static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
9b8cf779 EG	442	#endif
9b8cf779 EG	443
bd0b9ac4	444	static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
bc69b8ad	445	{
5b29264c	446	struct irq_chip *chip = irq_desc_get_chip(desc);
758e8366	447	unsigned long irqmap, irqn, irqsrc, cpuid;
bc69b8ad EG	448	unsigned int cascade_irq;
	449
	450	chained_irq_enter(chip, desc);
	451
	452	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
758e8366	453	cpuid = cpu_logical_map(smp_processor_id());
bc69b8ad EG	454
bc69b8ad EG	455	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
758e8366 GJ	456	irqsrc = readl_relaxed(main_int_base +
	457	ARMADA_370_XP_INT_SOURCE_CTL(irqn));
	458
	459	/* Check if the interrupt is not masked on current CPU.
	460	* Test IRQ (0-1) and FIQ (8-9) mask bits.
	461	*/
	462	if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
	463	continue;
	464
	465	if (irqn == 1) {
	466	armada_370_xp_handle_msi_irq(NULL, true);
	467	continue;
	468	}
	469
bc69b8ad EG	470	cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
	471	generic_handle_irq(cascade_irq);
	472	}
	473
	474	chained_irq_exit(chip, desc);
	475	}
	476
8783dd3a	477	static void __exception_irq_entry
9339d432	478	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	479	{
	480	u32 irqstat, irqnr;
	481
	482	do {
	483	irqstat = readl_relaxed(per_cpu_int_base +
	484	ARMADA_370_XP_CPU_INTACK_OFFS);
	485	irqnr = irqstat & 0x3FF;
	486
344e873e GC	487	if (irqnr > 1022)
	488	break;
	489
31f614ed	490	if (irqnr > 1) {
e89c6a06 MZ	491	handle_domain_irq(armada_370_xp_mpic_domain,
e89c6a06 MZ	492	irqnr, regs);
9ae6f740 TP	493	continue;
9ae6f740 TP	494	}
31f614ed	495
31f614ed	496	/* MSI handling */
9b8cf779	497	if (irqnr == 1)
bc69b8ad	498	armada_370_xp_handle_msi_irq(regs, false);
31f614ed	499
344e873e GC	500	#ifdef CONFIG_SMP
	501	/* IPI Handling */
	502	if (irqnr == 0) {
	503	u32 ipimask, ipinr;
	504
	505	ipimask = readl_relaxed(per_cpu_int_base +
	506	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	507	& IPI_DOORBELL_MASK;
344e873e	508
a6f089e9	509	writel(~ipimask, per_cpu_int_base +
344e873e GC	510	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	511
	512	/* Handle all pending doorbells */
5ec69017 TP	513	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	514	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	515	if (ipimask & (0x1 << ipinr))
	516	handle_IPI(ipinr, regs);
	517	}
	518	continue;
	519	}
	520	#endif
9ae6f740	521
9ae6f740 TP	522	} while (1);
	523	}
	524
0f077eb5 TP	525	static int armada_370_xp_mpic_suspend(void)
	526	{
	527	doorbell_mask_reg = readl(per_cpu_int_base +
	528	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	529	return 0;
	530	}
	531
	532	static void armada_370_xp_mpic_resume(void)
	533	{
	534	int nirqs;
	535	irq_hw_number_t irq;
	536
	537	/* Re-enable interrupts */
	538	nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
	539	for (irq = 0; irq < nirqs; irq++) {
	540	struct irq_data *data;
	541	int virq;
	542
	543	virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
	544	if (virq == 0)
	545	continue;
	546
080481f9	547	if (!is_percpu_irq(irq))
0f077eb5 TP	548	writel(irq, per_cpu_int_base +
	549	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	550	else
	551	writel(irq, main_int_base +
	552	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	553
	554	data = irq_get_irq_data(virq);
	555	if (!irqd_irq_disabled(data))
	556	armada_370_xp_irq_unmask(data);
	557	}
	558
	559	/* Reconfigure doorbells for IPIs and MSIs */
	560	writel(doorbell_mask_reg,
	561	per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	562	if (doorbell_mask_reg & IPI_DOORBELL_MASK)
	563	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	564	if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
	565	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	566	}
	567
	568	struct syscore_ops armada_370_xp_mpic_syscore_ops = {
	569	.suspend = armada_370_xp_mpic_suspend,
	570	.resume = armada_370_xp_mpic_resume,
	571	};
	572
b313ada8 TP	573	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	574	struct device_node *parent)
9ae6f740	575	{
627dfcc2	576	struct resource main_int_res, per_cpu_int_res;
5724be84	577	int nr_irqs, i;
b313ada8 TP	578	u32 control;
b313ada8 TP	579
627dfcc2 TP	580	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	581	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	582
627dfcc2 TP	583	BUG_ON(!request_mem_region(main_int_res.start,
	584	resource_size(&main_int_res),
	585	node->full_name));
	586	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	587	resource_size(&per_cpu_int_res),
	588	node->full_name));
	589
	590	main_int_base = ioremap(main_int_res.start,
	591	resource_size(&main_int_res));
b313ada8	592	BUG_ON(!main_int_base);
627dfcc2 TP	593
	594	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	595	resource_size(&per_cpu_int_res));
b313ada8 TP	596	BUG_ON(!per_cpu_int_base);
	597
	598	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
b73842b7 TP	599	nr_irqs = (control >> 2) & 0x3ff;
	600
	601	for (i = 0; i < nr_irqs; i++)
	602	writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
b313ada8 TP	603
b313ada8 TP	604	armada_370_xp_mpic_domain =
b73842b7	605	irq_domain_add_linear(node, nr_irqs,
b313ada8 TP	606	&armada_370_xp_mpic_irq_ops, NULL);
b313ada8 TP	607
627dfcc2	608	BUG_ON(!armada_370_xp_mpic_domain);
b313ada8	609
933a24b0	610	/* Setup for the boot CPU */
28da06df	611	armada_xp_mpic_perf_init();
b313ada8	612	armada_xp_mpic_smp_cpu_init();
b313ada8	613
31f614ed TP	614	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	615
bc69b8ad EG	616	parent_irq = irq_of_parse_and_map(node, 0);
	617	if (parent_irq <= 0) {
	618	irq_set_default_host(armada_370_xp_mpic_domain);
	619	set_handle_irq(armada_370_xp_handle_irq);
ef37d337 TP	620	#ifdef CONFIG_SMP
ef37d337 TP	621	set_smp_cross_call(armada_mpic_send_doorbell);
d7df84b3	622	register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
ef37d337	623	#endif
bc69b8ad	624	} else {
5724be84 MR	625	#ifdef CONFIG_SMP
	626	register_cpu_notifier(&mpic_cascaded_cpu_notifier);
	627	#endif
bc69b8ad EG	628	irq_set_chained_handler(parent_irq,
	629	armada_370_xp_mpic_handle_cascade_irq);
	630	}
b313ada8	631
0f077eb5 TP	632	register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
0f077eb5 TP	633
b313ada8	634	return 0;
9ae6f740	635	}
b313ada8	636
9339d432	637	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);