Merge tag 'asoc-fix-v5.19-rc0' of https://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / irqchip / Kconfig
CommitLineData
ec8f24b7 1# SPDX-License-Identifier: GPL-2.0-only
c94fb639
RD
2menu "IRQ chip support"
3
f6e916b8
TP
4config IRQCHIP
5 def_bool y
6 depends on OF_IRQ
7
81243e44
RH
8config ARM_GIC
9 bool
9a1091ef 10 select IRQ_DOMAIN_HIERARCHY
0c9e4982 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44 12
9c8edddf
JH
13config ARM_GIC_PM
14 bool
15 depends on PM
16 select ARM_GIC
9c8edddf 17
a27d21e0
LW
18config ARM_GIC_MAX_NR
19 int
70265523 20 depends on ARM_GIC
a27d21e0
LW
21 default 2 if ARCH_REALVIEW
22 default 1
23
853a33ce
SS
24config ARM_GIC_V2M
25 bool
3ee80364
AB
26 depends on PCI
27 select ARM_GIC
28 select PCI_MSI
853a33ce 29
81243e44
RH
30config GIC_NON_BANKED
31 bool
32
021f6537
MZ
33config ARM_GIC_V3
34 bool
443acc4f 35 select IRQ_DOMAIN_HIERARCHY
e3825ba1 36 select PARTITION_PERCPU
956ae91a 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537 38
19812729
MZ
39config ARM_GIC_V3_ITS
40 bool
29f41139
MZ
41 select GENERIC_MSI_IRQ_DOMAIN
42 default ARM_GIC_V3
43
44config ARM_GIC_V3_ITS_PCI
45 bool
46 depends on ARM_GIC_V3_ITS
3ee80364
AB
47 depends on PCI
48 depends on PCI_MSI
29f41139 49 default ARM_GIC_V3_ITS
021f6537 50
7afe031c
BP
51config ARM_GIC_V3_ITS_FSL_MC
52 bool
53 depends on ARM_GIC_V3_ITS
54 depends on FSL_MC_BUS
55 default ARM_GIC_V3_ITS
56
292ec080
UKK
57config ARM_NVIC
58 bool
2d9f59f7 59 select IRQ_DOMAIN_HIERARCHY
292ec080
UKK
60 select GENERIC_IRQ_CHIP
61
44430ec0
RH
62config ARM_VIC
63 bool
64 select IRQ_DOMAIN
44430ec0
RH
65
66config ARM_VIC_NR
67 int
68 default 4 if ARCH_S5PV210
44430ec0
RH
69 default 2
70 depends on ARM_VIC
71 help
72 The maximum number of VICs available in the system, for
73 power management.
74
fed6d336
TP
75config ARMADA_370_XP_IRQ
76 bool
fed6d336 77 select GENERIC_IRQ_CHIP
3ee80364 78 select PCI_MSI if PCI
e31793a3 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336 80
e6b78f2c
AT
81config ALPINE_MSI
82 bool
3ee80364
AB
83 depends on PCI
84 select PCI_MSI
e6b78f2c 85 select GENERIC_IRQ_CHIP
e6b78f2c 86
1eb77c3b
TS
87config AL_FIC
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
91 select IRQ_DOMAIN
92 help
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
94
b1479ebb
BB
95config ATMEL_AIC_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
b1479ebb
BB
99 select SPARSE_IRQ
100
101config ATMEL_AIC5_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
b1479ebb
BB
105 select SPARSE_IRQ
106
0509cfde
RB
107config I8259
108 bool
109 select IRQ_DOMAIN
110
c7c42ec2
SA
111config BCM6345_L1_IRQ
112 bool
113 select GENERIC_IRQ_CHIP
114 select IRQ_DOMAIN
d0ed5e8e 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2 116
5f7f0317 117config BCM7038_L1_IRQ
c057c799
FF
118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
119 depends on ARCH_BRCMSTB || BMIPS_GENERIC
120 default ARCH_BRCMSTB || BMIPS_GENERIC
5f7f0317
KC
121 select GENERIC_IRQ_CHIP
122 select IRQ_DOMAIN
b8d9884a 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317 124
a4fcbb86 125config BCM7120_L2_IRQ
3ac268d5
FF
126 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
127 depends on ARCH_BRCMSTB || BMIPS_GENERIC
128 default ARCH_BRCMSTB || BMIPS_GENERIC
a4fcbb86
KC
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
7f646e92 132config BRCMSTB_L2_IRQ
51d9db5c
FF
133 tristate "Broadcom STB generic L2 interrupt controller driver"
134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
7f646e92
FF
136 select GENERIC_IRQ_CHIP
137 select IRQ_DOMAIN
138
0145beed
BG
139config DAVINCI_AINTC
140 bool
141 select GENERIC_IRQ_CHIP
142 select IRQ_DOMAIN
143
0fc3d74c
BG
144config DAVINCI_CP_INTC
145 bool
146 select GENERIC_IRQ_CHIP
147 select IRQ_DOMAIN
148
350d71b9
SH
149config DW_APB_ICTL
150 bool
e1588490 151 select GENERIC_IRQ_CHIP
54a38440 152 select IRQ_DOMAIN_HIERARCHY
350d71b9 153
6ee532e2
LW
154config FARADAY_FTINTC010
155 bool
156 select IRQ_DOMAIN
6ee532e2
LW
157 select SPARSE_IRQ
158
9a7c4abd
M
159config HISILICON_IRQ_MBIGEN
160 bool
161 select ARM_GIC_V3
162 select ARM_GIC_V3_ITS
9a7c4abd 163
b6ef9161
JH
164config IMGPDC_IRQ
165 bool
166 select GENERIC_IRQ_CHIP
167 select IRQ_DOMAIN
168
5b978c10
LW
169config IXP4XX_IRQ
170 bool
171 select IRQ_DOMAIN
5b978c10
LW
172 select SPARSE_IRQ
173
da0abe1a
RF
174config MADERA_IRQ
175 tristate
176
67e38cf2
RB
177config IRQ_MIPS_CPU
178 bool
179 select GENERIC_IRQ_CHIP
3838a547 180 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2 181 select IRQ_DOMAIN
18416e45 182 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2 183
afc98d90
AS
184config CLPS711X_IRQCHIP
185 bool
186 depends on ARCH_CLPS711X
187 select IRQ_DOMAIN
afc98d90
AS
188 select SPARSE_IRQ
189 default y
190
9b54470a
SH
191config OMPIC
192 bool
193
4db8e6d2
SK
194config OR1K_PIC
195 bool
196 select IRQ_DOMAIN
197
8598066c
FB
198config OMAP_IRQCHIP
199 bool
200 select GENERIC_IRQ_CHIP
201 select IRQ_DOMAIN
202
9dbd90f1
SH
203config ORION_IRQCHIP
204 bool
205 select IRQ_DOMAIN
9dbd90f1 206
aaa8666a
CB
207config PIC32_EVIC
208 bool
209 select GENERIC_IRQ_CHIP
210 select IRQ_DOMAIN
211
981b58f6 212config JCORE_AIC
3602ffde
RF
213 bool "J-Core integrated AIC" if COMPILE_TEST
214 depends on OF
981b58f6
RF
215 select IRQ_DOMAIN
216 help
217 Support for the J-Core integrated AIC.
218
d852e62a
MS
219config RDA_INTC
220 bool
221 select IRQ_DOMAIN
222
44358048 223config RENESAS_INTC_IRQPIN
02d7e041 224 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
44358048 225 select IRQ_DOMAIN
02d7e041
GU
226 help
227 Enable support for the Renesas Interrupt Controller for external
228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
44358048 229
fbc83b7f 230config RENESAS_IRQC
72d44c0c 231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
99c221df 232 select GENERIC_IRQ_CHIP
fbc83b7f 233 select IRQ_DOMAIN
02d7e041
GU
234 help
235 Enable support for the Renesas Interrupt Controller for external
72d44c0c 236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
fbc83b7f 237
a644ccb8 238config RENESAS_RZA1_IRQC
02d7e041 239 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
a644ccb8 240 select IRQ_DOMAIN_HIERARCHY
02d7e041
GU
241 help
242 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
243 to 8 external interrupts with configurable sense select.
a644ccb8 244
03ac990e
MW
245config SL28CPLD_INTC
246 bool "Kontron sl28cpld IRQ controller"
247 depends on MFD_SL28CPLD=y || COMPILE_TEST
248 select REGMAP_IRQ
249 help
250 Interrupt controller driver for the board management controller
251 found on the Kontron sl28 CPLD.
252
07088484
LJ
253config ST_IRQCHIP
254 bool
255 select REGMAP
256 select MFD_SYSCON
257 help
258 Enables SysCfg Controlled IRQs on STi based platforms.
259
b06eb017
CR
260config TB10X_IRQC
261 bool
262 select IRQ_DOMAIN
263 select GENERIC_IRQ_CHIP
264
d01f8633
DR
265config TS4800_IRQ
266 tristate "TS-4800 IRQ controller"
267 select IRQ_DOMAIN
0df337cf 268 depends on HAS_IOMEM
d2b383dc 269 depends on SOC_IMX51 || COMPILE_TEST
d01f8633
DR
270 help
271 Support for the TS-4800 FPGA IRQ controller
272
2389d501
LW
273config VERSATILE_FPGA_IRQ
274 bool
275 select IRQ_DOMAIN
276
277config VERSATILE_FPGA_IRQ_NR
278 int
279 default 4
280 depends on VERSATILE_FPGA_IRQ
26a8e96a
MF
281
282config XTENSA_MX
283 bool
284 select IRQ_DOMAIN
50091212 285 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e 286
0547dc78 287config XILINX_INTC
debf69cf
RH
288 bool "Xilinx Interrupt Controller IP"
289 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
0547dc78 290 select IRQ_DOMAIN
debf69cf
RH
291 help
292 Support for the Xilinx Interrupt Controller IP core.
293 This is used as a primary controller with MicroBlaze and can also
294 be used as a secondary chained controller on other platforms.
0547dc78 295
96ca848e
S
296config IRQ_CROSSBAR
297 bool
298 help
f54619f2 299 Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e
S
300 The primary irqchip invokes the crossbar's callback which inturn allocates
301 a free irq and configures the IP. Thus the peripheral interrupts are
302 routed to one of the free irqchip interrupt lines.
89323f8c
GS
303
304config KEYSTONE_IRQ
305 tristate "Keystone 2 IRQ controller IP"
306 depends on ARCH_KEYSTONE
307 help
308 Support for Texas Instruments Keystone 2 IRQ controller IP which
309 is part of the Keystone 2 IPC mechanism
8a19b8f1
AB
310
311config MIPS_GIC
312 bool
bb11cff3 313 select GENERIC_IRQ_IPI
8a19b8f1 314 select MIPS_CM
8a764482 315
44e08e70
PB
316config INGENIC_IRQ
317 bool
318 depends on MACH_INGENIC
319 default y
78c10e55 320
9536eba0
PC
321config INGENIC_TCU_IRQ
322 bool "Ingenic JZ47xx TCU interrupt controller"
323 default MACH_INGENIC
324 depends on MIPS || COMPILE_TEST
325 select MFD_SYSCON
8084499b 326 select GENERIC_IRQ_CHIP
9536eba0
PC
327 help
328 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
329 JZ47xx SoCs.
330
331 If unsure, say N.
332
8a764482
YS
333config RENESAS_H8300H_INTC
334 bool
335 select IRQ_DOMAIN
336
337config RENESAS_H8S_INTC
02d7e041 338 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
78c10e55 339 select IRQ_DOMAIN
02d7e041
GU
340 help
341 Enable support for the Renesas H8/300 Interrupt Controller, as found
342 on Renesas H8S SoCs.
e324c4dc
SW
343
344config IMX_GPCV2
345 bool
346 select IRQ_DOMAIN
347 help
348 Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676
OR
349
350config IRQ_MXS
351 def_bool y if MACH_ASM9260 || ARCH_MXS
352 select IRQ_DOMAIN
353 select STMP_DEVICE
c27f29bb 354
19d99164
AB
355config MSCC_OCELOT_IRQ
356 bool
357 select IRQ_DOMAIN
358 select GENERIC_IRQ_CHIP
359
a68a63cb
TP
360config MVEBU_GICP
361 bool
362
e0de91a9
TP
363config MVEBU_ICU
364 bool
365
c27f29bb
TP
366config MVEBU_ODMI
367 bool
fa23b9d1 368 select GENERIC_MSI_IRQ_DOMAIN
9e2c986c 369
a109893b
TP
370config MVEBU_PIC
371 bool
372
61ce8d8d
MR
373config MVEBU_SEI
374 bool
375
0dcd9f87
RV
376config LS_EXTIRQ
377 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
378 select MFD_SYSCON
379
b8f3ebe6
ML
380config LS_SCFG_MSI
381 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
382 depends on PCI && PCI_MSI
b8f3ebe6 383
9e2c986c
MZ
384config PARTITION_PERCPU
385 bool
0efacbba 386
e0720416
AT
387config STM32_EXTI
388 bool
389 select IRQ_DOMAIN
0e7d7807 390 select GENERIC_IRQ_CHIP
f20cc9b0
AVF
391
392config QCOM_IRQ_COMBINER
393 bool "QCOM IRQ combiner support"
394 depends on ARCH_QCOM && ACPI
f20cc9b0
AVF
395 select IRQ_DOMAIN_HIERARCHY
396 help
397 Say yes here to add support for the IRQ combiner devices embedded
398 in Qualcomm Technologies chips.
5ed34d3a
MY
399
400config IRQ_UNIPHIER_AIDET
401 bool "UniPhier AIDET support" if COMPILE_TEST
402 depends on ARCH_UNIPHIER || COMPILE_TEST
403 default ARCH_UNIPHIER
404 select IRQ_DOMAIN_HIERARCHY
405 help
406 Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639 407
215f4cc0 408config MESON_IRQ_GPIO
a947aa00
NA
409 tristate "Meson GPIO Interrupt Multiplexer"
410 depends on ARCH_MESON || COMPILE_TEST
411 default ARCH_MESON
215f4cc0
JB
412 select IRQ_DOMAIN_HIERARCHY
413 help
414 Support Meson SoC Family GPIO Interrupt Multiplexer
415
4235ff50
MD
416config GOLDFISH_PIC
417 bool "Goldfish programmable interrupt controller"
418 depends on MIPS && (GOLDFISH || COMPILE_TEST)
969ac78d 419 select GENERIC_IRQ_CHIP
4235ff50
MD
420 select IRQ_DOMAIN
421 help
422 Say yes here to enable Goldfish interrupt controller driver used
423 for Goldfish based virtual platforms.
424
f55c73ae 425config QCOM_PDC
4acd8a4b 426 tristate "QCOM PDC"
f55c73ae 427 depends on ARCH_QCOM
f55c73ae
AS
428 select IRQ_DOMAIN_HIERARCHY
429 help
430 Power Domain Controller driver to manage and configure wakeup
431 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
432
a6199bb5
SG
433config QCOM_MPM
434 tristate "QCOM MPM"
435 depends on ARCH_QCOM
fa4dcc88 436 depends on MAILBOX
a6199bb5
SG
437 select IRQ_DOMAIN_HIERARCHY
438 help
439 MSM Power Manager driver to manage and configure wakeup
440 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
441
d8a5f5f7 442config CSKY_MPINTC
be1abc5b 443 bool
d8a5f5f7
GR
444 depends on CSKY
445 help
446 Say yes here to enable C-SKY SMP interrupt controller driver used
447 for C-SKY SMP system.
656b42de 448 In fact it's not mmio map in hardware and it uses ld/st to visit the
d8a5f5f7
GR
449 controller's register inside CPU.
450
edff1b48
GR
451config CSKY_APB_INTC
452 bool "C-SKY APB Interrupt Controller"
453 depends on CSKY
454 help
455 Say yes here to enable C-SKY APB interrupt controller driver used
656b42de 456 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
edff1b48
GR
457 the controller's register.
458
0136afa0
LS
459config IMX_IRQSTEER
460 bool "i.MX IRQSTEER support"
461 depends on ARCH_MXC || COMPILE_TEST
462 default ARCH_MXC
463 select IRQ_DOMAIN
464 help
465 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
466
2fbb1396 467config IMX_INTMUX
a890caeb
GU
468 bool "i.MX INTMUX support" if COMPILE_TEST
469 default y if ARCH_MXC
2fbb1396
JZ
470 select IRQ_DOMAIN
471 help
472 Support for the i.MX INTMUX interrupt multiplexer.
473
9e543e22
JY
474config LS1X_IRQ
475 bool "Loongson-1 Interrupt Controller"
476 depends on MACH_LOONGSON32
477 default y
478 select IRQ_DOMAIN
479 select GENERIC_IRQ_CHIP
480 help
481 Support for the Loongson-1 platform Interrupt Controller.
482
cd844b07
LV
483config TI_SCI_INTR_IRQCHIP
484 bool
485 depends on TI_SCI_PROTOCOL
486 select IRQ_DOMAIN_HIERARCHY
487 help
488 This enables the irqchip driver support for K3 Interrupt router
489 over TI System Control Interface available on some new TI's SoCs.
490 If you wish to use interrupt router irq resources managed by the
491 TI System Controller, say Y here. Otherwise, say N.
492
9f1463b8
LV
493config TI_SCI_INTA_IRQCHIP
494 bool
495 depends on TI_SCI_PROTOCOL
496 select IRQ_DOMAIN_HIERARCHY
f011df61 497 select TI_SCI_INTA_MSI_DOMAIN
9f1463b8
LV
498 help
499 This enables the irqchip driver support for K3 Interrupt aggregator
500 over TI System Control Interface available on some new TI's SoCs.
501 If you wish to use interrupt aggregator irq resources managed by the
502 TI System Controller, say Y here. Otherwise, say N.
503
04e2d1e0 504config TI_PRUSS_INTC
b8e594fa
SA
505 tristate
506 depends on TI_PRUSS
507 default TI_PRUSS
04e2d1e0
GJ
508 select IRQ_DOMAIN
509 help
510 This enables support for the PRU-ICSS Local Interrupt Controller
511 present within a PRU-ICSS subsystem present on various TI SoCs.
512 The PRUSS INTC enables various interrupts to be routed to multiple
513 different processors within the SoC.
514
6b7ce892
AP
515config RISCV_INTC
516 bool "RISC-V Local Interrupt Controller"
517 depends on RISCV
518 default y
519 help
520 This enables support for the per-HART local interrupt controller
521 found in standard RISC-V systems. The per-HART local interrupt
522 controller handles timer interrupts, software interrupts, and
523 hardware interrupts. Without a per-HART local interrupt controller,
524 a RISC-V system will be unable to handle any interrupts.
525
526 If you don't know what to do here, say Y.
527
8237f8bc
CH
528config SIFIVE_PLIC
529 bool "SiFive Platform-Level Interrupt Controller"
530 depends on RISCV
466008f9 531 select IRQ_DOMAIN_HIERARCHY
8237f8bc
CH
532 help
533 This enables support for the PLIC chip found in SiFive (and
534 potentially other) RISC-V systems. The PLIC controls devices
535 interrupts and connects them to each core's local interrupt
536 controller. Aside from timer and software interrupts, all other
537 interrupt sources are subordinate to the PLIC.
538
539 If you don't know what to do here, say Y.
01493855 540
b74416db
HK
541config EXYNOS_IRQ_COMBINER
542 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
543 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
544 help
545 Say yes here to add support for the IRQ combiner devices embedded
546 in Samsung Exynos chips.
547
dbb15226
JY
548config LOONGSON_LIOINTC
549 bool "Loongson Local I/O Interrupt Controller"
550 depends on MACH_LOONGSON64
551 default y
552 select IRQ_DOMAIN
553 select GENERIC_IRQ_CHIP
554 help
555 Support for the Loongson Local I/O Interrupt Controller.
556
a93f1d90
JY
557config LOONGSON_HTPIC
558 bool "Loongson3 HyperTransport PIC Controller"
559 depends on MACH_LOONGSON64
560 default y
561 select IRQ_DOMAIN
562 select GENERIC_IRQ_CHIP
a93f1d90
JY
563 help
564 Support for the Loongson-3 HyperTransport PIC Controller.
565
818e915f
JY
566config LOONGSON_HTVEC
567 bool "Loongson3 HyperTransport Interrupt Vector Controller"
d77aeb5d 568 depends on MACH_LOONGSON64
818e915f
JY
569 default MACH_LOONGSON64
570 select IRQ_DOMAIN_HIERARCHY
571 help
572 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
573
ef8c01eb
JY
574config LOONGSON_PCH_PIC
575 bool "Loongson PCH PIC Controller"
576 depends on MACH_LOONGSON64 || COMPILE_TEST
577 default MACH_LOONGSON64
578 select IRQ_DOMAIN_HIERARCHY
579 select IRQ_FASTEOI_HIERARCHY_HANDLERS
580 help
581 Support for the Loongson PCH PIC Controller.
582
632dcc2c 583config LOONGSON_PCH_MSI
a23df9a4 584 bool "Loongson PCH MSI Controller"
632dcc2c
JY
585 depends on MACH_LOONGSON64 || COMPILE_TEST
586 depends on PCI
587 default MACH_LOONGSON64
588 select IRQ_DOMAIN_HIERARCHY
589 select PCI_MSI
590 help
591 Support for the Loongson PCH MSI Controller.
592
ad4c938c
MPT
593config MST_IRQ
594 bool "MStar Interrupt Controller"
61b0648d 595 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
ad4c938c
MPT
596 default ARCH_MEDIATEK
597 select IRQ_DOMAIN
598 select IRQ_DOMAIN_HIERARCHY
599 help
600 Support MStar Interrupt Controller.
601
fead4dd4
JN
602config WPCM450_AIC
603 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
94bc9420 604 depends on ARCH_WPCM450
fead4dd4
JN
605 help
606 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
607
529ea368
TB
608config IRQ_IDT3243X
609 bool
610 select GENERIC_IRQ_CHIP
611 select IRQ_DOMAIN
612
76cde263
HM
613config APPLE_AIC
614 bool "Apple Interrupt Controller (AIC)"
615 depends on ARM64
5b44955d 616 depends on ARCH_APPLE || COMPILE_TEST
76cde263
HM
617 help
618 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
619 such as the M1.
620
00fa3461
CB
621config MCHP_EIC
622 bool "Microchip External Interrupt Controller"
623 depends on ARCH_AT91 || COMPILE_TEST
624 select IRQ_DOMAIN
625 select IRQ_DOMAIN_HIERARCHY
626 help
627 Support for Microchip External Interrupt Controller.
628
01493855 629endmenu