[linux-2.6-block.git] / drivers / irqchip / Kconfig

# SPDX-License-Identifier: GPL-2.0-only
menu "IRQ chip support"

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_MULTI_HANDLER
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC

config ARM_GIC_MAX_NR
	int
	depends on ARM_GIC
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select GENERIC_IRQ_MULTI_HANDLER
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_V3_ITS
	bool
	select GENERIC_MSI_IRQ_DOMAIN
	default ARM_GIC_V3

config ARM_GIC_V3_ITS_PCI
	bool
	depends on ARM_GIC_V3_ITS
	depends on PCI
	depends on PCI_MSI
	default ARM_GIC_V3_ITS

config ARM_GIC_V3_ITS_FSL_MC
	bool
	depends on ARM_GIC_V3_ITS
	depends on FSL_MC_BUS
	default ARM_GIC_V3_ITS

config ARM_NVIC
	bool
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config AL_FIC
	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
	depends on OF || COMPILE_TEST
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	help
	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DAVINCI_AINTC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DAVINCI_CP_INTC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN_HIERARCHY

config FARADAY_FTINTC010
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER
	select SPARSE_IRQ

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IXP4XX_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER
	select SPARSE_IRQ

config MADERA_IRQ
	tristate

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER
	select SPARSE_IRQ
	default y

config OMPIC
	bool

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_MULTI_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC" if COMPILE_TEST
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RDA_INTC
	bool
	select IRQ_DOMAIN

config RENESAS_INTC_IRQPIN
	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
	select IRQ_DOMAIN
	help
	  Enable support for the Renesas Interrupt Controller for external
	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.

config RENESAS_IRQC
	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	help
	  Enable support for the Renesas Interrupt Controller for external
	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.

config RENESAS_RZA1_IRQC
	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
	select IRQ_DOMAIN_HIERARCHY
	help
	  Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
	  to 8 external interrupts with configurable sense select.

config SL28CPLD_INTC
	bool "Kontron sl28cpld IRQ controller"
	depends on MFD_SL28CPLD=y || COMPILE_TEST
	select REGMAP_IRQ
	help
	  Interrupt controller driver for the board management controller
	  found on the Kontron sl28 CPLD.

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config XILINX_INTC
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config INGENIC_TCU_IRQ
	bool "Ingenic JZ47xx TCU interrupt controller"
	default MACH_INGENIC
	depends on MIPS || COMPILE_TEST
	select MFD_SYSCON
	select GENERIC_IRQ_CHIP
	help
	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
	  JZ47xx SoCs.

	  If unsure, say N.

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
	bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
	select IRQ_DOMAIN
	help
	  Enable support for the Renesas H8/300 Interrupt Controller, as found
	  on Renesas H8S SoCs.

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MSCC_OCELOT_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config MVEBU_GICP
	bool

config MVEBU_ICU
	bool

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN

config MVEBU_PIC
	bool

config MVEBU_SEI
        bool

config LS_EXTIRQ
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	select MFD_SYSCON

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config EZNPS_GIC
	bool "NPS400 Global Interrupt Manager (GIM)"
	depends on ARC || (COMPILE_TEST && !64BIT)
	select IRQ_DOMAIN
	help
	  Support the EZchip NPS400 global interrupt controller

config STM32_EXTI
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config QCOM_IRQ_COMBINER
	bool "QCOM IRQ combiner support"
	depends on ARCH_QCOM && ACPI
	select IRQ_DOMAIN_HIERARCHY
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Qualcomm Technologies chips.

config IRQ_UNIPHIER_AIDET
	bool "UniPhier AIDET support" if COMPILE_TEST
	depends on ARCH_UNIPHIER || COMPILE_TEST
	default ARCH_UNIPHIER
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the UniPhier AIDET (ARM Interrupt Detector).

config MESON_IRQ_GPIO
       bool "Meson GPIO Interrupt Multiplexer"
       depends on ARCH_MESON
       select IRQ_DOMAIN_HIERARCHY
       help
         Support Meson SoC Family GPIO Interrupt Multiplexer

config GOLDFISH_PIC
       bool "Goldfish programmable interrupt controller"
       depends on MIPS && (GOLDFISH || COMPILE_TEST)
       select IRQ_DOMAIN
       help
         Say yes here to enable Goldfish interrupt controller driver used
         for Goldfish based virtual platforms.

config QCOM_PDC
	bool "QCOM PDC"
	depends on ARCH_QCOM
	select IRQ_DOMAIN_HIERARCHY
	help
	  Power Domain Controller driver to manage and configure wakeup
	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.

config CSKY_MPINTC
	bool "C-SKY Multi Processor Interrupt Controller"
	depends on CSKY
	help
	  Say yes here to enable C-SKY SMP interrupt controller driver used
	  for C-SKY SMP system.
	  In fact it's not mmio map in hardware and it uses ld/st to visit the
	  controller's register inside CPU.

config CSKY_APB_INTC
	bool "C-SKY APB Interrupt Controller"
	depends on CSKY
	help
	  Say yes here to enable C-SKY APB interrupt controller driver used
	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
	  the controller's register.

config IMX_IRQSTEER
	bool "i.MX IRQSTEER support"
	depends on ARCH_MXC || COMPILE_TEST
	default ARCH_MXC
	select IRQ_DOMAIN
	help
	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.

config IMX_INTMUX
	def_bool y if ARCH_MXC || COMPILE_TEST
	select IRQ_DOMAIN
	help
	  Support for the i.MX INTMUX interrupt multiplexer.

config LS1X_IRQ
	bool "Loongson-1 Interrupt Controller"
	depends on MACH_LOONGSON32
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson-1 platform Interrupt Controller.

config TI_SCI_INTR_IRQCHIP
	bool
	depends on TI_SCI_PROTOCOL
	select IRQ_DOMAIN_HIERARCHY
	help
	  This enables the irqchip driver support for K3 Interrupt router
	  over TI System Control Interface available on some new TI's SoCs.
	  If you wish to use interrupt router irq resources managed by the
	  TI System Controller, say Y here. Otherwise, say N.

config TI_SCI_INTA_IRQCHIP
	bool
	depends on TI_SCI_PROTOCOL
	select IRQ_DOMAIN_HIERARCHY
	select TI_SCI_INTA_MSI_DOMAIN
	help
	  This enables the irqchip driver support for K3 Interrupt aggregator
	  over TI System Control Interface available on some new TI's SoCs.
	  If you wish to use interrupt aggregator irq resources managed by the
	  TI System Controller, say Y here. Otherwise, say N.

config TI_PRUSS_INTC
	tristate "TI PRU-ICSS Interrupt Controller"
	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3
	select IRQ_DOMAIN
	help
	  This enables support for the PRU-ICSS Local Interrupt Controller
	  present within a PRU-ICSS subsystem present on various TI SoCs.
	  The PRUSS INTC enables various interrupts to be routed to multiple
	  different processors within the SoC.

config RISCV_INTC
	bool "RISC-V Local Interrupt Controller"
	depends on RISCV
	default y
	help
	   This enables support for the per-HART local interrupt controller
	   found in standard RISC-V systems.  The per-HART local interrupt
	   controller handles timer interrupts, software interrupts, and
	   hardware interrupts. Without a per-HART local interrupt controller,
	   a RISC-V system will be unable to handle any interrupts.

	   If you don't know what to do here, say Y.

config SIFIVE_PLIC
	bool "SiFive Platform-Level Interrupt Controller"
	depends on RISCV
	select IRQ_DOMAIN_HIERARCHY
	help
	   This enables support for the PLIC chip found in SiFive (and
	   potentially other) RISC-V systems.  The PLIC controls devices
	   interrupts and connects them to each core's local interrupt
	   controller.  Aside from timer and software interrupts, all other
	   interrupt sources are subordinate to the PLIC.

	   If you don't know what to do here, say Y.

config EXYNOS_IRQ_COMBINER
	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Samsung Exynos chips.

config LOONGSON_LIOINTC
	bool "Loongson Local I/O Interrupt Controller"
	depends on MACH_LOONGSON64
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson Local I/O Interrupt Controller.

config LOONGSON_HTPIC
	bool "Loongson3 HyperTransport PIC Controller"
	depends on MACH_LOONGSON64
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson-3 HyperTransport PIC Controller.

config LOONGSON_HTVEC
	bool "Loongson3 HyperTransport Interrupt Vector Controller"
	depends on MACH_LOONGSON64
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the Loongson3 HyperTransport Interrupt Vector Controller.

config LOONGSON_PCH_PIC
	bool "Loongson PCH PIC Controller"
	depends on MACH_LOONGSON64 || COMPILE_TEST
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	select IRQ_FASTEOI_HIERARCHY_HANDLERS
	help
	  Support for the Loongson PCH PIC Controller.

config LOONGSON_PCH_MSI
	bool "Loongson PCH MSI Controller"
	depends on MACH_LOONGSON64 || COMPILE_TEST
	depends on PCI
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	select PCI_MSI
	help
	  Support for the Loongson PCH MSI Controller.

config MST_IRQ
	bool "MStar Interrupt Controller"
	default ARCH_MEDIATEK
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support MStar Interrupt Controller.

endmenu
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
c94fb639 RD	2	menu "IRQ chip support"
c94fb639 RD	3
f6e916b8 TP	4	config IRQCHIP
	5	def_bool y
	6	depends on OF_IRQ
	7
81243e44 RH	8	config ARM_GIC
81243e44 RH	9	bool
9a1091ef	10	select IRQ_DOMAIN_HIERARCHY
4f7799d9	11	select GENERIC_IRQ_MULTI_HANDLER
0c9e4982	12	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44	13
9c8edddf JH	14	config ARM_GIC_PM
	15	bool
	16	depends on PM
	17	select ARM_GIC
9c8edddf	18
a27d21e0 LW	19	config ARM_GIC_MAX_NR
a27d21e0 LW	20	int
70265523	21	depends on ARM_GIC
a27d21e0 LW	22	default 2 if ARCH_REALVIEW
	23	default 1
	24
853a33ce SS	25	config ARM_GIC_V2M
853a33ce SS	26	bool
3ee80364 AB	27	depends on PCI
	28	select ARM_GIC
	29	select PCI_MSI
853a33ce	30
81243e44 RH	31	config GIC_NON_BANKED
	32	bool
	33
021f6537 MZ	34	config ARM_GIC_V3
021f6537 MZ	35	bool
4f7799d9	36	select GENERIC_IRQ_MULTI_HANDLER
443acc4f	37	select IRQ_DOMAIN_HIERARCHY
e3825ba1	38	select PARTITION_PERCPU
956ae91a	39	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537	40
19812729 MZ	41	config ARM_GIC_V3_ITS
19812729 MZ	42	bool
29f41139 MZ	43	select GENERIC_MSI_IRQ_DOMAIN
	44	default ARM_GIC_V3
	45
	46	config ARM_GIC_V3_ITS_PCI
	47	bool
	48	depends on ARM_GIC_V3_ITS
3ee80364 AB	49	depends on PCI
3ee80364 AB	50	depends on PCI_MSI
29f41139	51	default ARM_GIC_V3_ITS
021f6537	52
7afe031c BP	53	config ARM_GIC_V3_ITS_FSL_MC
	54	bool
	55	depends on ARM_GIC_V3_ITS
	56	depends on FSL_MC_BUS
	57	default ARM_GIC_V3_ITS
	58
292ec080 UKK	59	config ARM_NVIC
292ec080 UKK	60	bool
2d9f59f7	61	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	62	select GENERIC_IRQ_CHIP
292ec080 UKK	63
44430ec0 RH	64	config ARM_VIC
	65	bool
	66	select IRQ_DOMAIN
4f7799d9	67	select GENERIC_IRQ_MULTI_HANDLER
44430ec0 RH	68
	69	config ARM_VIC_NR
	70	int
	71	default 4 if ARCH_S5PV210
44430ec0 RH	72	default 2
	73	depends on ARM_VIC
	74	help
	75	The maximum number of VICs available in the system, for
	76	power management.
	77
fed6d336 TP	78	config ARMADA_370_XP_IRQ
fed6d336 TP	79	bool
fed6d336	80	select GENERIC_IRQ_CHIP
3ee80364	81	select PCI_MSI if PCI
e31793a3	82	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336	83
e6b78f2c AT	84	config ALPINE_MSI
e6b78f2c AT	85	bool
3ee80364 AB	86	depends on PCI
3ee80364 AB	87	select PCI_MSI
e6b78f2c	88	select GENERIC_IRQ_CHIP
e6b78f2c	89
1eb77c3b TS	90	config AL_FIC
	91	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
	92	depends on OF \|\| COMPILE_TEST
	93	select GENERIC_IRQ_CHIP
	94	select IRQ_DOMAIN
	95	help
	96	Support Amazon's Annapurna Labs Fabric Interrupt Controller.
	97
b1479ebb BB	98	config ATMEL_AIC_IRQ
	99	bool
	100	select GENERIC_IRQ_CHIP
	101	select IRQ_DOMAIN
4f7799d9	102	select GENERIC_IRQ_MULTI_HANDLER
b1479ebb BB	103	select SPARSE_IRQ
	104
	105	config ATMEL_AIC5_IRQ
	106	bool
	107	select GENERIC_IRQ_CHIP
	108	select IRQ_DOMAIN
4f7799d9	109	select GENERIC_IRQ_MULTI_HANDLER
b1479ebb BB	110	select SPARSE_IRQ
b1479ebb BB	111
0509cfde RB	112	config I8259
	113	bool
	114	select IRQ_DOMAIN
	115
c7c42ec2 SA	116	config BCM6345_L1_IRQ
	117	bool
	118	select GENERIC_IRQ_CHIP
	119	select IRQ_DOMAIN
d0ed5e8e	120	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2	121
5f7f0317 KC	122	config BCM7038_L1_IRQ
	123	bool
	124	select GENERIC_IRQ_CHIP
	125	select IRQ_DOMAIN
b8d9884a	126	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317	127
a4fcbb86 KC	128	config BCM7120_L2_IRQ
	129	bool
	130	select GENERIC_IRQ_CHIP
	131	select IRQ_DOMAIN
	132
7f646e92 FF	133	config BRCMSTB_L2_IRQ
7f646e92 FF	134	bool
7f646e92 FF	135	select GENERIC_IRQ_CHIP
	136	select IRQ_DOMAIN
	137
0145beed BG	138	config DAVINCI_AINTC
	139	bool
	140	select GENERIC_IRQ_CHIP
	141	select IRQ_DOMAIN
	142
0fc3d74c BG	143	config DAVINCI_CP_INTC
	144	bool
	145	select GENERIC_IRQ_CHIP
	146	select IRQ_DOMAIN
	147
350d71b9 SH	148	config DW_APB_ICTL
350d71b9 SH	149	bool
e1588490	150	select GENERIC_IRQ_CHIP
54a38440	151	select IRQ_DOMAIN_HIERARCHY
350d71b9	152
6ee532e2 LW	153	config FARADAY_FTINTC010
	154	bool
	155	select IRQ_DOMAIN
4f7799d9	156	select GENERIC_IRQ_MULTI_HANDLER
6ee532e2 LW	157	select SPARSE_IRQ
6ee532e2 LW	158
9a7c4abd M	159	config HISILICON_IRQ_MBIGEN
	160	bool
	161	select ARM_GIC_V3
	162	select ARM_GIC_V3_ITS
9a7c4abd	163
b6ef9161 JH	164	config IMGPDC_IRQ
	165	bool
	166	select GENERIC_IRQ_CHIP
	167	select IRQ_DOMAIN
	168
5b978c10 LW	169	config IXP4XX_IRQ
	170	bool
	171	select IRQ_DOMAIN
	172	select GENERIC_IRQ_MULTI_HANDLER
	173	select SPARSE_IRQ
	174
da0abe1a RF	175	config MADERA_IRQ
	176	tristate
	177
67e38cf2 RB	178	config IRQ_MIPS_CPU
	179	bool
	180	select GENERIC_IRQ_CHIP
3838a547	181	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2	182	select IRQ_DOMAIN
3838a547	183	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
18416e45	184	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2	185
afc98d90 AS	186	config CLPS711X_IRQCHIP
	187	bool
	188	depends on ARCH_CLPS711X
	189	select IRQ_DOMAIN
4f7799d9	190	select GENERIC_IRQ_MULTI_HANDLER
afc98d90 AS	191	select SPARSE_IRQ
	192	default y
	193
9b54470a SH	194	config OMPIC
	195	bool
	196
4db8e6d2 SK	197	config OR1K_PIC
	198	bool
	199	select IRQ_DOMAIN
	200
8598066c FB	201	config OMAP_IRQCHIP
	202	bool
	203	select GENERIC_IRQ_CHIP
	204	select IRQ_DOMAIN
	205
9dbd90f1 SH	206	config ORION_IRQCHIP
	207	bool
	208	select IRQ_DOMAIN
4f7799d9	209	select GENERIC_IRQ_MULTI_HANDLER
9dbd90f1	210
aaa8666a CB	211	config PIC32_EVIC
	212	bool
	213	select GENERIC_IRQ_CHIP
	214	select IRQ_DOMAIN
	215
981b58f6	216	config JCORE_AIC
3602ffde RF	217	bool "J-Core integrated AIC" if COMPILE_TEST
3602ffde RF	218	depends on OF
981b58f6 RF	219	select IRQ_DOMAIN
	220	help
	221	Support for the J-Core integrated AIC.
	222
d852e62a MS	223	config RDA_INTC
	224	bool
	225	select IRQ_DOMAIN
	226
44358048	227	config RENESAS_INTC_IRQPIN
02d7e041	228	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
44358048	229	select IRQ_DOMAIN
02d7e041 GU	230	help
	231	Enable support for the Renesas Interrupt Controller for external
	232	interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
44358048	233
fbc83b7f	234	config RENESAS_IRQC
72d44c0c	235	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
99c221df	236	select GENERIC_IRQ_CHIP
fbc83b7f	237	select IRQ_DOMAIN
02d7e041 GU	238	help
02d7e041 GU	239	Enable support for the Renesas Interrupt Controller for external
72d44c0c	240	devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
fbc83b7f	241
a644ccb8	242	config RENESAS_RZA1_IRQC
02d7e041	243	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
a644ccb8	244	select IRQ_DOMAIN_HIERARCHY
02d7e041 GU	245	help
	246	Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
	247	to 8 external interrupts with configurable sense select.
a644ccb8	248
03ac990e MW	249	config SL28CPLD_INTC
	250	bool "Kontron sl28cpld IRQ controller"
	251	depends on MFD_SL28CPLD=y \|\| COMPILE_TEST
	252	select REGMAP_IRQ
	253	help
	254	Interrupt controller driver for the board management controller
	255	found on the Kontron sl28 CPLD.
	256
07088484 LJ	257	config ST_IRQCHIP
	258	bool
	259	select REGMAP
	260	select MFD_SYSCON
	261	help
	262	Enables SysCfg Controlled IRQs on STi based platforms.
	263
4bba6689 MR	264	config TANGO_IRQ
	265	bool
	266	select IRQ_DOMAIN
	267	select GENERIC_IRQ_CHIP
	268
b06eb017 CR	269	config TB10X_IRQC
	270	bool
	271	select IRQ_DOMAIN
	272	select GENERIC_IRQ_CHIP
	273
d01f8633 DR	274	config TS4800_IRQ
	275	tristate "TS-4800 IRQ controller"
	276	select IRQ_DOMAIN
0df337cf	277	depends on HAS_IOMEM
d2b383dc	278	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	279	help
	280	Support for the TS-4800 FPGA IRQ controller
	281
2389d501 LW	282	config VERSATILE_FPGA_IRQ
	283	bool
	284	select IRQ_DOMAIN
	285
	286	config VERSATILE_FPGA_IRQ_NR
	287	int
	288	default 4
	289	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	290
	291	config XTENSA_MX
	292	bool
	293	select IRQ_DOMAIN
50091212	294	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e	295
0547dc78 ZLK	296	config XILINX_INTC
	297	bool
	298	select IRQ_DOMAIN
	299
96ca848e S	300	config IRQ_CROSSBAR
	301	bool
	302	help
f54619f2	303	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	304	The primary irqchip invokes the crossbar's callback which inturn allocates
	305	a free irq and configures the IP. Thus the peripheral interrupts are
	306	routed to one of the free irqchip interrupt lines.
89323f8c GS	307
	308	config KEYSTONE_IRQ
	309	tristate "Keystone 2 IRQ controller IP"
	310	depends on ARCH_KEYSTONE
	311	help
	312	Support for Texas Instruments Keystone 2 IRQ controller IP which
	313	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	314
	315	config MIPS_GIC
	316	bool
bb11cff3	317	select GENERIC_IRQ_IPI
2af70a96	318	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	319	select MIPS_CM
8a764482	320
44e08e70 PB	321	config INGENIC_IRQ
	322	bool
	323	depends on MACH_INGENIC
	324	default y
78c10e55	325
9536eba0 PC	326	config INGENIC_TCU_IRQ
	327	bool "Ingenic JZ47xx TCU interrupt controller"
	328	default MACH_INGENIC
	329	depends on MIPS \|\| COMPILE_TEST
	330	select MFD_SYSCON
8084499b	331	select GENERIC_IRQ_CHIP
9536eba0 PC	332	help
	333	Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
	334	JZ47xx SoCs.
	335
	336	If unsure, say N.
	337
8a764482 YS	338	config RENESAS_H8300H_INTC
	339	bool
	340	select IRQ_DOMAIN
	341
	342	config RENESAS_H8S_INTC
02d7e041	343	bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
78c10e55	344	select IRQ_DOMAIN
02d7e041 GU	345	help
	346	Enable support for the Renesas H8/300 Interrupt Controller, as found
	347	on Renesas H8S SoCs.
e324c4dc SW	348
	349	config IMX_GPCV2
	350	bool
	351	select IRQ_DOMAIN
	352	help
	353	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	354
	355	config IRQ_MXS
	356	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	357	select IRQ_DOMAIN
	358	select STMP_DEVICE
c27f29bb	359
19d99164 AB	360	config MSCC_OCELOT_IRQ
	361	bool
	362	select IRQ_DOMAIN
	363	select GENERIC_IRQ_CHIP
	364
a68a63cb TP	365	config MVEBU_GICP
	366	bool
	367
e0de91a9 TP	368	config MVEBU_ICU
	369	bool
	370
c27f29bb TP	371	config MVEBU_ODMI
c27f29bb TP	372	bool
fa23b9d1	373	select GENERIC_MSI_IRQ_DOMAIN
9e2c986c	374
a109893b TP	375	config MVEBU_PIC
	376	bool
	377
61ce8d8d MR	378	config MVEBU_SEI
	379	bool
	380
0dcd9f87 RV	381	config LS_EXTIRQ
	382	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	383	select MFD_SYSCON
	384
b8f3ebe6 ML	385	config LS_SCFG_MSI
	386	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	387	depends on PCI && PCI_MSI
b8f3ebe6	388
9e2c986c MZ	389	config PARTITION_PERCPU
9e2c986c MZ	390	bool
0efacbba	391
44df427c NC	392	config EZNPS_GIC
44df427c NC	393	bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3	394	depends on ARC \|\| (COMPILE_TEST && !64BIT)
44df427c NC	395	select IRQ_DOMAIN
	396	help
	397	Support the EZchip NPS400 global interrupt controller
e0720416 AT	398
	399	config STM32_EXTI
	400	bool
	401	select IRQ_DOMAIN
0e7d7807	402	select GENERIC_IRQ_CHIP
f20cc9b0 AVF	403
	404	config QCOM_IRQ_COMBINER
	405	bool "QCOM IRQ combiner support"
	406	depends on ARCH_QCOM && ACPI
f20cc9b0 AVF	407	select IRQ_DOMAIN_HIERARCHY
	408	help
	409	Say yes here to add support for the IRQ combiner devices embedded
	410	in Qualcomm Technologies chips.
5ed34d3a MY	411
	412	config IRQ_UNIPHIER_AIDET
	413	bool "UniPhier AIDET support" if COMPILE_TEST
	414	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
	415	default ARCH_UNIPHIER
	416	select IRQ_DOMAIN_HIERARCHY
	417	help
	418	Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639	419
215f4cc0 JB	420	config MESON_IRQ_GPIO
215f4cc0 JB	421	bool "Meson GPIO Interrupt Multiplexer"
d9ee91c1	422	depends on ARCH_MESON
215f4cc0 JB	423	select IRQ_DOMAIN_HIERARCHY
	424	help
	425	Support Meson SoC Family GPIO Interrupt Multiplexer
	426
4235ff50 MD	427	config GOLDFISH_PIC
	428	bool "Goldfish programmable interrupt controller"
	429	depends on MIPS && (GOLDFISH \|\| COMPILE_TEST)
	430	select IRQ_DOMAIN
	431	help
	432	Say yes here to enable Goldfish interrupt controller driver used
	433	for Goldfish based virtual platforms.
	434
f55c73ae	435	config QCOM_PDC
a150dac5	436	bool "QCOM PDC"
f55c73ae	437	depends on ARCH_QCOM
f55c73ae AS	438	select IRQ_DOMAIN_HIERARCHY
	439	help
	440	Power Domain Controller driver to manage and configure wakeup
	441	IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
	442
d8a5f5f7 GR	443	config CSKY_MPINTC
	444	bool "C-SKY Multi Processor Interrupt Controller"
	445	depends on CSKY
	446	help
	447	Say yes here to enable C-SKY SMP interrupt controller driver used
	448	for C-SKY SMP system.
656b42de	449	In fact it's not mmio map in hardware and it uses ld/st to visit the
d8a5f5f7 GR	450	controller's register inside CPU.
d8a5f5f7 GR	451
edff1b48 GR	452	config CSKY_APB_INTC
	453	bool "C-SKY APB Interrupt Controller"
	454	depends on CSKY
	455	help
	456	Say yes here to enable C-SKY APB interrupt controller driver used
656b42de	457	by C-SKY single core SOC system. It uses mmio map apb-bus to visit
edff1b48 GR	458	the controller's register.
edff1b48 GR	459
0136afa0 LS	460	config IMX_IRQSTEER
	461	bool "i.MX IRQSTEER support"
	462	depends on ARCH_MXC \|\| COMPILE_TEST
	463	default ARCH_MXC
	464	select IRQ_DOMAIN
	465	help
	466	Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
	467
2fbb1396	468	config IMX_INTMUX
66968d7d	469	def_bool y if ARCH_MXC \|\| COMPILE_TEST
2fbb1396 JZ	470	select IRQ_DOMAIN
	471	help
	472	Support for the i.MX INTMUX interrupt multiplexer.
	473
9e543e22 JY	474	config LS1X_IRQ
	475	bool "Loongson-1 Interrupt Controller"
	476	depends on MACH_LOONGSON32
	477	default y
	478	select IRQ_DOMAIN
	479	select GENERIC_IRQ_CHIP
	480	help
	481	Support for the Loongson-1 platform Interrupt Controller.
	482
cd844b07 LV	483	config TI_SCI_INTR_IRQCHIP
	484	bool
	485	depends on TI_SCI_PROTOCOL
	486	select IRQ_DOMAIN_HIERARCHY
	487	help
	488	This enables the irqchip driver support for K3 Interrupt router
	489	over TI System Control Interface available on some new TI's SoCs.
	490	If you wish to use interrupt router irq resources managed by the
	491	TI System Controller, say Y here. Otherwise, say N.
	492
9f1463b8 LV	493	config TI_SCI_INTA_IRQCHIP
	494	bool
	495	depends on TI_SCI_PROTOCOL
	496	select IRQ_DOMAIN_HIERARCHY
f011df61	497	select TI_SCI_INTA_MSI_DOMAIN
9f1463b8 LV	498	help
	499	This enables the irqchip driver support for K3 Interrupt aggregator
	500	over TI System Control Interface available on some new TI's SoCs.
	501	If you wish to use interrupt aggregator irq resources managed by the
	502	TI System Controller, say Y here. Otherwise, say N.
	503
04e2d1e0 GJ	504	config TI_PRUSS_INTC
04e2d1e0 GJ	505	tristate "TI PRU-ICSS Interrupt Controller"
7e92dee6	506	depends on ARCH_DAVINCI \|\| SOC_AM33XX \|\| SOC_AM43XX \|\| SOC_DRA7XX \|\| ARCH_KEYSTONE \|\| ARCH_K3
04e2d1e0 GJ	507	select IRQ_DOMAIN
	508	help
	509	This enables support for the PRU-ICSS Local Interrupt Controller
	510	present within a PRU-ICSS subsystem present on various TI SoCs.
	511	The PRUSS INTC enables various interrupts to be routed to multiple
	512	different processors within the SoC.
	513
6b7ce892 AP	514	config RISCV_INTC
	515	bool "RISC-V Local Interrupt Controller"
	516	depends on RISCV
	517	default y
	518	help
	519	This enables support for the per-HART local interrupt controller
	520	found in standard RISC-V systems. The per-HART local interrupt
	521	controller handles timer interrupts, software interrupts, and
	522	hardware interrupts. Without a per-HART local interrupt controller,
	523	a RISC-V system will be unable to handle any interrupts.
	524
	525	If you don't know what to do here, say Y.
	526
8237f8bc CH	527	config SIFIVE_PLIC
	528	bool "SiFive Platform-Level Interrupt Controller"
	529	depends on RISCV
466008f9	530	select IRQ_DOMAIN_HIERARCHY
8237f8bc CH	531	help
	532	This enables support for the PLIC chip found in SiFive (and
	533	potentially other) RISC-V systems. The PLIC controls devices
	534	interrupts and connects them to each core's local interrupt
	535	controller. Aside from timer and software interrupts, all other
	536	interrupt sources are subordinate to the PLIC.
	537
	538	If you don't know what to do here, say Y.
01493855	539
b74416db HK	540	config EXYNOS_IRQ_COMBINER
	541	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
	542	depends on (ARCH_EXYNOS && ARM) \|\| COMPILE_TEST
	543	help
	544	Say yes here to add support for the IRQ combiner devices embedded
	545	in Samsung Exynos chips.
	546
dbb15226 JY	547	config LOONGSON_LIOINTC
	548	bool "Loongson Local I/O Interrupt Controller"
	549	depends on MACH_LOONGSON64
	550	default y
	551	select IRQ_DOMAIN
	552	select GENERIC_IRQ_CHIP
	553	help
	554	Support for the Loongson Local I/O Interrupt Controller.
	555
a93f1d90 JY	556	config LOONGSON_HTPIC
	557	bool "Loongson3 HyperTransport PIC Controller"
	558	depends on MACH_LOONGSON64
	559	default y
	560	select IRQ_DOMAIN
	561	select GENERIC_IRQ_CHIP
a93f1d90 JY	562	help
	563	Support for the Loongson-3 HyperTransport PIC Controller.
	564
818e915f JY	565	config LOONGSON_HTVEC
818e915f JY	566	bool "Loongson3 HyperTransport Interrupt Vector Controller"
d77aeb5d	567	depends on MACH_LOONGSON64
818e915f JY	568	default MACH_LOONGSON64
	569	select IRQ_DOMAIN_HIERARCHY
	570	help
	571	Support for the Loongson3 HyperTransport Interrupt Vector Controller.
	572
ef8c01eb JY	573	config LOONGSON_PCH_PIC
	574	bool "Loongson PCH PIC Controller"
	575	depends on MACH_LOONGSON64 \|\| COMPILE_TEST
	576	default MACH_LOONGSON64
	577	select IRQ_DOMAIN_HIERARCHY
	578	select IRQ_FASTEOI_HIERARCHY_HANDLERS
	579	help
	580	Support for the Loongson PCH PIC Controller.
	581
632dcc2c	582	config LOONGSON_PCH_MSI
a23df9a4	583	bool "Loongson PCH MSI Controller"
632dcc2c JY	584	depends on MACH_LOONGSON64 \|\| COMPILE_TEST
	585	depends on PCI
	586	default MACH_LOONGSON64
	587	select IRQ_DOMAIN_HIERARCHY
	588	select PCI_MSI
	589	help
	590	Support for the Loongson PCH MSI Controller.
	591
ad4c938c MPT	592	config MST_IRQ
	593	bool "MStar Interrupt Controller"
	594	default ARCH_MEDIATEK
	595	select IRQ_DOMAIN
	596	select IRQ_DOMAIN_HIERARCHY
	597	help
	598	Support MStar Interrupt Controller.
	599
01493855	600	endmenu