[linux-2.6-block.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC
	select PM_CLK

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_V3_ITS
	bool
	depends on PCI
	depends on PCI_MSI

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config FARADAY_FTINTC010
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC" if COMPILE_TEST
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config XILINX_INTC
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MVEBU_GICP
	bool

config MVEBU_ICU
	bool

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN

config MVEBU_PIC
	bool

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config EZNPS_GIC
	bool "NPS400 Global Interrupt Manager (GIM)"
	depends on ARC || (COMPILE_TEST && !64BIT)
	select IRQ_DOMAIN
	help
	  Support the EZchip NPS400 global interrupt controller

config STM32_EXTI
	bool
	select IRQ_DOMAIN

config QCOM_IRQ_COMBINER
	bool "QCOM IRQ combiner support"
	depends on ARCH_QCOM && ACPI
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Qualcomm Technologies chips.

config IRQ_UNIPHIER_AIDET
	bool "UniPhier AIDET support" if COMPILE_TEST
	depends on ARCH_UNIPHIER || COMPILE_TEST
	default ARCH_UNIPHIER
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the UniPhier AIDET (ARM Interrupt Detector).
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44	9	select MULTI_IRQ_HANDLER
0c9e4982	10	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44	11
9c8edddf JH	12	config ARM_GIC_PM
	13	bool
	14	depends on PM
	15	select ARM_GIC
	16	select PM_CLK
	17
a27d21e0 LW	18	config ARM_GIC_MAX_NR
	19	int
	20	default 2 if ARCH_REALVIEW
	21	default 1
	22
853a33ce SS	23	config ARM_GIC_V2M
853a33ce SS	24	bool
3ee80364 AB	25	depends on PCI
	26	select ARM_GIC
	27	select PCI_MSI
853a33ce	28
81243e44 RH	29	config GIC_NON_BANKED
	30	bool
	31
021f6537 MZ	32	config ARM_GIC_V3
	33	bool
	34	select IRQ_DOMAIN
	35	select MULTI_IRQ_HANDLER
443acc4f	36	select IRQ_DOMAIN_HIERARCHY
e3825ba1	37	select PARTITION_PERCPU
956ae91a	38	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537	39
19812729 MZ	40	config ARM_GIC_V3_ITS
19812729 MZ	41	bool
3ee80364 AB	42	depends on PCI
3ee80364 AB	43	depends on PCI_MSI
021f6537	44
292ec080 UKK	45	config ARM_NVIC
	46	bool
	47	select IRQ_DOMAIN
2d9f59f7	48	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	49	select GENERIC_IRQ_CHIP
292ec080 UKK	50
44430ec0 RH	51	config ARM_VIC
	52	bool
	53	select IRQ_DOMAIN
	54	select MULTI_IRQ_HANDLER
	55
	56	config ARM_VIC_NR
	57	int
	58	default 4 if ARCH_S5PV210
44430ec0 RH	59	default 2
	60	depends on ARM_VIC
	61	help
	62	The maximum number of VICs available in the system, for
	63	power management.
	64
fed6d336 TP	65	config ARMADA_370_XP_IRQ
fed6d336 TP	66	bool
fed6d336	67	select GENERIC_IRQ_CHIP
3ee80364	68	select PCI_MSI if PCI
e31793a3	69	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336	70
e6b78f2c AT	71	config ALPINE_MSI
e6b78f2c AT	72	bool
3ee80364 AB	73	depends on PCI
3ee80364 AB	74	select PCI_MSI
e6b78f2c	75	select GENERIC_IRQ_CHIP
e6b78f2c	76
b1479ebb BB	77	config ATMEL_AIC_IRQ
	78	bool
	79	select GENERIC_IRQ_CHIP
	80	select IRQ_DOMAIN
	81	select MULTI_IRQ_HANDLER
	82	select SPARSE_IRQ
	83
	84	config ATMEL_AIC5_IRQ
	85	bool
	86	select GENERIC_IRQ_CHIP
	87	select IRQ_DOMAIN
	88	select MULTI_IRQ_HANDLER
	89	select SPARSE_IRQ
	90
0509cfde RB	91	config I8259
	92	bool
	93	select IRQ_DOMAIN
	94
c7c42ec2 SA	95	config BCM6345_L1_IRQ
	96	bool
	97	select GENERIC_IRQ_CHIP
	98	select IRQ_DOMAIN
d0ed5e8e	99	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2	100
5f7f0317 KC	101	config BCM7038_L1_IRQ
	102	bool
	103	select GENERIC_IRQ_CHIP
	104	select IRQ_DOMAIN
b8d9884a	105	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317	106
a4fcbb86 KC	107	config BCM7120_L2_IRQ
	108	bool
	109	select GENERIC_IRQ_CHIP
	110	select IRQ_DOMAIN
	111
7f646e92 FF	112	config BRCMSTB_L2_IRQ
7f646e92 FF	113	bool
7f646e92 FF	114	select GENERIC_IRQ_CHIP
	115	select IRQ_DOMAIN
	116
350d71b9 SH	117	config DW_APB_ICTL
350d71b9 SH	118	bool
e1588490	119	select GENERIC_IRQ_CHIP
350d71b9 SH	120	select IRQ_DOMAIN
350d71b9 SH	121
6ee532e2 LW	122	config FARADAY_FTINTC010
	123	bool
	124	select IRQ_DOMAIN
	125	select MULTI_IRQ_HANDLER
	126	select SPARSE_IRQ
	127
9a7c4abd M	128	config HISILICON_IRQ_MBIGEN
	129	bool
	130	select ARM_GIC_V3
	131	select ARM_GIC_V3_ITS
9a7c4abd	132
b6ef9161 JH	133	config IMGPDC_IRQ
	134	bool
	135	select GENERIC_IRQ_CHIP
	136	select IRQ_DOMAIN
	137
67e38cf2 RB	138	config IRQ_MIPS_CPU
	139	bool
	140	select GENERIC_IRQ_CHIP
3838a547	141	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2	142	select IRQ_DOMAIN
3838a547	143	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
18416e45	144	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2	145
afc98d90 AS	146	config CLPS711X_IRQCHIP
	147	bool
	148	depends on ARCH_CLPS711X
	149	select IRQ_DOMAIN
	150	select MULTI_IRQ_HANDLER
	151	select SPARSE_IRQ
	152	default y
	153
4db8e6d2 SK	154	config OR1K_PIC
	155	bool
	156	select IRQ_DOMAIN
	157
8598066c FB	158	config OMAP_IRQCHIP
	159	bool
	160	select GENERIC_IRQ_CHIP
	161	select IRQ_DOMAIN
	162
9dbd90f1 SH	163	config ORION_IRQCHIP
	164	bool
	165	select IRQ_DOMAIN
	166	select MULTI_IRQ_HANDLER
	167
aaa8666a CB	168	config PIC32_EVIC
	169	bool
	170	select GENERIC_IRQ_CHIP
	171	select IRQ_DOMAIN
	172
981b58f6	173	config JCORE_AIC
3602ffde RF	174	bool "J-Core integrated AIC" if COMPILE_TEST
3602ffde RF	175	depends on OF
981b58f6 RF	176	select IRQ_DOMAIN
	177	help
	178	Support for the J-Core integrated AIC.
	179
44358048 MD	180	config RENESAS_INTC_IRQPIN
	181	bool
	182	select IRQ_DOMAIN
	183
fbc83b7f MD	184	config RENESAS_IRQC
fbc83b7f MD	185	bool
99c221df	186	select GENERIC_IRQ_CHIP
fbc83b7f MD	187	select IRQ_DOMAIN
fbc83b7f MD	188
07088484 LJ	189	config ST_IRQCHIP
	190	bool
	191	select REGMAP
	192	select MFD_SYSCON
	193	help
	194	Enables SysCfg Controlled IRQs on STi based platforms.
	195
4bba6689 MR	196	config TANGO_IRQ
	197	bool
	198	select IRQ_DOMAIN
	199	select GENERIC_IRQ_CHIP
	200
b06eb017 CR	201	config TB10X_IRQC
	202	bool
	203	select IRQ_DOMAIN
	204	select GENERIC_IRQ_CHIP
	205
d01f8633 DR	206	config TS4800_IRQ
	207	tristate "TS-4800 IRQ controller"
	208	select IRQ_DOMAIN
0df337cf	209	depends on HAS_IOMEM
d2b383dc	210	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	211	help
	212	Support for the TS-4800 FPGA IRQ controller
	213
2389d501 LW	214	config VERSATILE_FPGA_IRQ
	215	bool
	216	select IRQ_DOMAIN
	217
	218	config VERSATILE_FPGA_IRQ_NR
	219	int
	220	default 4
	221	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	222
	223	config XTENSA_MX
	224	bool
	225	select IRQ_DOMAIN
50091212	226	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e	227
0547dc78 ZLK	228	config XILINX_INTC
	229	bool
	230	select IRQ_DOMAIN
	231
96ca848e S	232	config IRQ_CROSSBAR
	233	bool
	234	help
f54619f2	235	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	236	The primary irqchip invokes the crossbar's callback which inturn allocates
	237	a free irq and configures the IP. Thus the peripheral interrupts are
	238	routed to one of the free irqchip interrupt lines.
89323f8c GS	239
	240	config KEYSTONE_IRQ
	241	tristate "Keystone 2 IRQ controller IP"
	242	depends on ARCH_KEYSTONE
	243	help
	244	Support for Texas Instruments Keystone 2 IRQ controller IP which
	245	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	246
	247	config MIPS_GIC
	248	bool
bb11cff3	249	select GENERIC_IRQ_IPI
2af70a96	250	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	251	select MIPS_CM
8a764482	252
44e08e70 PB	253	config INGENIC_IRQ
	254	bool
	255	depends on MACH_INGENIC
	256	default y
78c10e55	257
8a764482 YS	258	config RENESAS_H8300H_INTC
	259	bool
	260	select IRQ_DOMAIN
	261
	262	config RENESAS_H8S_INTC
	263	bool
78c10e55	264	select IRQ_DOMAIN
e324c4dc SW	265
	266	config IMX_GPCV2
	267	bool
	268	select IRQ_DOMAIN
	269	help
	270	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	271
	272	config IRQ_MXS
	273	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	274	select IRQ_DOMAIN
	275	select STMP_DEVICE
c27f29bb	276
a68a63cb TP	277	config MVEBU_GICP
	278	bool
	279
e0de91a9 TP	280	config MVEBU_ICU
	281	bool
	282
c27f29bb TP	283	config MVEBU_ODMI
c27f29bb TP	284	bool
fa23b9d1	285	select GENERIC_MSI_IRQ_DOMAIN
9e2c986c	286
a109893b TP	287	config MVEBU_PIC
	288	bool
	289
b8f3ebe6 ML	290	config LS_SCFG_MSI
	291	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	292	depends on PCI && PCI_MSI
b8f3ebe6	293
9e2c986c MZ	294	config PARTITION_PERCPU
9e2c986c MZ	295	bool
0efacbba	296
44df427c NC	297	config EZNPS_GIC
44df427c NC	298	bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3	299	depends on ARC \|\| (COMPILE_TEST && !64BIT)
44df427c NC	300	select IRQ_DOMAIN
	301	help
	302	Support the EZchip NPS400 global interrupt controller
e0720416 AT	303
	304	config STM32_EXTI
	305	bool
	306	select IRQ_DOMAIN
f20cc9b0 AVF	307
	308	config QCOM_IRQ_COMBINER
	309	bool "QCOM IRQ combiner support"
	310	depends on ARCH_QCOM && ACPI
	311	select IRQ_DOMAIN
	312	select IRQ_DOMAIN_HIERARCHY
	313	help
	314	Say yes here to add support for the IRQ combiner devices embedded
	315	in Qualcomm Technologies chips.
5ed34d3a MY	316
	317	config IRQ_UNIPHIER_AIDET
	318	bool "UniPhier AIDET support" if COMPILE_TEST
	319	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
	320	default ARCH_UNIPHIER
	321	select IRQ_DOMAIN_HIERARCHY
	322	help
	323	Support for the UniPhier AIDET (ARM Interrupt Detector).