[linux-2.6-block.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on ARM_GIC
	depends on PCI && PCI_MSI
	select PCI_MSI_IRQ_DOMAIN

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY

config ARM_GIC_V3_ITS
	bool
	select PCI_MSI_IRQ_DOMAIN

config HISILICON_IRQ_MBIGEN
	bool "Support mbigen interrupt controller"
	default n
	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
	help
	 Enable the mbigen interrupt controller used on
	 Hisilicon platform.

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI_IRQ_DOMAIN if PCI_MSI

config ALPINE_MSI
	bool
	depends on PCI && PCI_MSI
	select GENERIC_IRQ_CHIP
	select PCI_MSI_IRQ_DOMAIN

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44 RH	9	select MULTI_IRQ_HANDLER
81243e44 RH	10
a27d21e0 LW	11	config ARM_GIC_MAX_NR
	12	int
	13	default 2 if ARCH_REALVIEW
	14	default 1
	15
853a33ce SS	16	config ARM_GIC_V2M
	17	bool
	18	depends on ARM_GIC
	19	depends on PCI && PCI_MSI
	20	select PCI_MSI_IRQ_DOMAIN
	21
81243e44 RH	22	config GIC_NON_BANKED
	23	bool
	24
021f6537 MZ	25	config ARM_GIC_V3
	26	bool
	27	select IRQ_DOMAIN
	28	select MULTI_IRQ_HANDLER
443acc4f	29	select IRQ_DOMAIN_HIERARCHY
021f6537	30
19812729 MZ	31	config ARM_GIC_V3_ITS
	32	bool
	33	select PCI_MSI_IRQ_DOMAIN
021f6537	34
717c3dbc MJ	35	config HISILICON_IRQ_MBIGEN
	36	bool "Support mbigen interrupt controller"
	37	default n
	38	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
	39	help
	40	Enable the mbigen interrupt controller used on
	41	Hisilicon platform.
	42
292ec080 UKK	43	config ARM_NVIC
	44	bool
	45	select IRQ_DOMAIN
2d9f59f7	46	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	47	select GENERIC_IRQ_CHIP
292ec080 UKK	48
44430ec0 RH	49	config ARM_VIC
	50	bool
	51	select IRQ_DOMAIN
	52	select MULTI_IRQ_HANDLER
	53
	54	config ARM_VIC_NR
	55	int
	56	default 4 if ARCH_S5PV210
44430ec0 RH	57	default 2
	58	depends on ARM_VIC
	59	help
	60	The maximum number of VICs available in the system, for
	61	power management.
	62
fed6d336 TP	63	config ARMADA_370_XP_IRQ
fed6d336 TP	64	bool
fed6d336	65	select GENERIC_IRQ_CHIP
fcc392d5	66	select PCI_MSI_IRQ_DOMAIN if PCI_MSI
fed6d336	67
e6b78f2c AT	68	config ALPINE_MSI
	69	bool
	70	depends on PCI && PCI_MSI
	71	select GENERIC_IRQ_CHIP
	72	select PCI_MSI_IRQ_DOMAIN
	73
b1479ebb BB	74	config ATMEL_AIC_IRQ
	75	bool
	76	select GENERIC_IRQ_CHIP
	77	select IRQ_DOMAIN
	78	select MULTI_IRQ_HANDLER
	79	select SPARSE_IRQ
	80
	81	config ATMEL_AIC5_IRQ
	82	bool
	83	select GENERIC_IRQ_CHIP
	84	select IRQ_DOMAIN
	85	select MULTI_IRQ_HANDLER
	86	select SPARSE_IRQ
	87
0509cfde RB	88	config I8259
	89	bool
	90	select IRQ_DOMAIN
	91
c7c42ec2 SA	92	config BCM6345_L1_IRQ
	93	bool
	94	select GENERIC_IRQ_CHIP
	95	select IRQ_DOMAIN
	96
5f7f0317 KC	97	config BCM7038_L1_IRQ
	98	bool
	99	select GENERIC_IRQ_CHIP
	100	select IRQ_DOMAIN
	101
a4fcbb86 KC	102	config BCM7120_L2_IRQ
	103	bool
	104	select GENERIC_IRQ_CHIP
	105	select IRQ_DOMAIN
	106
7f646e92 FF	107	config BRCMSTB_L2_IRQ
7f646e92 FF	108	bool
7f646e92 FF	109	select GENERIC_IRQ_CHIP
	110	select IRQ_DOMAIN
	111
350d71b9 SH	112	config DW_APB_ICTL
350d71b9 SH	113	bool
e1588490	114	select GENERIC_IRQ_CHIP
350d71b9 SH	115	select IRQ_DOMAIN
350d71b9 SH	116
b6ef9161 JH	117	config IMGPDC_IRQ
	118	bool
	119	select GENERIC_IRQ_CHIP
	120	select IRQ_DOMAIN
	121
67e38cf2 RB	122	config IRQ_MIPS_CPU
	123	bool
	124	select GENERIC_IRQ_CHIP
	125	select IRQ_DOMAIN
	126
afc98d90 AS	127	config CLPS711X_IRQCHIP
	128	bool
	129	depends on ARCH_CLPS711X
	130	select IRQ_DOMAIN
	131	select MULTI_IRQ_HANDLER
	132	select SPARSE_IRQ
	133	default y
	134
4db8e6d2 SK	135	config OR1K_PIC
	136	bool
	137	select IRQ_DOMAIN
	138
8598066c FB	139	config OMAP_IRQCHIP
	140	bool
	141	select GENERIC_IRQ_CHIP
	142	select IRQ_DOMAIN
	143
9dbd90f1 SH	144	config ORION_IRQCHIP
	145	bool
	146	select IRQ_DOMAIN
	147	select MULTI_IRQ_HANDLER
	148
aaa8666a CB	149	config PIC32_EVIC
	150	bool
	151	select GENERIC_IRQ_CHIP
	152	select IRQ_DOMAIN
	153
44358048 MD	154	config RENESAS_INTC_IRQPIN
	155	bool
	156	select IRQ_DOMAIN
	157
fbc83b7f MD	158	config RENESAS_IRQC
fbc83b7f MD	159	bool
99c221df	160	select GENERIC_IRQ_CHIP
fbc83b7f MD	161	select IRQ_DOMAIN
fbc83b7f MD	162
07088484 LJ	163	config ST_IRQCHIP
	164	bool
	165	select REGMAP
	166	select MFD_SYSCON
	167	help
	168	Enables SysCfg Controlled IRQs on STi based platforms.
	169
4bba6689 MR	170	config TANGO_IRQ
	171	bool
	172	select IRQ_DOMAIN
	173	select GENERIC_IRQ_CHIP
	174
b06eb017 CR	175	config TB10X_IRQC
	176	bool
	177	select IRQ_DOMAIN
	178	select GENERIC_IRQ_CHIP
	179
d01f8633 DR	180	config TS4800_IRQ
	181	tristate "TS-4800 IRQ controller"
	182	select IRQ_DOMAIN
0df337cf	183	depends on HAS_IOMEM
d2b383dc	184	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	185	help
	186	Support for the TS-4800 FPGA IRQ controller
	187
2389d501 LW	188	config VERSATILE_FPGA_IRQ
	189	bool
	190	select IRQ_DOMAIN
	191
	192	config VERSATILE_FPGA_IRQ_NR
	193	int
	194	default 4
	195	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	196
	197	config XTENSA_MX
	198	bool
	199	select IRQ_DOMAIN
96ca848e S	200
	201	config IRQ_CROSSBAR
	202	bool
	203	help
f54619f2	204	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	205	The primary irqchip invokes the crossbar's callback which inturn allocates
	206	a free irq and configures the IP. Thus the peripheral interrupts are
	207	routed to one of the free irqchip interrupt lines.
89323f8c GS	208
	209	config KEYSTONE_IRQ
	210	tristate "Keystone 2 IRQ controller IP"
	211	depends on ARCH_KEYSTONE
	212	help
	213	Support for Texas Instruments Keystone 2 IRQ controller IP which
	214	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	215
	216	config MIPS_GIC
	217	bool
bb11cff3	218	select GENERIC_IRQ_IPI
2af70a96	219	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	220	select MIPS_CM
8a764482	221
44e08e70 PB	222	config INGENIC_IRQ
	223	bool
	224	depends on MACH_INGENIC
	225	default y
78c10e55	226
8a764482 YS	227	config RENESAS_H8300H_INTC
	228	bool
	229	select IRQ_DOMAIN
	230
	231	config RENESAS_H8S_INTC
	232	bool
78c10e55	233	select IRQ_DOMAIN
e324c4dc SW	234
	235	config IMX_GPCV2
	236	bool
	237	select IRQ_DOMAIN
	238	help
	239	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	240
	241	config IRQ_MXS
	242	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	243	select IRQ_DOMAIN
	244	select STMP_DEVICE
c27f29bb TP	245
	246	config MVEBU_ODMI
	247	bool
	248	select GENERIC_MSI_IRQ_DOMAIN