Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
c94fb639 RD |
2 | menu "IRQ chip support" |
3 | ||
f6e916b8 TP |
4 | config IRQCHIP |
5 | def_bool y | |
6 | depends on OF_IRQ | |
7 | ||
81243e44 RH |
8 | config ARM_GIC |
9 | bool | |
9a1091ef | 10 | select IRQ_DOMAIN_HIERARCHY |
4f7799d9 | 11 | select GENERIC_IRQ_MULTI_HANDLER |
0c9e4982 | 12 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
81243e44 | 13 | |
9c8edddf JH |
14 | config ARM_GIC_PM |
15 | bool | |
16 | depends on PM | |
17 | select ARM_GIC | |
18 | select PM_CLK | |
19 | ||
a27d21e0 LW |
20 | config ARM_GIC_MAX_NR |
21 | int | |
22 | default 2 if ARCH_REALVIEW | |
23 | default 1 | |
24 | ||
853a33ce SS |
25 | config ARM_GIC_V2M |
26 | bool | |
3ee80364 AB |
27 | depends on PCI |
28 | select ARM_GIC | |
29 | select PCI_MSI | |
853a33ce | 30 | |
81243e44 RH |
31 | config GIC_NON_BANKED |
32 | bool | |
33 | ||
021f6537 MZ |
34 | config ARM_GIC_V3 |
35 | bool | |
4f7799d9 | 36 | select GENERIC_IRQ_MULTI_HANDLER |
443acc4f | 37 | select IRQ_DOMAIN_HIERARCHY |
e3825ba1 | 38 | select PARTITION_PERCPU |
956ae91a | 39 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
021f6537 | 40 | |
19812729 MZ |
41 | config ARM_GIC_V3_ITS |
42 | bool | |
29f41139 MZ |
43 | select GENERIC_MSI_IRQ_DOMAIN |
44 | default ARM_GIC_V3 | |
45 | ||
46 | config ARM_GIC_V3_ITS_PCI | |
47 | bool | |
48 | depends on ARM_GIC_V3_ITS | |
3ee80364 AB |
49 | depends on PCI |
50 | depends on PCI_MSI | |
29f41139 | 51 | default ARM_GIC_V3_ITS |
021f6537 | 52 | |
7afe031c BP |
53 | config ARM_GIC_V3_ITS_FSL_MC |
54 | bool | |
55 | depends on ARM_GIC_V3_ITS | |
56 | depends on FSL_MC_BUS | |
57 | default ARM_GIC_V3_ITS | |
58 | ||
292ec080 UKK |
59 | config ARM_NVIC |
60 | bool | |
2d9f59f7 | 61 | select IRQ_DOMAIN_HIERARCHY |
292ec080 UKK |
62 | select GENERIC_IRQ_CHIP |
63 | ||
44430ec0 RH |
64 | config ARM_VIC |
65 | bool | |
66 | select IRQ_DOMAIN | |
4f7799d9 | 67 | select GENERIC_IRQ_MULTI_HANDLER |
44430ec0 RH |
68 | |
69 | config ARM_VIC_NR | |
70 | int | |
71 | default 4 if ARCH_S5PV210 | |
44430ec0 RH |
72 | default 2 |
73 | depends on ARM_VIC | |
74 | help | |
75 | The maximum number of VICs available in the system, for | |
76 | power management. | |
77 | ||
fed6d336 TP |
78 | config ARMADA_370_XP_IRQ |
79 | bool | |
fed6d336 | 80 | select GENERIC_IRQ_CHIP |
3ee80364 | 81 | select PCI_MSI if PCI |
e31793a3 | 82 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
fed6d336 | 83 | |
e6b78f2c AT |
84 | config ALPINE_MSI |
85 | bool | |
3ee80364 AB |
86 | depends on PCI |
87 | select PCI_MSI | |
e6b78f2c | 88 | select GENERIC_IRQ_CHIP |
e6b78f2c | 89 | |
b1479ebb BB |
90 | config ATMEL_AIC_IRQ |
91 | bool | |
92 | select GENERIC_IRQ_CHIP | |
93 | select IRQ_DOMAIN | |
4f7799d9 | 94 | select GENERIC_IRQ_MULTI_HANDLER |
b1479ebb BB |
95 | select SPARSE_IRQ |
96 | ||
97 | config ATMEL_AIC5_IRQ | |
98 | bool | |
99 | select GENERIC_IRQ_CHIP | |
100 | select IRQ_DOMAIN | |
4f7799d9 | 101 | select GENERIC_IRQ_MULTI_HANDLER |
b1479ebb BB |
102 | select SPARSE_IRQ |
103 | ||
0509cfde RB |
104 | config I8259 |
105 | bool | |
106 | select IRQ_DOMAIN | |
107 | ||
c7c42ec2 SA |
108 | config BCM6345_L1_IRQ |
109 | bool | |
110 | select GENERIC_IRQ_CHIP | |
111 | select IRQ_DOMAIN | |
d0ed5e8e | 112 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
c7c42ec2 | 113 | |
5f7f0317 KC |
114 | config BCM7038_L1_IRQ |
115 | bool | |
116 | select GENERIC_IRQ_CHIP | |
117 | select IRQ_DOMAIN | |
b8d9884a | 118 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
5f7f0317 | 119 | |
a4fcbb86 KC |
120 | config BCM7120_L2_IRQ |
121 | bool | |
122 | select GENERIC_IRQ_CHIP | |
123 | select IRQ_DOMAIN | |
124 | ||
7f646e92 FF |
125 | config BRCMSTB_L2_IRQ |
126 | bool | |
7f646e92 FF |
127 | select GENERIC_IRQ_CHIP |
128 | select IRQ_DOMAIN | |
129 | ||
0145beed BG |
130 | config DAVINCI_AINTC |
131 | bool | |
132 | select GENERIC_IRQ_CHIP | |
133 | select IRQ_DOMAIN | |
134 | ||
0fc3d74c BG |
135 | config DAVINCI_CP_INTC |
136 | bool | |
137 | select GENERIC_IRQ_CHIP | |
138 | select IRQ_DOMAIN | |
139 | ||
350d71b9 SH |
140 | config DW_APB_ICTL |
141 | bool | |
e1588490 | 142 | select GENERIC_IRQ_CHIP |
350d71b9 SH |
143 | select IRQ_DOMAIN |
144 | ||
6ee532e2 LW |
145 | config FARADAY_FTINTC010 |
146 | bool | |
147 | select IRQ_DOMAIN | |
4f7799d9 | 148 | select GENERIC_IRQ_MULTI_HANDLER |
6ee532e2 LW |
149 | select SPARSE_IRQ |
150 | ||
9a7c4abd M |
151 | config HISILICON_IRQ_MBIGEN |
152 | bool | |
153 | select ARM_GIC_V3 | |
154 | select ARM_GIC_V3_ITS | |
9a7c4abd | 155 | |
b6ef9161 JH |
156 | config IMGPDC_IRQ |
157 | bool | |
158 | select GENERIC_IRQ_CHIP | |
159 | select IRQ_DOMAIN | |
160 | ||
5b978c10 LW |
161 | config IXP4XX_IRQ |
162 | bool | |
163 | select IRQ_DOMAIN | |
164 | select GENERIC_IRQ_MULTI_HANDLER | |
165 | select SPARSE_IRQ | |
166 | ||
da0abe1a RF |
167 | config MADERA_IRQ |
168 | tristate | |
169 | ||
67e38cf2 RB |
170 | config IRQ_MIPS_CPU |
171 | bool | |
172 | select GENERIC_IRQ_CHIP | |
3838a547 | 173 | select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
67e38cf2 | 174 | select IRQ_DOMAIN |
3838a547 | 175 | select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI |
18416e45 | 176 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
67e38cf2 | 177 | |
afc98d90 AS |
178 | config CLPS711X_IRQCHIP |
179 | bool | |
180 | depends on ARCH_CLPS711X | |
181 | select IRQ_DOMAIN | |
4f7799d9 | 182 | select GENERIC_IRQ_MULTI_HANDLER |
afc98d90 AS |
183 | select SPARSE_IRQ |
184 | default y | |
185 | ||
9b54470a SH |
186 | config OMPIC |
187 | bool | |
188 | ||
4db8e6d2 SK |
189 | config OR1K_PIC |
190 | bool | |
191 | select IRQ_DOMAIN | |
192 | ||
8598066c FB |
193 | config OMAP_IRQCHIP |
194 | bool | |
195 | select GENERIC_IRQ_CHIP | |
196 | select IRQ_DOMAIN | |
197 | ||
9dbd90f1 SH |
198 | config ORION_IRQCHIP |
199 | bool | |
200 | select IRQ_DOMAIN | |
4f7799d9 | 201 | select GENERIC_IRQ_MULTI_HANDLER |
9dbd90f1 | 202 | |
aaa8666a CB |
203 | config PIC32_EVIC |
204 | bool | |
205 | select GENERIC_IRQ_CHIP | |
206 | select IRQ_DOMAIN | |
207 | ||
981b58f6 | 208 | config JCORE_AIC |
3602ffde RF |
209 | bool "J-Core integrated AIC" if COMPILE_TEST |
210 | depends on OF | |
981b58f6 RF |
211 | select IRQ_DOMAIN |
212 | help | |
213 | Support for the J-Core integrated AIC. | |
214 | ||
d852e62a MS |
215 | config RDA_INTC |
216 | bool | |
217 | select IRQ_DOMAIN | |
218 | ||
44358048 MD |
219 | config RENESAS_INTC_IRQPIN |
220 | bool | |
221 | select IRQ_DOMAIN | |
222 | ||
fbc83b7f MD |
223 | config RENESAS_IRQC |
224 | bool | |
99c221df | 225 | select GENERIC_IRQ_CHIP |
fbc83b7f MD |
226 | select IRQ_DOMAIN |
227 | ||
07088484 LJ |
228 | config ST_IRQCHIP |
229 | bool | |
230 | select REGMAP | |
231 | select MFD_SYSCON | |
232 | help | |
233 | Enables SysCfg Controlled IRQs on STi based platforms. | |
234 | ||
4bba6689 MR |
235 | config TANGO_IRQ |
236 | bool | |
237 | select IRQ_DOMAIN | |
238 | select GENERIC_IRQ_CHIP | |
239 | ||
b06eb017 CR |
240 | config TB10X_IRQC |
241 | bool | |
242 | select IRQ_DOMAIN | |
243 | select GENERIC_IRQ_CHIP | |
244 | ||
d01f8633 DR |
245 | config TS4800_IRQ |
246 | tristate "TS-4800 IRQ controller" | |
247 | select IRQ_DOMAIN | |
0df337cf | 248 | depends on HAS_IOMEM |
d2b383dc | 249 | depends on SOC_IMX51 || COMPILE_TEST |
d01f8633 DR |
250 | help |
251 | Support for the TS-4800 FPGA IRQ controller | |
252 | ||
2389d501 LW |
253 | config VERSATILE_FPGA_IRQ |
254 | bool | |
255 | select IRQ_DOMAIN | |
256 | ||
257 | config VERSATILE_FPGA_IRQ_NR | |
258 | int | |
259 | default 4 | |
260 | depends on VERSATILE_FPGA_IRQ | |
26a8e96a MF |
261 | |
262 | config XTENSA_MX | |
263 | bool | |
264 | select IRQ_DOMAIN | |
50091212 | 265 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
96ca848e | 266 | |
0547dc78 ZLK |
267 | config XILINX_INTC |
268 | bool | |
269 | select IRQ_DOMAIN | |
270 | ||
96ca848e S |
271 | config IRQ_CROSSBAR |
272 | bool | |
273 | help | |
f54619f2 | 274 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
96ca848e S |
275 | The primary irqchip invokes the crossbar's callback which inturn allocates |
276 | a free irq and configures the IP. Thus the peripheral interrupts are | |
277 | routed to one of the free irqchip interrupt lines. | |
89323f8c GS |
278 | |
279 | config KEYSTONE_IRQ | |
280 | tristate "Keystone 2 IRQ controller IP" | |
281 | depends on ARCH_KEYSTONE | |
282 | help | |
283 | Support for Texas Instruments Keystone 2 IRQ controller IP which | |
284 | is part of the Keystone 2 IPC mechanism | |
8a19b8f1 AB |
285 | |
286 | config MIPS_GIC | |
287 | bool | |
bb11cff3 | 288 | select GENERIC_IRQ_IPI |
2af70a96 | 289 | select IRQ_DOMAIN_HIERARCHY |
8a19b8f1 | 290 | select MIPS_CM |
8a764482 | 291 | |
44e08e70 PB |
292 | config INGENIC_IRQ |
293 | bool | |
294 | depends on MACH_INGENIC | |
295 | default y | |
78c10e55 | 296 | |
8a764482 YS |
297 | config RENESAS_H8300H_INTC |
298 | bool | |
299 | select IRQ_DOMAIN | |
300 | ||
301 | config RENESAS_H8S_INTC | |
302 | bool | |
78c10e55 | 303 | select IRQ_DOMAIN |
e324c4dc SW |
304 | |
305 | config IMX_GPCV2 | |
306 | bool | |
307 | select IRQ_DOMAIN | |
308 | help | |
309 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | |
7e4ac676 OR |
310 | |
311 | config IRQ_MXS | |
312 | def_bool y if MACH_ASM9260 || ARCH_MXS | |
313 | select IRQ_DOMAIN | |
314 | select STMP_DEVICE | |
c27f29bb | 315 | |
19d99164 AB |
316 | config MSCC_OCELOT_IRQ |
317 | bool | |
318 | select IRQ_DOMAIN | |
319 | select GENERIC_IRQ_CHIP | |
320 | ||
a68a63cb TP |
321 | config MVEBU_GICP |
322 | bool | |
323 | ||
e0de91a9 TP |
324 | config MVEBU_ICU |
325 | bool | |
326 | ||
c27f29bb TP |
327 | config MVEBU_ODMI |
328 | bool | |
fa23b9d1 | 329 | select GENERIC_MSI_IRQ_DOMAIN |
9e2c986c | 330 | |
a109893b TP |
331 | config MVEBU_PIC |
332 | bool | |
333 | ||
61ce8d8d MR |
334 | config MVEBU_SEI |
335 | bool | |
336 | ||
b8f3ebe6 ML |
337 | config LS_SCFG_MSI |
338 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | |
339 | depends on PCI && PCI_MSI | |
b8f3ebe6 | 340 | |
9e2c986c MZ |
341 | config PARTITION_PERCPU |
342 | bool | |
0efacbba | 343 | |
44df427c NC |
344 | config EZNPS_GIC |
345 | bool "NPS400 Global Interrupt Manager (GIM)" | |
ffd565e3 | 346 | depends on ARC || (COMPILE_TEST && !64BIT) |
44df427c NC |
347 | select IRQ_DOMAIN |
348 | help | |
349 | Support the EZchip NPS400 global interrupt controller | |
e0720416 AT |
350 | |
351 | config STM32_EXTI | |
352 | bool | |
353 | select IRQ_DOMAIN | |
0e7d7807 | 354 | select GENERIC_IRQ_CHIP |
f20cc9b0 AVF |
355 | |
356 | config QCOM_IRQ_COMBINER | |
357 | bool "QCOM IRQ combiner support" | |
358 | depends on ARCH_QCOM && ACPI | |
f20cc9b0 AVF |
359 | select IRQ_DOMAIN_HIERARCHY |
360 | help | |
361 | Say yes here to add support for the IRQ combiner devices embedded | |
362 | in Qualcomm Technologies chips. | |
5ed34d3a MY |
363 | |
364 | config IRQ_UNIPHIER_AIDET | |
365 | bool "UniPhier AIDET support" if COMPILE_TEST | |
366 | depends on ARCH_UNIPHIER || COMPILE_TEST | |
367 | default ARCH_UNIPHIER | |
368 | select IRQ_DOMAIN_HIERARCHY | |
369 | help | |
370 | Support for the UniPhier AIDET (ARM Interrupt Detector). | |
c94fb639 | 371 | |
215f4cc0 JB |
372 | config MESON_IRQ_GPIO |
373 | bool "Meson GPIO Interrupt Multiplexer" | |
d9ee91c1 | 374 | depends on ARCH_MESON |
215f4cc0 JB |
375 | select IRQ_DOMAIN_HIERARCHY |
376 | help | |
377 | Support Meson SoC Family GPIO Interrupt Multiplexer | |
378 | ||
4235ff50 MD |
379 | config GOLDFISH_PIC |
380 | bool "Goldfish programmable interrupt controller" | |
381 | depends on MIPS && (GOLDFISH || COMPILE_TEST) | |
382 | select IRQ_DOMAIN | |
383 | help | |
384 | Say yes here to enable Goldfish interrupt controller driver used | |
385 | for Goldfish based virtual platforms. | |
386 | ||
f55c73ae AS |
387 | config QCOM_PDC |
388 | bool "QCOM PDC" | |
389 | depends on ARCH_QCOM | |
f55c73ae AS |
390 | select IRQ_DOMAIN_HIERARCHY |
391 | help | |
392 | Power Domain Controller driver to manage and configure wakeup | |
393 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. | |
394 | ||
d8a5f5f7 GR |
395 | config CSKY_MPINTC |
396 | bool "C-SKY Multi Processor Interrupt Controller" | |
397 | depends on CSKY | |
398 | help | |
399 | Say yes here to enable C-SKY SMP interrupt controller driver used | |
400 | for C-SKY SMP system. | |
401 | In fact it's not mmio map in hw and it use ld/st to visit the | |
402 | controller's register inside CPU. | |
403 | ||
edff1b48 GR |
404 | config CSKY_APB_INTC |
405 | bool "C-SKY APB Interrupt Controller" | |
406 | depends on CSKY | |
407 | help | |
408 | Say yes here to enable C-SKY APB interrupt controller driver used | |
409 | by C-SKY single core SOC system. It use mmio map apb-bus to visit | |
410 | the controller's register. | |
411 | ||
0136afa0 LS |
412 | config IMX_IRQSTEER |
413 | bool "i.MX IRQSTEER support" | |
414 | depends on ARCH_MXC || COMPILE_TEST | |
415 | default ARCH_MXC | |
416 | select IRQ_DOMAIN | |
417 | help | |
418 | Support for the i.MX IRQSTEER interrupt multiplexer/remapper. | |
419 | ||
9e543e22 JY |
420 | config LS1X_IRQ |
421 | bool "Loongson-1 Interrupt Controller" | |
422 | depends on MACH_LOONGSON32 | |
423 | default y | |
424 | select IRQ_DOMAIN | |
425 | select GENERIC_IRQ_CHIP | |
426 | help | |
427 | Support for the Loongson-1 platform Interrupt Controller. | |
428 | ||
cd844b07 LV |
429 | config TI_SCI_INTR_IRQCHIP |
430 | bool | |
431 | depends on TI_SCI_PROTOCOL | |
432 | select IRQ_DOMAIN_HIERARCHY | |
433 | help | |
434 | This enables the irqchip driver support for K3 Interrupt router | |
435 | over TI System Control Interface available on some new TI's SoCs. | |
436 | If you wish to use interrupt router irq resources managed by the | |
437 | TI System Controller, say Y here. Otherwise, say N. | |
438 | ||
9f1463b8 LV |
439 | config TI_SCI_INTA_IRQCHIP |
440 | bool | |
441 | depends on TI_SCI_PROTOCOL | |
442 | select IRQ_DOMAIN_HIERARCHY | |
f011df61 | 443 | select TI_SCI_INTA_MSI_DOMAIN |
9f1463b8 LV |
444 | help |
445 | This enables the irqchip driver support for K3 Interrupt aggregator | |
446 | over TI System Control Interface available on some new TI's SoCs. | |
447 | If you wish to use interrupt aggregator irq resources managed by the | |
448 | TI System Controller, say Y here. Otherwise, say N. | |
449 | ||
c94fb639 | 450 | endmenu |
8237f8bc CH |
451 | |
452 | config SIFIVE_PLIC | |
453 | bool "SiFive Platform-Level Interrupt Controller" | |
454 | depends on RISCV | |
455 | help | |
456 | This enables support for the PLIC chip found in SiFive (and | |
457 | potentially other) RISC-V systems. The PLIC controls devices | |
458 | interrupts and connects them to each core's local interrupt | |
459 | controller. Aside from timer and software interrupts, all other | |
460 | interrupt sources are subordinate to the PLIC. | |
461 | ||
462 | If you don't know what to do here, say Y. |