[linux-block.git] / drivers / irqchip / Kconfig

# SPDX-License-Identifier: GPL-2.0-only
menu "IRQ chip support"

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC

config ARM_GIC_MAX_NR
	int
	depends on ARM_GIC
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_V3_ITS
	bool
	select GENERIC_MSI_IRQ_DOMAIN
	default ARM_GIC_V3

config ARM_GIC_V3_ITS_PCI
	bool
	depends on ARM_GIC_V3_ITS
	depends on PCI
	depends on PCI_MSI
	default ARM_GIC_V3_ITS

config ARM_GIC_V3_ITS_FSL_MC
	bool
	depends on ARM_GIC_V3_ITS
	depends on FSL_MC_BUS
	default ARM_GIC_V3_ITS

config ARM_NVIC
	bool
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config AL_FIC
	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
	depends on OF || COMPILE_TEST
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	help
	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7038_L1_IRQ
	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
	depends on ARCH_BRCMSTB || BMIPS_GENERIC
	default ARCH_BRCMSTB || BMIPS_GENERIC
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7120_L2_IRQ
	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
	depends on ARCH_BRCMSTB || BMIPS_GENERIC
	default ARCH_BRCMSTB || BMIPS_GENERIC
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	tristate "Broadcom STB generic L2 interrupt controller driver"
	depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
	default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DAVINCI_AINTC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DAVINCI_CP_INTC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN_HIERARCHY

config FARADAY_FTINTC010
	bool
	select IRQ_DOMAIN
	select SPARSE_IRQ

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IXP4XX_IRQ
	bool
	select IRQ_DOMAIN
	select SPARSE_IRQ

config MADERA_IRQ
	tristate

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select SPARSE_IRQ
	default y

config OMPIC
	bool

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC" if COMPILE_TEST
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RDA_INTC
	bool
	select IRQ_DOMAIN

config RENESAS_INTC_IRQPIN
	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
	select IRQ_DOMAIN
	help
	  Enable support for the Renesas Interrupt Controller for external
	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.

config RENESAS_IRQC
	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	help
	  Enable support for the Renesas Interrupt Controller for external
	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.

config RENESAS_RZA1_IRQC
	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
	select IRQ_DOMAIN_HIERARCHY
	help
	  Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
	  to 8 external interrupts with configurable sense select.

config SL28CPLD_INTC
	bool "Kontron sl28cpld IRQ controller"
	depends on MFD_SL28CPLD=y || COMPILE_TEST
	select REGMAP_IRQ
	help
	  Interrupt controller driver for the board management controller
	  found on the Kontron sl28 CPLD.

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config SUN4I_INTC
	bool

config SUN6I_R_INTC
	bool
	select IRQ_DOMAIN_HIERARCHY
	select IRQ_FASTEOI_HIERARCHY_HANDLERS

config SUNXI_NMI_INTC
	bool
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config XILINX_INTC
	bool "Xilinx Interrupt Controller IP"
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the Xilinx Interrupt Controller IP core.
	  This is used as a primary controller with MicroBlaze and can also
	  be used as a secondary chained controller on other platforms.

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config INGENIC_TCU_IRQ
	bool "Ingenic JZ47xx TCU interrupt controller"
	default MACH_INGENIC
	depends on MIPS || COMPILE_TEST
	select MFD_SYSCON
	select GENERIC_IRQ_CHIP
	help
	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
	  JZ47xx SoCs.

	  If unsure, say N.

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MSCC_OCELOT_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config MVEBU_GICP
	bool

config MVEBU_ICU
	bool

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN

config MVEBU_PIC
	bool

config MVEBU_SEI
        bool

config LS_EXTIRQ
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	select MFD_SYSCON

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config STM32_EXTI
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config QCOM_IRQ_COMBINER
	bool "QCOM IRQ combiner support"
	depends on ARCH_QCOM && ACPI
	select IRQ_DOMAIN_HIERARCHY
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Qualcomm Technologies chips.

config IRQ_UNIPHIER_AIDET
	bool "UniPhier AIDET support" if COMPILE_TEST
	depends on ARCH_UNIPHIER || COMPILE_TEST
	default ARCH_UNIPHIER
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the UniPhier AIDET (ARM Interrupt Detector).

config MESON_IRQ_GPIO
       tristate "Meson GPIO Interrupt Multiplexer"
       depends on ARCH_MESON || COMPILE_TEST
       default ARCH_MESON
       select IRQ_DOMAIN_HIERARCHY
       help
         Support Meson SoC Family GPIO Interrupt Multiplexer

config GOLDFISH_PIC
       bool "Goldfish programmable interrupt controller"
       depends on MIPS && (GOLDFISH || COMPILE_TEST)
       select GENERIC_IRQ_CHIP
       select IRQ_DOMAIN
       help
         Say yes here to enable Goldfish interrupt controller driver used
         for Goldfish based virtual platforms.

config QCOM_PDC
	tristate "QCOM PDC"
	depends on ARCH_QCOM
	select IRQ_DOMAIN_HIERARCHY
	help
	  Power Domain Controller driver to manage and configure wakeup
	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.

config QCOM_MPM
	tristate "QCOM MPM"
	depends on ARCH_QCOM
	depends on MAILBOX
	select IRQ_DOMAIN_HIERARCHY
	help
	  MSM Power Manager driver to manage and configure wakeup
	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.

config CSKY_MPINTC
	bool
	depends on CSKY
	help
	  Say yes here to enable C-SKY SMP interrupt controller driver used
	  for C-SKY SMP system.
	  In fact it's not mmio map in hardware and it uses ld/st to visit the
	  controller's register inside CPU.

config CSKY_APB_INTC
	bool "C-SKY APB Interrupt Controller"
	depends on CSKY
	help
	  Say yes here to enable C-SKY APB interrupt controller driver used
	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
	  the controller's register.

config IMX_IRQSTEER
	bool "i.MX IRQSTEER support"
	depends on ARCH_MXC || COMPILE_TEST
	default ARCH_MXC
	select IRQ_DOMAIN
	help
	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.

config IMX_INTMUX
	bool "i.MX INTMUX support" if COMPILE_TEST
	default y if ARCH_MXC
	select IRQ_DOMAIN
	help
	  Support for the i.MX INTMUX interrupt multiplexer.

config LS1X_IRQ
	bool "Loongson-1 Interrupt Controller"
	depends on MACH_LOONGSON32
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson-1 platform Interrupt Controller.

config TI_SCI_INTR_IRQCHIP
	bool
	depends on TI_SCI_PROTOCOL
	select IRQ_DOMAIN_HIERARCHY
	help
	  This enables the irqchip driver support for K3 Interrupt router
	  over TI System Control Interface available on some new TI's SoCs.
	  If you wish to use interrupt router irq resources managed by the
	  TI System Controller, say Y here. Otherwise, say N.

config TI_SCI_INTA_IRQCHIP
	bool
	depends on TI_SCI_PROTOCOL
	select IRQ_DOMAIN_HIERARCHY
	select TI_SCI_INTA_MSI_DOMAIN
	help
	  This enables the irqchip driver support for K3 Interrupt aggregator
	  over TI System Control Interface available on some new TI's SoCs.
	  If you wish to use interrupt aggregator irq resources managed by the
	  TI System Controller, say Y here. Otherwise, say N.

config TI_PRUSS_INTC
	tristate
	depends on TI_PRUSS
	default TI_PRUSS
	select IRQ_DOMAIN
	help
	  This enables support for the PRU-ICSS Local Interrupt Controller
	  present within a PRU-ICSS subsystem present on various TI SoCs.
	  The PRUSS INTC enables various interrupts to be routed to multiple
	  different processors within the SoC.

config RISCV_INTC
	bool "RISC-V Local Interrupt Controller"
	depends on RISCV
	default y
	help
	   This enables support for the per-HART local interrupt controller
	   found in standard RISC-V systems.  The per-HART local interrupt
	   controller handles timer interrupts, software interrupts, and
	   hardware interrupts. Without a per-HART local interrupt controller,
	   a RISC-V system will be unable to handle any interrupts.

	   If you don't know what to do here, say Y.

config SIFIVE_PLIC
	bool "SiFive Platform-Level Interrupt Controller"
	depends on RISCV
	select IRQ_DOMAIN_HIERARCHY
	help
	   This enables support for the PLIC chip found in SiFive (and
	   potentially other) RISC-V systems.  The PLIC controls devices
	   interrupts and connects them to each core's local interrupt
	   controller.  Aside from timer and software interrupts, all other
	   interrupt sources are subordinate to the PLIC.

	   If you don't know what to do here, say Y.

config EXYNOS_IRQ_COMBINER
	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Samsung Exynos chips.

config LOONGSON_LIOINTC
	bool "Loongson Local I/O Interrupt Controller"
	depends on MACH_LOONGSON64
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson Local I/O Interrupt Controller.

config LOONGSON_HTPIC
	bool "Loongson3 HyperTransport PIC Controller"
	depends on MACH_LOONGSON64 && MIPS
	default y
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP
	help
	  Support for the Loongson-3 HyperTransport PIC Controller.

config LOONGSON_HTVEC
	bool "Loongson HyperTransport Interrupt Vector Controller"
	depends on MACH_LOONGSON64
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the Loongson HyperTransport Interrupt Vector Controller.

config LOONGSON_PCH_PIC
	bool "Loongson PCH PIC Controller"
	depends on MACH_LOONGSON64 || COMPILE_TEST
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	select IRQ_FASTEOI_HIERARCHY_HANDLERS
	help
	  Support for the Loongson PCH PIC Controller.

config LOONGSON_PCH_MSI
	bool "Loongson PCH MSI Controller"
	depends on MACH_LOONGSON64 || COMPILE_TEST
	depends on PCI
	default MACH_LOONGSON64
	select IRQ_DOMAIN_HIERARCHY
	select PCI_MSI
	help
	  Support for the Loongson PCH MSI Controller.

config MST_IRQ
	bool "MStar Interrupt Controller"
	depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
	default ARCH_MEDIATEK
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support MStar Interrupt Controller.

config WPCM450_AIC
	bool "Nuvoton WPCM450 Advanced Interrupt Controller"
	depends on ARCH_WPCM450
	help
	  Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.

config IRQ_IDT3243X
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config APPLE_AIC
	bool "Apple Interrupt Controller (AIC)"
	depends on ARM64
	depends on ARCH_APPLE || COMPILE_TEST
	help
	  Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
	  such as the M1.

config MCHP_EIC
	bool "Microchip External Interrupt Controller"
	depends on ARCH_AT91 || COMPILE_TEST
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for Microchip External Interrupt Controller.

endmenu
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
c94fb639 RD	2	menu "IRQ chip support"
c94fb639 RD	3
f6e916b8 TP	4	config IRQCHIP
	5	def_bool y
	6	depends on OF_IRQ
	7
81243e44 RH	8	config ARM_GIC
81243e44 RH	9	bool
9a1091ef	10	select IRQ_DOMAIN_HIERARCHY
0c9e4982	11	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44	12
9c8edddf JH	13	config ARM_GIC_PM
	14	bool
	15	depends on PM
	16	select ARM_GIC
9c8edddf	17
a27d21e0 LW	18	config ARM_GIC_MAX_NR
a27d21e0 LW	19	int
70265523	20	depends on ARM_GIC
a27d21e0 LW	21	default 2 if ARCH_REALVIEW
	22	default 1
	23
853a33ce SS	24	config ARM_GIC_V2M
853a33ce SS	25	bool
3ee80364 AB	26	depends on PCI
	27	select ARM_GIC
	28	select PCI_MSI
853a33ce	29
81243e44 RH	30	config GIC_NON_BANKED
	31	bool
	32
021f6537 MZ	33	config ARM_GIC_V3
021f6537 MZ	34	bool
443acc4f	35	select IRQ_DOMAIN_HIERARCHY
e3825ba1	36	select PARTITION_PERCPU
956ae91a	37	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537	38
19812729 MZ	39	config ARM_GIC_V3_ITS
19812729 MZ	40	bool
29f41139 MZ	41	select GENERIC_MSI_IRQ_DOMAIN
	42	default ARM_GIC_V3
	43
	44	config ARM_GIC_V3_ITS_PCI
	45	bool
	46	depends on ARM_GIC_V3_ITS
3ee80364 AB	47	depends on PCI
3ee80364 AB	48	depends on PCI_MSI
29f41139	49	default ARM_GIC_V3_ITS
021f6537	50
7afe031c BP	51	config ARM_GIC_V3_ITS_FSL_MC
	52	bool
	53	depends on ARM_GIC_V3_ITS
	54	depends on FSL_MC_BUS
	55	default ARM_GIC_V3_ITS
	56
292ec080 UKK	57	config ARM_NVIC
292ec080 UKK	58	bool
2d9f59f7	59	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	60	select GENERIC_IRQ_CHIP
292ec080 UKK	61
44430ec0 RH	62	config ARM_VIC
	63	bool
	64	select IRQ_DOMAIN
44430ec0 RH	65
	66	config ARM_VIC_NR
	67	int
	68	default 4 if ARCH_S5PV210
44430ec0 RH	69	default 2
	70	depends on ARM_VIC
	71	help
	72	The maximum number of VICs available in the system, for
	73	power management.
	74
fed6d336 TP	75	config ARMADA_370_XP_IRQ
fed6d336 TP	76	bool
fed6d336	77	select GENERIC_IRQ_CHIP
3ee80364	78	select PCI_MSI if PCI
e31793a3	79	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336	80
e6b78f2c AT	81	config ALPINE_MSI
e6b78f2c AT	82	bool
3ee80364 AB	83	depends on PCI
3ee80364 AB	84	select PCI_MSI
e6b78f2c	85	select GENERIC_IRQ_CHIP
e6b78f2c	86
1eb77c3b TS	87	config AL_FIC
	88	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
	89	depends on OF \|\| COMPILE_TEST
	90	select GENERIC_IRQ_CHIP
	91	select IRQ_DOMAIN
	92	help
	93	Support Amazon's Annapurna Labs Fabric Interrupt Controller.
	94
b1479ebb BB	95	config ATMEL_AIC_IRQ
	96	bool
	97	select GENERIC_IRQ_CHIP
	98	select IRQ_DOMAIN
b1479ebb BB	99	select SPARSE_IRQ
	100
	101	config ATMEL_AIC5_IRQ
	102	bool
	103	select GENERIC_IRQ_CHIP
	104	select IRQ_DOMAIN
b1479ebb BB	105	select SPARSE_IRQ
b1479ebb BB	106
0509cfde RB	107	config I8259
	108	bool
	109	select IRQ_DOMAIN
	110
c7c42ec2 SA	111	config BCM6345_L1_IRQ
	112	bool
	113	select GENERIC_IRQ_CHIP
	114	select IRQ_DOMAIN
d0ed5e8e	115	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2	116
5f7f0317	117	config BCM7038_L1_IRQ
c057c799 FF	118	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
	119	depends on ARCH_BRCMSTB \|\| BMIPS_GENERIC
	120	default ARCH_BRCMSTB \|\| BMIPS_GENERIC
5f7f0317 KC	121	select GENERIC_IRQ_CHIP
5f7f0317 KC	122	select IRQ_DOMAIN
b8d9884a	123	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317	124
a4fcbb86	125	config BCM7120_L2_IRQ
3ac268d5 FF	126	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
	127	depends on ARCH_BRCMSTB \|\| BMIPS_GENERIC
	128	default ARCH_BRCMSTB \|\| BMIPS_GENERIC
a4fcbb86 KC	129	select GENERIC_IRQ_CHIP
	130	select IRQ_DOMAIN
	131
7f646e92	132	config BRCMSTB_L2_IRQ
51d9db5c FF	133	tristate "Broadcom STB generic L2 interrupt controller driver"
	134	depends on ARCH_BCM2835 \|\| ARCH_BRCMSTB \|\| BMIPS_GENERIC
	135	default ARCH_BCM2835 \|\| ARCH_BRCMSTB \|\| BMIPS_GENERIC
7f646e92 FF	136	select GENERIC_IRQ_CHIP
	137	select IRQ_DOMAIN
	138
0145beed BG	139	config DAVINCI_AINTC
	140	bool
	141	select GENERIC_IRQ_CHIP
	142	select IRQ_DOMAIN
	143
0fc3d74c BG	144	config DAVINCI_CP_INTC
	145	bool
	146	select GENERIC_IRQ_CHIP
	147	select IRQ_DOMAIN
	148
350d71b9 SH	149	config DW_APB_ICTL
350d71b9 SH	150	bool
e1588490	151	select GENERIC_IRQ_CHIP
54a38440	152	select IRQ_DOMAIN_HIERARCHY
350d71b9	153
6ee532e2 LW	154	config FARADAY_FTINTC010
	155	bool
	156	select IRQ_DOMAIN
6ee532e2 LW	157	select SPARSE_IRQ
6ee532e2 LW	158
9a7c4abd M	159	config HISILICON_IRQ_MBIGEN
	160	bool
	161	select ARM_GIC_V3
	162	select ARM_GIC_V3_ITS
9a7c4abd	163
b6ef9161 JH	164	config IMGPDC_IRQ
	165	bool
	166	select GENERIC_IRQ_CHIP
	167	select IRQ_DOMAIN
	168
5b978c10 LW	169	config IXP4XX_IRQ
	170	bool
	171	select IRQ_DOMAIN
5b978c10 LW	172	select SPARSE_IRQ
5b978c10 LW	173
da0abe1a RF	174	config MADERA_IRQ
	175	tristate
	176
67e38cf2 RB	177	config IRQ_MIPS_CPU
	178	bool
	179	select GENERIC_IRQ_CHIP
3838a547	180	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2	181	select IRQ_DOMAIN
18416e45	182	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2	183
afc98d90 AS	184	config CLPS711X_IRQCHIP
	185	bool
	186	depends on ARCH_CLPS711X
	187	select IRQ_DOMAIN
afc98d90 AS	188	select SPARSE_IRQ
	189	default y
	190
9b54470a SH	191	config OMPIC
	192	bool
	193
4db8e6d2 SK	194	config OR1K_PIC
	195	bool
	196	select IRQ_DOMAIN
	197
8598066c FB	198	config OMAP_IRQCHIP
	199	bool
	200	select GENERIC_IRQ_CHIP
	201	select IRQ_DOMAIN
	202
9dbd90f1 SH	203	config ORION_IRQCHIP
	204	bool
	205	select IRQ_DOMAIN
9dbd90f1	206
aaa8666a CB	207	config PIC32_EVIC
	208	bool
	209	select GENERIC_IRQ_CHIP
	210	select IRQ_DOMAIN
	211
981b58f6	212	config JCORE_AIC
3602ffde RF	213	bool "J-Core integrated AIC" if COMPILE_TEST
3602ffde RF	214	depends on OF
981b58f6 RF	215	select IRQ_DOMAIN
	216	help
	217	Support for the J-Core integrated AIC.
	218
d852e62a MS	219	config RDA_INTC
	220	bool
	221	select IRQ_DOMAIN
	222
44358048	223	config RENESAS_INTC_IRQPIN
02d7e041	224	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
44358048	225	select IRQ_DOMAIN
02d7e041 GU	226	help
	227	Enable support for the Renesas Interrupt Controller for external
	228	interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
44358048	229
fbc83b7f	230	config RENESAS_IRQC
72d44c0c	231	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
99c221df	232	select GENERIC_IRQ_CHIP
fbc83b7f	233	select IRQ_DOMAIN
02d7e041 GU	234	help
02d7e041 GU	235	Enable support for the Renesas Interrupt Controller for external
72d44c0c	236	devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
fbc83b7f	237
a644ccb8	238	config RENESAS_RZA1_IRQC
02d7e041	239	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
a644ccb8	240	select IRQ_DOMAIN_HIERARCHY
02d7e041 GU	241	help
	242	Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
	243	to 8 external interrupts with configurable sense select.
a644ccb8	244
03ac990e MW	245	config SL28CPLD_INTC
	246	bool "Kontron sl28cpld IRQ controller"
	247	depends on MFD_SL28CPLD=y \|\| COMPILE_TEST
	248	select REGMAP_IRQ
	249	help
	250	Interrupt controller driver for the board management controller
	251	found on the Kontron sl28 CPLD.
	252
07088484 LJ	253	config ST_IRQCHIP
	254	bool
	255	select REGMAP
	256	select MFD_SYSCON
	257	help
	258	Enables SysCfg Controlled IRQs on STi based platforms.
	259
d421fd6d SH	260	config SUN4I_INTC
	261	bool
	262
	263	config SUN6I_R_INTC
	264	bool
	265	select IRQ_DOMAIN_HIERARCHY
	266	select IRQ_FASTEOI_HIERARCHY_HANDLERS
	267
	268	config SUNXI_NMI_INTC
	269	bool
	270	select GENERIC_IRQ_CHIP
	271
b06eb017 CR	272	config TB10X_IRQC
	273	bool
	274	select IRQ_DOMAIN
	275	select GENERIC_IRQ_CHIP
	276
d01f8633 DR	277	config TS4800_IRQ
	278	tristate "TS-4800 IRQ controller"
	279	select IRQ_DOMAIN
0df337cf	280	depends on HAS_IOMEM
d2b383dc	281	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	282	help
	283	Support for the TS-4800 FPGA IRQ controller
	284
2389d501 LW	285	config VERSATILE_FPGA_IRQ
	286	bool
	287	select IRQ_DOMAIN
	288
	289	config VERSATILE_FPGA_IRQ_NR
	290	int
	291	default 4
	292	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	293
	294	config XTENSA_MX
	295	bool
	296	select IRQ_DOMAIN
50091212	297	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e	298
0547dc78	299	config XILINX_INTC
debf69cf	300	bool "Xilinx Interrupt Controller IP"
b84dc7f0	301	depends on OF
0547dc78	302	select IRQ_DOMAIN
debf69cf RH	303	help
	304	Support for the Xilinx Interrupt Controller IP core.
	305	This is used as a primary controller with MicroBlaze and can also
	306	be used as a secondary chained controller on other platforms.
0547dc78	307
96ca848e S	308	config IRQ_CROSSBAR
	309	bool
	310	help
f54619f2	311	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	312	The primary irqchip invokes the crossbar's callback which inturn allocates
	313	a free irq and configures the IP. Thus the peripheral interrupts are
	314	routed to one of the free irqchip interrupt lines.
89323f8c GS	315
	316	config KEYSTONE_IRQ
	317	tristate "Keystone 2 IRQ controller IP"
	318	depends on ARCH_KEYSTONE
	319	help
	320	Support for Texas Instruments Keystone 2 IRQ controller IP which
	321	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	322
	323	config MIPS_GIC
	324	bool
bb11cff3	325	select GENERIC_IRQ_IPI
8a19b8f1	326	select MIPS_CM
8a764482	327
44e08e70 PB	328	config INGENIC_IRQ
	329	bool
	330	depends on MACH_INGENIC
	331	default y
78c10e55	332
9536eba0 PC	333	config INGENIC_TCU_IRQ
	334	bool "Ingenic JZ47xx TCU interrupt controller"
	335	default MACH_INGENIC
	336	depends on MIPS \|\| COMPILE_TEST
	337	select MFD_SYSCON
8084499b	338	select GENERIC_IRQ_CHIP
9536eba0 PC	339	help
	340	Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
	341	JZ47xx SoCs.
	342
	343	If unsure, say N.
	344
e324c4dc SW	345	config IMX_GPCV2
	346	bool
	347	select IRQ_DOMAIN
	348	help
	349	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	350
	351	config IRQ_MXS
	352	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	353	select IRQ_DOMAIN
	354	select STMP_DEVICE
c27f29bb	355
19d99164 AB	356	config MSCC_OCELOT_IRQ
	357	bool
	358	select IRQ_DOMAIN
	359	select GENERIC_IRQ_CHIP
	360
a68a63cb TP	361	config MVEBU_GICP
	362	bool
	363
e0de91a9 TP	364	config MVEBU_ICU
	365	bool
	366
c27f29bb TP	367	config MVEBU_ODMI
c27f29bb TP	368	bool
fa23b9d1	369	select GENERIC_MSI_IRQ_DOMAIN
9e2c986c	370
a109893b TP	371	config MVEBU_PIC
	372	bool
	373
61ce8d8d MR	374	config MVEBU_SEI
	375	bool
	376
0dcd9f87 RV	377	config LS_EXTIRQ
	378	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	379	select MFD_SYSCON
	380
b8f3ebe6 ML	381	config LS_SCFG_MSI
	382	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	383	depends on PCI && PCI_MSI
b8f3ebe6	384
9e2c986c MZ	385	config PARTITION_PERCPU
9e2c986c MZ	386	bool
0efacbba	387
e0720416 AT	388	config STM32_EXTI
	389	bool
	390	select IRQ_DOMAIN
0e7d7807	391	select GENERIC_IRQ_CHIP
f20cc9b0 AVF	392
	393	config QCOM_IRQ_COMBINER
	394	bool "QCOM IRQ combiner support"
	395	depends on ARCH_QCOM && ACPI
f20cc9b0 AVF	396	select IRQ_DOMAIN_HIERARCHY
	397	help
	398	Say yes here to add support for the IRQ combiner devices embedded
	399	in Qualcomm Technologies chips.
5ed34d3a MY	400
	401	config IRQ_UNIPHIER_AIDET
	402	bool "UniPhier AIDET support" if COMPILE_TEST
	403	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
	404	default ARCH_UNIPHIER
	405	select IRQ_DOMAIN_HIERARCHY
	406	help
	407	Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639	408
215f4cc0	409	config MESON_IRQ_GPIO
a947aa00 NA	410	tristate "Meson GPIO Interrupt Multiplexer"
	411	depends on ARCH_MESON \|\| COMPILE_TEST
	412	default ARCH_MESON
215f4cc0 JB	413	select IRQ_DOMAIN_HIERARCHY
	414	help
	415	Support Meson SoC Family GPIO Interrupt Multiplexer
	416
4235ff50 MD	417	config GOLDFISH_PIC
	418	bool "Goldfish programmable interrupt controller"
	419	depends on MIPS && (GOLDFISH \|\| COMPILE_TEST)
969ac78d	420	select GENERIC_IRQ_CHIP
4235ff50 MD	421	select IRQ_DOMAIN
	422	help
	423	Say yes here to enable Goldfish interrupt controller driver used
	424	for Goldfish based virtual platforms.
	425
f55c73ae	426	config QCOM_PDC
4acd8a4b	427	tristate "QCOM PDC"
f55c73ae	428	depends on ARCH_QCOM
f55c73ae AS	429	select IRQ_DOMAIN_HIERARCHY
	430	help
	431	Power Domain Controller driver to manage and configure wakeup
	432	IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
	433
a6199bb5 SG	434	config QCOM_MPM
	435	tristate "QCOM MPM"
	436	depends on ARCH_QCOM
fa4dcc88	437	depends on MAILBOX
a6199bb5 SG	438	select IRQ_DOMAIN_HIERARCHY
	439	help
	440	MSM Power Manager driver to manage and configure wakeup
	441	IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
	442
d8a5f5f7	443	config CSKY_MPINTC
be1abc5b	444	bool
d8a5f5f7 GR	445	depends on CSKY
	446	help
	447	Say yes here to enable C-SKY SMP interrupt controller driver used
	448	for C-SKY SMP system.
656b42de	449	In fact it's not mmio map in hardware and it uses ld/st to visit the
d8a5f5f7 GR	450	controller's register inside CPU.
d8a5f5f7 GR	451
edff1b48 GR	452	config CSKY_APB_INTC
	453	bool "C-SKY APB Interrupt Controller"
	454	depends on CSKY
	455	help
	456	Say yes here to enable C-SKY APB interrupt controller driver used
656b42de	457	by C-SKY single core SOC system. It uses mmio map apb-bus to visit
edff1b48 GR	458	the controller's register.
edff1b48 GR	459
0136afa0 LS	460	config IMX_IRQSTEER
	461	bool "i.MX IRQSTEER support"
	462	depends on ARCH_MXC \|\| COMPILE_TEST
	463	default ARCH_MXC
	464	select IRQ_DOMAIN
	465	help
	466	Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
	467
2fbb1396	468	config IMX_INTMUX
a890caeb GU	469	bool "i.MX INTMUX support" if COMPILE_TEST
a890caeb GU	470	default y if ARCH_MXC
2fbb1396 JZ	471	select IRQ_DOMAIN
	472	help
	473	Support for the i.MX INTMUX interrupt multiplexer.
	474
9e543e22 JY	475	config LS1X_IRQ
	476	bool "Loongson-1 Interrupt Controller"
	477	depends on MACH_LOONGSON32
	478	default y
	479	select IRQ_DOMAIN
	480	select GENERIC_IRQ_CHIP
	481	help
	482	Support for the Loongson-1 platform Interrupt Controller.
	483
cd844b07 LV	484	config TI_SCI_INTR_IRQCHIP
	485	bool
	486	depends on TI_SCI_PROTOCOL
	487	select IRQ_DOMAIN_HIERARCHY
	488	help
	489	This enables the irqchip driver support for K3 Interrupt router
	490	over TI System Control Interface available on some new TI's SoCs.
	491	If you wish to use interrupt router irq resources managed by the
	492	TI System Controller, say Y here. Otherwise, say N.
	493
9f1463b8 LV	494	config TI_SCI_INTA_IRQCHIP
	495	bool
	496	depends on TI_SCI_PROTOCOL
	497	select IRQ_DOMAIN_HIERARCHY
f011df61	498	select TI_SCI_INTA_MSI_DOMAIN
9f1463b8 LV	499	help
	500	This enables the irqchip driver support for K3 Interrupt aggregator
	501	over TI System Control Interface available on some new TI's SoCs.
	502	If you wish to use interrupt aggregator irq resources managed by the
	503	TI System Controller, say Y here. Otherwise, say N.
	504
04e2d1e0	505	config TI_PRUSS_INTC
b8e594fa SA	506	tristate
	507	depends on TI_PRUSS
	508	default TI_PRUSS
04e2d1e0 GJ	509	select IRQ_DOMAIN
	510	help
	511	This enables support for the PRU-ICSS Local Interrupt Controller
	512	present within a PRU-ICSS subsystem present on various TI SoCs.
	513	The PRUSS INTC enables various interrupts to be routed to multiple
	514	different processors within the SoC.
	515
6b7ce892 AP	516	config RISCV_INTC
	517	bool "RISC-V Local Interrupt Controller"
	518	depends on RISCV
	519	default y
	520	help
	521	This enables support for the per-HART local interrupt controller
	522	found in standard RISC-V systems. The per-HART local interrupt
	523	controller handles timer interrupts, software interrupts, and
	524	hardware interrupts. Without a per-HART local interrupt controller,
	525	a RISC-V system will be unable to handle any interrupts.
	526
	527	If you don't know what to do here, say Y.
	528
8237f8bc CH	529	config SIFIVE_PLIC
	530	bool "SiFive Platform-Level Interrupt Controller"
	531	depends on RISCV
466008f9	532	select IRQ_DOMAIN_HIERARCHY
8237f8bc CH	533	help
	534	This enables support for the PLIC chip found in SiFive (and
	535	potentially other) RISC-V systems. The PLIC controls devices
	536	interrupts and connects them to each core's local interrupt
	537	controller. Aside from timer and software interrupts, all other
	538	interrupt sources are subordinate to the PLIC.
	539
	540	If you don't know what to do here, say Y.
01493855	541
b74416db HK	542	config EXYNOS_IRQ_COMBINER
	543	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
	544	depends on (ARCH_EXYNOS && ARM) \|\| COMPILE_TEST
	545	help
	546	Say yes here to add support for the IRQ combiner devices embedded
	547	in Samsung Exynos chips.
	548
dbb15226 JY	549	config LOONGSON_LIOINTC
	550	bool "Loongson Local I/O Interrupt Controller"
	551	depends on MACH_LOONGSON64
	552	default y
	553	select IRQ_DOMAIN
	554	select GENERIC_IRQ_CHIP
	555	help
	556	Support for the Loongson Local I/O Interrupt Controller.
	557
a93f1d90 JY	558	config LOONGSON_HTPIC
a93f1d90 JY	559	bool "Loongson3 HyperTransport PIC Controller"
987a3e03	560	depends on MACH_LOONGSON64 && MIPS
a93f1d90 JY	561	default y
	562	select IRQ_DOMAIN
	563	select GENERIC_IRQ_CHIP
a93f1d90 JY	564	help
	565	Support for the Loongson-3 HyperTransport PIC Controller.
	566
818e915f	567	config LOONGSON_HTVEC
987a3e03	568	bool "Loongson HyperTransport Interrupt Vector Controller"
d77aeb5d	569	depends on MACH_LOONGSON64
818e915f JY	570	default MACH_LOONGSON64
	571	select IRQ_DOMAIN_HIERARCHY
	572	help
987a3e03	573	Support for the Loongson HyperTransport Interrupt Vector Controller.
818e915f	574
ef8c01eb JY	575	config LOONGSON_PCH_PIC
	576	bool "Loongson PCH PIC Controller"
	577	depends on MACH_LOONGSON64 \|\| COMPILE_TEST
	578	default MACH_LOONGSON64
	579	select IRQ_DOMAIN_HIERARCHY
	580	select IRQ_FASTEOI_HIERARCHY_HANDLERS
	581	help
	582	Support for the Loongson PCH PIC Controller.
	583
632dcc2c	584	config LOONGSON_PCH_MSI
a23df9a4	585	bool "Loongson PCH MSI Controller"
632dcc2c JY	586	depends on MACH_LOONGSON64 \|\| COMPILE_TEST
	587	depends on PCI
	588	default MACH_LOONGSON64
	589	select IRQ_DOMAIN_HIERARCHY
	590	select PCI_MSI
	591	help
	592	Support for the Loongson PCH MSI Controller.
	593
ad4c938c MPT	594	config MST_IRQ
ad4c938c MPT	595	bool "MStar Interrupt Controller"
61b0648d	596	depends on ARCH_MEDIATEK \|\| ARCH_MSTARV7 \|\| COMPILE_TEST
ad4c938c MPT	597	default ARCH_MEDIATEK
	598	select IRQ_DOMAIN
	599	select IRQ_DOMAIN_HIERARCHY
	600	help
	601	Support MStar Interrupt Controller.
	602
fead4dd4 JN	603	config WPCM450_AIC
fead4dd4 JN	604	bool "Nuvoton WPCM450 Advanced Interrupt Controller"
94bc9420	605	depends on ARCH_WPCM450
fead4dd4 JN	606	help
	607	Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
	608
529ea368 TB	609	config IRQ_IDT3243X
	610	bool
	611	select GENERIC_IRQ_CHIP
	612	select IRQ_DOMAIN
	613
76cde263 HM	614	config APPLE_AIC
	615	bool "Apple Interrupt Controller (AIC)"
	616	depends on ARM64
5b44955d	617	depends on ARCH_APPLE \|\| COMPILE_TEST
76cde263 HM	618	help
	619	Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
	620	such as the M1.
	621
00fa3461 CB	622	config MCHP_EIC
	623	bool "Microchip External Interrupt Controller"
	624	depends on ARCH_AT91 \|\| COMPILE_TEST
	625	select IRQ_DOMAIN
	626	select IRQ_DOMAIN_HIERARCHY
	627	help
	628	Support for Microchip External Interrupt Controller.
	629
01493855	630	endmenu