Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
c94fb639 RD |
2 | menu "IRQ chip support" |
3 | ||
f6e916b8 TP |
4 | config IRQCHIP |
5 | def_bool y | |
612d5494 | 6 | depends on (OF_IRQ || ACPI_GENERIC_GSI) |
f6e916b8 | 7 | |
81243e44 RH |
8 | config ARM_GIC |
9 | bool | |
dee23403 | 10 | depends on OF |
9a1091ef | 11 | select IRQ_DOMAIN_HIERARCHY |
0e6c027c | 12 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
81243e44 | 13 | |
9c8edddf JH |
14 | config ARM_GIC_PM |
15 | bool | |
16 | depends on PM | |
17 | select ARM_GIC | |
9c8edddf | 18 | |
a27d21e0 LW |
19 | config ARM_GIC_MAX_NR |
20 | int | |
70265523 | 21 | depends on ARM_GIC |
a27d21e0 LW |
22 | default 2 if ARCH_REALVIEW |
23 | default 1 | |
24 | ||
853a33ce SS |
25 | config ARM_GIC_V2M |
26 | bool | |
3ee80364 AB |
27 | depends on PCI |
28 | select ARM_GIC | |
29 | select PCI_MSI | |
853a33ce | 30 | |
81243e44 RH |
31 | config GIC_NON_BANKED |
32 | bool | |
33 | ||
021f6537 MZ |
34 | config ARM_GIC_V3 |
35 | bool | |
443acc4f | 36 | select IRQ_DOMAIN_HIERARCHY |
e3825ba1 | 37 | select PARTITION_PERCPU |
0e6c027c | 38 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
35727af2 | 39 | select HAVE_ARM_SMCCC_DISCOVERY |
021f6537 | 40 | |
19812729 MZ |
41 | config ARM_GIC_V3_ITS |
42 | bool | |
13e7accb | 43 | select GENERIC_MSI_IRQ |
29f41139 MZ |
44 | default ARM_GIC_V3 |
45 | ||
46 | config ARM_GIC_V3_ITS_PCI | |
47 | bool | |
48 | depends on ARM_GIC_V3_ITS | |
3ee80364 AB |
49 | depends on PCI |
50 | depends on PCI_MSI | |
29f41139 | 51 | default ARM_GIC_V3_ITS |
021f6537 | 52 | |
7afe031c BP |
53 | config ARM_GIC_V3_ITS_FSL_MC |
54 | bool | |
55 | depends on ARM_GIC_V3_ITS | |
56 | depends on FSL_MC_BUS | |
57 | default ARM_GIC_V3_ITS | |
58 | ||
292ec080 UKK |
59 | config ARM_NVIC |
60 | bool | |
2d9f59f7 | 61 | select IRQ_DOMAIN_HIERARCHY |
292ec080 UKK |
62 | select GENERIC_IRQ_CHIP |
63 | ||
44430ec0 RH |
64 | config ARM_VIC |
65 | bool | |
66 | select IRQ_DOMAIN | |
44430ec0 RH |
67 | |
68 | config ARM_VIC_NR | |
69 | int | |
70 | default 4 if ARCH_S5PV210 | |
44430ec0 RH |
71 | default 2 |
72 | depends on ARM_VIC | |
73 | help | |
74 | The maximum number of VICs available in the system, for | |
75 | power management. | |
76 | ||
fed6d336 TP |
77 | config ARMADA_370_XP_IRQ |
78 | bool | |
fed6d336 | 79 | select GENERIC_IRQ_CHIP |
3ee80364 | 80 | select PCI_MSI if PCI |
0e6c027c | 81 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
fed6d336 | 82 | |
e6b78f2c AT |
83 | config ALPINE_MSI |
84 | bool | |
3ee80364 AB |
85 | depends on PCI |
86 | select PCI_MSI | |
e6b78f2c | 87 | select GENERIC_IRQ_CHIP |
e6b78f2c | 88 | |
1eb77c3b TS |
89 | config AL_FIC |
90 | bool "Amazon's Annapurna Labs Fabric Interrupt Controller" | |
9869f37a | 91 | depends on OF |
1eb77c3b TS |
92 | select GENERIC_IRQ_CHIP |
93 | select IRQ_DOMAIN | |
94 | help | |
95 | Support Amazon's Annapurna Labs Fabric Interrupt Controller. | |
96 | ||
b1479ebb BB |
97 | config ATMEL_AIC_IRQ |
98 | bool | |
99 | select GENERIC_IRQ_CHIP | |
100 | select IRQ_DOMAIN | |
b1479ebb BB |
101 | select SPARSE_IRQ |
102 | ||
103 | config ATMEL_AIC5_IRQ | |
104 | bool | |
105 | select GENERIC_IRQ_CHIP | |
106 | select IRQ_DOMAIN | |
b1479ebb BB |
107 | select SPARSE_IRQ |
108 | ||
0509cfde RB |
109 | config I8259 |
110 | bool | |
111 | select IRQ_DOMAIN | |
112 | ||
c7c42ec2 SA |
113 | config BCM6345_L1_IRQ |
114 | bool | |
115 | select GENERIC_IRQ_CHIP | |
116 | select IRQ_DOMAIN | |
0e6c027c | 117 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
c7c42ec2 | 118 | |
5f7f0317 | 119 | config BCM7038_L1_IRQ |
c057c799 FF |
120 | tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" |
121 | depends on ARCH_BRCMSTB || BMIPS_GENERIC | |
122 | default ARCH_BRCMSTB || BMIPS_GENERIC | |
5f7f0317 KC |
123 | select GENERIC_IRQ_CHIP |
124 | select IRQ_DOMAIN | |
0e6c027c | 125 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
5f7f0317 | 126 | |
a4fcbb86 | 127 | config BCM7120_L2_IRQ |
3ac268d5 FF |
128 | tristate "Broadcom STB 7120-style L2 interrupt controller driver" |
129 | depends on ARCH_BRCMSTB || BMIPS_GENERIC | |
130 | default ARCH_BRCMSTB || BMIPS_GENERIC | |
a4fcbb86 KC |
131 | select GENERIC_IRQ_CHIP |
132 | select IRQ_DOMAIN | |
133 | ||
7f646e92 | 134 | config BRCMSTB_L2_IRQ |
51d9db5c FF |
135 | tristate "Broadcom STB generic L2 interrupt controller driver" |
136 | depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC | |
137 | default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC | |
7f646e92 FF |
138 | select GENERIC_IRQ_CHIP |
139 | select IRQ_DOMAIN | |
140 | ||
0fc3d74c BG |
141 | config DAVINCI_CP_INTC |
142 | bool | |
143 | select GENERIC_IRQ_CHIP | |
144 | select IRQ_DOMAIN | |
145 | ||
350d71b9 SH |
146 | config DW_APB_ICTL |
147 | bool | |
e1588490 | 148 | select GENERIC_IRQ_CHIP |
54a38440 | 149 | select IRQ_DOMAIN_HIERARCHY |
350d71b9 | 150 | |
6ee532e2 LW |
151 | config FARADAY_FTINTC010 |
152 | bool | |
153 | select IRQ_DOMAIN | |
6ee532e2 LW |
154 | select SPARSE_IRQ |
155 | ||
9a7c4abd M |
156 | config HISILICON_IRQ_MBIGEN |
157 | bool | |
158 | select ARM_GIC_V3 | |
159 | select ARM_GIC_V3_ITS | |
9a7c4abd | 160 | |
b6ef9161 JH |
161 | config IMGPDC_IRQ |
162 | bool | |
163 | select GENERIC_IRQ_CHIP | |
164 | select IRQ_DOMAIN | |
165 | ||
5b978c10 LW |
166 | config IXP4XX_IRQ |
167 | bool | |
168 | select IRQ_DOMAIN | |
5b978c10 LW |
169 | select SPARSE_IRQ |
170 | ||
da0abe1a RF |
171 | config MADERA_IRQ |
172 | tristate | |
173 | ||
67e38cf2 RB |
174 | config IRQ_MIPS_CPU |
175 | bool | |
176 | select GENERIC_IRQ_CHIP | |
0f5209fe | 177 | select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING |
67e38cf2 | 178 | select IRQ_DOMAIN |
0e6c027c | 179 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
67e38cf2 | 180 | |
afc98d90 AS |
181 | config CLPS711X_IRQCHIP |
182 | bool | |
183 | depends on ARCH_CLPS711X | |
184 | select IRQ_DOMAIN | |
afc98d90 AS |
185 | select SPARSE_IRQ |
186 | default y | |
187 | ||
9b54470a SH |
188 | config OMPIC |
189 | bool | |
190 | ||
4db8e6d2 SK |
191 | config OR1K_PIC |
192 | bool | |
193 | select IRQ_DOMAIN | |
194 | ||
8598066c FB |
195 | config OMAP_IRQCHIP |
196 | bool | |
197 | select GENERIC_IRQ_CHIP | |
198 | select IRQ_DOMAIN | |
199 | ||
9dbd90f1 SH |
200 | config ORION_IRQCHIP |
201 | bool | |
202 | select IRQ_DOMAIN | |
9dbd90f1 | 203 | |
aaa8666a CB |
204 | config PIC32_EVIC |
205 | bool | |
206 | select GENERIC_IRQ_CHIP | |
207 | select IRQ_DOMAIN | |
208 | ||
981b58f6 | 209 | config JCORE_AIC |
3602ffde RF |
210 | bool "J-Core integrated AIC" if COMPILE_TEST |
211 | depends on OF | |
981b58f6 RF |
212 | select IRQ_DOMAIN |
213 | help | |
214 | Support for the J-Core integrated AIC. | |
215 | ||
d852e62a MS |
216 | config RDA_INTC |
217 | bool | |
218 | select IRQ_DOMAIN | |
219 | ||
44358048 | 220 | config RENESAS_INTC_IRQPIN |
02d7e041 | 221 | bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST |
44358048 | 222 | select IRQ_DOMAIN |
02d7e041 GU |
223 | help |
224 | Enable support for the Renesas Interrupt Controller for external | |
225 | interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. | |
44358048 | 226 | |
fbc83b7f | 227 | config RENESAS_IRQC |
72d44c0c | 228 | bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST |
99c221df | 229 | select GENERIC_IRQ_CHIP |
fbc83b7f | 230 | select IRQ_DOMAIN |
02d7e041 GU |
231 | help |
232 | Enable support for the Renesas Interrupt Controller for external | |
72d44c0c | 233 | devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. |
fbc83b7f | 234 | |
a644ccb8 | 235 | config RENESAS_RZA1_IRQC |
02d7e041 | 236 | bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST |
a644ccb8 | 237 | select IRQ_DOMAIN_HIERARCHY |
02d7e041 GU |
238 | help |
239 | Enable support for the Renesas RZ/A1 Interrupt Controller, to use up | |
240 | to 8 external interrupts with configurable sense select. | |
a644ccb8 | 241 | |
3fed0955 LP |
242 | config RENESAS_RZG2L_IRQC |
243 | bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST | |
244 | select GENERIC_IRQ_CHIP | |
245 | select IRQ_DOMAIN_HIERARCHY | |
246 | help | |
247 | Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller | |
248 | for external devices. | |
249 | ||
03ac990e MW |
250 | config SL28CPLD_INTC |
251 | bool "Kontron sl28cpld IRQ controller" | |
252 | depends on MFD_SL28CPLD=y || COMPILE_TEST | |
253 | select REGMAP_IRQ | |
254 | help | |
255 | Interrupt controller driver for the board management controller | |
256 | found on the Kontron sl28 CPLD. | |
257 | ||
07088484 LJ |
258 | config ST_IRQCHIP |
259 | bool | |
260 | select REGMAP | |
261 | select MFD_SYSCON | |
262 | help | |
263 | Enables SysCfg Controlled IRQs on STi based platforms. | |
264 | ||
d421fd6d SH |
265 | config SUN4I_INTC |
266 | bool | |
267 | ||
268 | config SUN6I_R_INTC | |
269 | bool | |
270 | select IRQ_DOMAIN_HIERARCHY | |
271 | select IRQ_FASTEOI_HIERARCHY_HANDLERS | |
272 | ||
273 | config SUNXI_NMI_INTC | |
274 | bool | |
275 | select GENERIC_IRQ_CHIP | |
276 | ||
b06eb017 CR |
277 | config TB10X_IRQC |
278 | bool | |
279 | select IRQ_DOMAIN | |
280 | select GENERIC_IRQ_CHIP | |
281 | ||
d01f8633 DR |
282 | config TS4800_IRQ |
283 | tristate "TS-4800 IRQ controller" | |
284 | select IRQ_DOMAIN | |
0df337cf | 285 | depends on HAS_IOMEM |
d2b383dc | 286 | depends on SOC_IMX51 || COMPILE_TEST |
d01f8633 DR |
287 | help |
288 | Support for the TS-4800 FPGA IRQ controller | |
289 | ||
2389d501 LW |
290 | config VERSATILE_FPGA_IRQ |
291 | bool | |
292 | select IRQ_DOMAIN | |
293 | ||
294 | config VERSATILE_FPGA_IRQ_NR | |
295 | int | |
296 | default 4 | |
297 | depends on VERSATILE_FPGA_IRQ | |
26a8e96a MF |
298 | |
299 | config XTENSA_MX | |
300 | bool | |
301 | select IRQ_DOMAIN | |
0e6c027c | 302 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
96ca848e | 303 | |
0547dc78 | 304 | config XILINX_INTC |
debf69cf | 305 | bool "Xilinx Interrupt Controller IP" |
fd31000d | 306 | depends on OF_ADDRESS |
0547dc78 | 307 | select IRQ_DOMAIN |
debf69cf RH |
308 | help |
309 | Support for the Xilinx Interrupt Controller IP core. | |
310 | This is used as a primary controller with MicroBlaze and can also | |
311 | be used as a secondary chained controller on other platforms. | |
0547dc78 | 312 | |
96ca848e S |
313 | config IRQ_CROSSBAR |
314 | bool | |
315 | help | |
f54619f2 | 316 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
96ca848e S |
317 | The primary irqchip invokes the crossbar's callback which inturn allocates |
318 | a free irq and configures the IP. Thus the peripheral interrupts are | |
319 | routed to one of the free irqchip interrupt lines. | |
89323f8c GS |
320 | |
321 | config KEYSTONE_IRQ | |
322 | tristate "Keystone 2 IRQ controller IP" | |
323 | depends on ARCH_KEYSTONE | |
324 | help | |
325 | Support for Texas Instruments Keystone 2 IRQ controller IP which | |
326 | is part of the Keystone 2 IPC mechanism | |
8a19b8f1 AB |
327 | |
328 | config MIPS_GIC | |
329 | bool | |
8190cc57 SH |
330 | select GENERIC_IRQ_IPI if SMP |
331 | select IRQ_DOMAIN_HIERARCHY | |
8a19b8f1 | 332 | select MIPS_CM |
8a764482 | 333 | |
44e08e70 PB |
334 | config INGENIC_IRQ |
335 | bool | |
336 | depends on MACH_INGENIC | |
337 | default y | |
78c10e55 | 338 | |
9536eba0 PC |
339 | config INGENIC_TCU_IRQ |
340 | bool "Ingenic JZ47xx TCU interrupt controller" | |
341 | default MACH_INGENIC | |
342 | depends on MIPS || COMPILE_TEST | |
343 | select MFD_SYSCON | |
8084499b | 344 | select GENERIC_IRQ_CHIP |
9536eba0 PC |
345 | help |
346 | Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic | |
347 | JZ47xx SoCs. | |
348 | ||
349 | If unsure, say N. | |
350 | ||
e324c4dc SW |
351 | config IMX_GPCV2 |
352 | bool | |
353 | select IRQ_DOMAIN | |
354 | help | |
355 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | |
7e4ac676 OR |
356 | |
357 | config IRQ_MXS | |
358 | def_bool y if MACH_ASM9260 || ARCH_MXS | |
359 | select IRQ_DOMAIN | |
360 | select STMP_DEVICE | |
c27f29bb | 361 | |
19d99164 AB |
362 | config MSCC_OCELOT_IRQ |
363 | bool | |
364 | select IRQ_DOMAIN | |
365 | select GENERIC_IRQ_CHIP | |
366 | ||
a68a63cb TP |
367 | config MVEBU_GICP |
368 | bool | |
369 | ||
e0de91a9 TP |
370 | config MVEBU_ICU |
371 | bool | |
372 | ||
c27f29bb TP |
373 | config MVEBU_ODMI |
374 | bool | |
13e7accb | 375 | select GENERIC_MSI_IRQ |
9e2c986c | 376 | |
a109893b TP |
377 | config MVEBU_PIC |
378 | bool | |
379 | ||
61ce8d8d MR |
380 | config MVEBU_SEI |
381 | bool | |
382 | ||
0dcd9f87 RV |
383 | config LS_EXTIRQ |
384 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | |
385 | select MFD_SYSCON | |
386 | ||
b8f3ebe6 ML |
387 | config LS_SCFG_MSI |
388 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | |
9c1a7bfc | 389 | depends on PCI_MSI |
b8f3ebe6 | 390 | |
9e2c986c MZ |
391 | config PARTITION_PERCPU |
392 | bool | |
0efacbba | 393 | |
e0720416 AT |
394 | config STM32_EXTI |
395 | bool | |
396 | select IRQ_DOMAIN | |
0e7d7807 | 397 | select GENERIC_IRQ_CHIP |
f20cc9b0 AVF |
398 | |
399 | config QCOM_IRQ_COMBINER | |
400 | bool "QCOM IRQ combiner support" | |
401 | depends on ARCH_QCOM && ACPI | |
f20cc9b0 AVF |
402 | select IRQ_DOMAIN_HIERARCHY |
403 | help | |
404 | Say yes here to add support for the IRQ combiner devices embedded | |
405 | in Qualcomm Technologies chips. | |
5ed34d3a MY |
406 | |
407 | config IRQ_UNIPHIER_AIDET | |
408 | bool "UniPhier AIDET support" if COMPILE_TEST | |
409 | depends on ARCH_UNIPHIER || COMPILE_TEST | |
410 | default ARCH_UNIPHIER | |
411 | select IRQ_DOMAIN_HIERARCHY | |
412 | help | |
413 | Support for the UniPhier AIDET (ARM Interrupt Detector). | |
c94fb639 | 414 | |
215f4cc0 | 415 | config MESON_IRQ_GPIO |
a947aa00 NA |
416 | tristate "Meson GPIO Interrupt Multiplexer" |
417 | depends on ARCH_MESON || COMPILE_TEST | |
418 | default ARCH_MESON | |
215f4cc0 JB |
419 | select IRQ_DOMAIN_HIERARCHY |
420 | help | |
421 | Support Meson SoC Family GPIO Interrupt Multiplexer | |
422 | ||
4235ff50 MD |
423 | config GOLDFISH_PIC |
424 | bool "Goldfish programmable interrupt controller" | |
425 | depends on MIPS && (GOLDFISH || COMPILE_TEST) | |
969ac78d | 426 | select GENERIC_IRQ_CHIP |
4235ff50 MD |
427 | select IRQ_DOMAIN |
428 | help | |
429 | Say yes here to enable Goldfish interrupt controller driver used | |
430 | for Goldfish based virtual platforms. | |
431 | ||
f55c73ae | 432 | config QCOM_PDC |
4acd8a4b | 433 | tristate "QCOM PDC" |
f55c73ae | 434 | depends on ARCH_QCOM |
f55c73ae AS |
435 | select IRQ_DOMAIN_HIERARCHY |
436 | help | |
437 | Power Domain Controller driver to manage and configure wakeup | |
438 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. | |
439 | ||
a6199bb5 SG |
440 | config QCOM_MPM |
441 | tristate "QCOM MPM" | |
442 | depends on ARCH_QCOM | |
fa4dcc88 | 443 | depends on MAILBOX |
a6199bb5 SG |
444 | select IRQ_DOMAIN_HIERARCHY |
445 | help | |
446 | MSM Power Manager driver to manage and configure wakeup | |
447 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. | |
448 | ||
d8a5f5f7 | 449 | config CSKY_MPINTC |
be1abc5b | 450 | bool |
d8a5f5f7 GR |
451 | depends on CSKY |
452 | help | |
453 | Say yes here to enable C-SKY SMP interrupt controller driver used | |
454 | for C-SKY SMP system. | |
656b42de | 455 | In fact it's not mmio map in hardware and it uses ld/st to visit the |
d8a5f5f7 GR |
456 | controller's register inside CPU. |
457 | ||
edff1b48 GR |
458 | config CSKY_APB_INTC |
459 | bool "C-SKY APB Interrupt Controller" | |
460 | depends on CSKY | |
461 | help | |
462 | Say yes here to enable C-SKY APB interrupt controller driver used | |
656b42de | 463 | by C-SKY single core SOC system. It uses mmio map apb-bus to visit |
edff1b48 GR |
464 | the controller's register. |
465 | ||
0136afa0 LS |
466 | config IMX_IRQSTEER |
467 | bool "i.MX IRQSTEER support" | |
468 | depends on ARCH_MXC || COMPILE_TEST | |
469 | default ARCH_MXC | |
470 | select IRQ_DOMAIN | |
471 | help | |
472 | Support for the i.MX IRQSTEER interrupt multiplexer/remapper. | |
473 | ||
2fbb1396 | 474 | config IMX_INTMUX |
a890caeb GU |
475 | bool "i.MX INTMUX support" if COMPILE_TEST |
476 | default y if ARCH_MXC | |
2fbb1396 JZ |
477 | select IRQ_DOMAIN |
478 | help | |
479 | Support for the i.MX INTMUX interrupt multiplexer. | |
480 | ||
70afdab9 FL |
481 | config IMX_MU_MSI |
482 | tristate "i.MX MU used as MSI controller" | |
483 | depends on OF && HAS_IOMEM | |
6c9f7434 | 484 | depends on ARCH_MXC || COMPILE_TEST |
70afdab9 FL |
485 | default m if ARCH_MXC |
486 | select IRQ_DOMAIN | |
487 | select IRQ_DOMAIN_HIERARCHY | |
13e7accb | 488 | select GENERIC_MSI_IRQ |
70afdab9 | 489 | help |
6c9f7434 GU |
490 | Provide a driver for the i.MX Messaging Unit block used as a |
491 | CPU-to-CPU MSI controller. This requires a specially crafted DT | |
492 | to make use of this driver. | |
70afdab9 FL |
493 | |
494 | If unsure, say N | |
495 | ||
9e543e22 JY |
496 | config LS1X_IRQ |
497 | bool "Loongson-1 Interrupt Controller" | |
498 | depends on MACH_LOONGSON32 | |
499 | default y | |
500 | select IRQ_DOMAIN | |
501 | select GENERIC_IRQ_CHIP | |
502 | help | |
503 | Support for the Loongson-1 platform Interrupt Controller. | |
504 | ||
cd844b07 LV |
505 | config TI_SCI_INTR_IRQCHIP |
506 | bool | |
507 | depends on TI_SCI_PROTOCOL | |
508 | select IRQ_DOMAIN_HIERARCHY | |
509 | help | |
510 | This enables the irqchip driver support for K3 Interrupt router | |
511 | over TI System Control Interface available on some new TI's SoCs. | |
512 | If you wish to use interrupt router irq resources managed by the | |
513 | TI System Controller, say Y here. Otherwise, say N. | |
514 | ||
9f1463b8 LV |
515 | config TI_SCI_INTA_IRQCHIP |
516 | bool | |
517 | depends on TI_SCI_PROTOCOL | |
518 | select IRQ_DOMAIN_HIERARCHY | |
f011df61 | 519 | select TI_SCI_INTA_MSI_DOMAIN |
9f1463b8 LV |
520 | help |
521 | This enables the irqchip driver support for K3 Interrupt aggregator | |
522 | over TI System Control Interface available on some new TI's SoCs. | |
523 | If you wish to use interrupt aggregator irq resources managed by the | |
524 | TI System Controller, say Y here. Otherwise, say N. | |
525 | ||
04e2d1e0 | 526 | config TI_PRUSS_INTC |
b8e594fa SA |
527 | tristate |
528 | depends on TI_PRUSS | |
529 | default TI_PRUSS | |
04e2d1e0 GJ |
530 | select IRQ_DOMAIN |
531 | help | |
532 | This enables support for the PRU-ICSS Local Interrupt Controller | |
533 | present within a PRU-ICSS subsystem present on various TI SoCs. | |
534 | The PRUSS INTC enables various interrupts to be routed to multiple | |
535 | different processors within the SoC. | |
536 | ||
6b7ce892 | 537 | config RISCV_INTC |
d8fb1307 | 538 | bool |
6b7ce892 | 539 | depends on RISCV |
832f15f4 | 540 | select IRQ_DOMAIN_HIERARCHY |
6b7ce892 | 541 | |
8237f8bc | 542 | config SIFIVE_PLIC |
fdb1742a | 543 | bool |
8237f8bc | 544 | depends on RISCV |
466008f9 | 545 | select IRQ_DOMAIN_HIERARCHY |
de078949 | 546 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP |
01493855 | 547 | |
b74416db HK |
548 | config EXYNOS_IRQ_COMBINER |
549 | bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST | |
550 | depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST | |
551 | help | |
552 | Say yes here to add support for the IRQ combiner devices embedded | |
553 | in Samsung Exynos chips. | |
554 | ||
b2d3e335 HC |
555 | config IRQ_LOONGARCH_CPU |
556 | bool | |
557 | select GENERIC_IRQ_CHIP | |
558 | select IRQ_DOMAIN | |
559 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK | |
70f7b6c0 | 560 | select LOONGSON_HTVEC |
8d5356f9 HC |
561 | select LOONGSON_LIOINTC |
562 | select LOONGSON_EIOINTC | |
563 | select LOONGSON_PCH_PIC | |
564 | select LOONGSON_PCH_MSI | |
565 | select LOONGSON_PCH_LPC | |
b2d3e335 HC |
566 | help |
567 | Support for the LoongArch CPU Interrupt Controller. For details of | |
568 | irq chip hierarchy on LoongArch platforms please read the document | |
569 | Documentation/loongarch/irq-chip-model.rst. | |
570 | ||
dbb15226 JY |
571 | config LOONGSON_LIOINTC |
572 | bool "Loongson Local I/O Interrupt Controller" | |
573 | depends on MACH_LOONGSON64 | |
574 | default y | |
575 | select IRQ_DOMAIN | |
576 | select GENERIC_IRQ_CHIP | |
577 | help | |
578 | Support for the Loongson Local I/O Interrupt Controller. | |
579 | ||
dd281e1a HC |
580 | config LOONGSON_EIOINTC |
581 | bool "Loongson Extend I/O Interrupt Controller" | |
582 | depends on LOONGARCH | |
583 | depends on MACH_LOONGSON64 | |
584 | default MACH_LOONGSON64 | |
585 | select IRQ_DOMAIN_HIERARCHY | |
586 | select GENERIC_IRQ_CHIP | |
587 | help | |
588 | Support for the Loongson3 Extend I/O Interrupt Vector Controller. | |
589 | ||
a93f1d90 JY |
590 | config LOONGSON_HTPIC |
591 | bool "Loongson3 HyperTransport PIC Controller" | |
987a3e03 | 592 | depends on MACH_LOONGSON64 && MIPS |
a93f1d90 JY |
593 | default y |
594 | select IRQ_DOMAIN | |
595 | select GENERIC_IRQ_CHIP | |
a93f1d90 JY |
596 | help |
597 | Support for the Loongson-3 HyperTransport PIC Controller. | |
598 | ||
818e915f | 599 | config LOONGSON_HTVEC |
987a3e03 | 600 | bool "Loongson HyperTransport Interrupt Vector Controller" |
d77aeb5d | 601 | depends on MACH_LOONGSON64 |
818e915f JY |
602 | default MACH_LOONGSON64 |
603 | select IRQ_DOMAIN_HIERARCHY | |
604 | help | |
987a3e03 | 605 | Support for the Loongson HyperTransport Interrupt Vector Controller. |
818e915f | 606 | |
ef8c01eb JY |
607 | config LOONGSON_PCH_PIC |
608 | bool "Loongson PCH PIC Controller" | |
bcdd75c5 | 609 | depends on MACH_LOONGSON64 |
ef8c01eb JY |
610 | default MACH_LOONGSON64 |
611 | select IRQ_DOMAIN_HIERARCHY | |
612 | select IRQ_FASTEOI_HIERARCHY_HANDLERS | |
613 | help | |
614 | Support for the Loongson PCH PIC Controller. | |
615 | ||
632dcc2c | 616 | config LOONGSON_PCH_MSI |
a23df9a4 | 617 | bool "Loongson PCH MSI Controller" |
02308732 | 618 | depends on MACH_LOONGSON64 |
632dcc2c JY |
619 | depends on PCI |
620 | default MACH_LOONGSON64 | |
621 | select IRQ_DOMAIN_HIERARCHY | |
622 | select PCI_MSI | |
623 | help | |
624 | Support for the Loongson PCH MSI Controller. | |
625 | ||
ee73f14e HC |
626 | config LOONGSON_PCH_LPC |
627 | bool "Loongson PCH LPC Controller" | |
e7ccba77 | 628 | depends on LOONGARCH |
ee73f14e | 629 | depends on MACH_LOONGSON64 |
e7ccba77 | 630 | default MACH_LOONGSON64 |
ee73f14e HC |
631 | select IRQ_DOMAIN_HIERARCHY |
632 | help | |
633 | Support for the Loongson PCH LPC Controller. | |
634 | ||
ad4c938c MPT |
635 | config MST_IRQ |
636 | bool "MStar Interrupt Controller" | |
61b0648d | 637 | depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST |
ad4c938c MPT |
638 | default ARCH_MEDIATEK |
639 | select IRQ_DOMAIN | |
640 | select IRQ_DOMAIN_HIERARCHY | |
641 | help | |
642 | Support MStar Interrupt Controller. | |
643 | ||
fead4dd4 JN |
644 | config WPCM450_AIC |
645 | bool "Nuvoton WPCM450 Advanced Interrupt Controller" | |
94bc9420 | 646 | depends on ARCH_WPCM450 |
fead4dd4 JN |
647 | help |
648 | Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. | |
649 | ||
529ea368 TB |
650 | config IRQ_IDT3243X |
651 | bool | |
652 | select GENERIC_IRQ_CHIP | |
653 | select IRQ_DOMAIN | |
654 | ||
76cde263 HM |
655 | config APPLE_AIC |
656 | bool "Apple Interrupt Controller (AIC)" | |
657 | depends on ARM64 | |
5b44955d | 658 | depends on ARCH_APPLE || COMPILE_TEST |
c19f8971 | 659 | select GENERIC_IRQ_IPI_MUX |
76cde263 HM |
660 | help |
661 | Support for the Apple Interrupt Controller found on Apple Silicon SoCs, | |
662 | such as the M1. | |
663 | ||
00fa3461 CB |
664 | config MCHP_EIC |
665 | bool "Microchip External Interrupt Controller" | |
666 | depends on ARCH_AT91 || COMPILE_TEST | |
667 | select IRQ_DOMAIN | |
668 | select IRQ_DOMAIN_HIERARCHY | |
669 | help | |
670 | Support for Microchip External Interrupt Controller. | |
671 | ||
f7189d93 QJ |
672 | config SUNPLUS_SP7021_INTC |
673 | bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST | |
674 | default SOC_SP7021 | |
675 | help | |
676 | Support for the Sunplus SP7021 Interrupt Controller IP core. | |
677 | SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a | |
678 | chained controller, routing all interrupt source in P-Chip to | |
679 | the primary controller on C-Chip. | |
680 | ||
01493855 | 681 | endmenu |