Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7a31f6f4 | 2 | /* |
89184651 | 3 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 HD |
4 | */ |
5 | ||
804cb54c | 6 | #include <linux/bitops.h> |
d1313e78 | 7 | #include <linux/debugfs.h> |
bc5e6dea | 8 | #include <linux/err.h> |
7a31f6f4 | 9 | #include <linux/iommu.h> |
89184651 | 10 | #include <linux/kernel.h> |
0760e8fa | 11 | #include <linux/of.h> |
89184651 TR |
12 | #include <linux/of_device.h> |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/slab.h> | |
461a6946 | 15 | #include <linux/dma-mapping.h> |
306a7f91 TR |
16 | |
17 | #include <soc/tegra/ahb.h> | |
89184651 | 18 | #include <soc/tegra/mc.h> |
7a31f6f4 | 19 | |
7f4c9176 TR |
20 | struct tegra_smmu_group { |
21 | struct list_head list; | |
22 | const struct tegra_smmu_group_soc *soc; | |
23 | struct iommu_group *group; | |
24 | }; | |
25 | ||
89184651 TR |
26 | struct tegra_smmu { |
27 | void __iomem *regs; | |
28 | struct device *dev; | |
e6bc5933 | 29 | |
89184651 TR |
30 | struct tegra_mc *mc; |
31 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 32 | |
7f4c9176 TR |
33 | struct list_head groups; |
34 | ||
804cb54c | 35 | unsigned long pfn_mask; |
11cec15b | 36 | unsigned long tlb_mask; |
804cb54c | 37 | |
89184651 TR |
38 | unsigned long *asids; |
39 | struct mutex lock; | |
39abf8aa | 40 | |
89184651 | 41 | struct list_head list; |
d1313e78 TR |
42 | |
43 | struct dentry *debugfs; | |
0b480e44 JR |
44 | |
45 | struct iommu_device iommu; /* IOMMU Core code handle */ | |
7a31f6f4 | 46 | }; |
7a31f6f4 | 47 | |
89184651 | 48 | struct tegra_smmu_as { |
d5f1a81c | 49 | struct iommu_domain domain; |
89184651 TR |
50 | struct tegra_smmu *smmu; |
51 | unsigned int use_count; | |
32924c76 | 52 | u32 *count; |
853520fa | 53 | struct page **pts; |
89184651 | 54 | struct page *pd; |
e3c97196 | 55 | dma_addr_t pd_dma; |
89184651 TR |
56 | unsigned id; |
57 | u32 attr; | |
7a31f6f4 HD |
58 | }; |
59 | ||
d5f1a81c JR |
60 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
61 | { | |
62 | return container_of(dom, struct tegra_smmu_as, domain); | |
63 | } | |
64 | ||
89184651 TR |
65 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
66 | unsigned long offset) | |
67 | { | |
68 | writel(value, smmu->regs + offset); | |
69 | } | |
7a31f6f4 | 70 | |
89184651 TR |
71 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
72 | { | |
73 | return readl(smmu->regs + offset); | |
74 | } | |
5a2c937a | 75 | |
89184651 TR |
76 | #define SMMU_CONFIG 0x010 |
77 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 78 | |
89184651 TR |
79 | #define SMMU_TLB_CONFIG 0x14 |
80 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
81 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
11cec15b TR |
82 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ |
83 | ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask) | |
0760e8fa | 84 | |
89184651 TR |
85 | #define SMMU_PTC_CONFIG 0x18 |
86 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
87 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
88 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 89 | |
89184651 TR |
90 | #define SMMU_PTB_ASID 0x01c |
91 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 92 | |
89184651 | 93 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 94 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 95 | |
e3c97196 | 96 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 97 | |
89184651 TR |
98 | #define SMMU_TLB_FLUSH 0x030 |
99 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
100 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
101 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
89184651 TR |
102 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
103 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
104 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
105 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
106 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 107 | |
89184651 TR |
108 | #define SMMU_PTC_FLUSH 0x034 |
109 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
110 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 111 | |
89184651 TR |
112 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
113 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 114 | |
89184651 TR |
115 | /* per-SWGROUP SMMU_*_ASID register */ |
116 | #define SMMU_ASID_ENABLE (1 << 31) | |
117 | #define SMMU_ASID_MASK 0x7f | |
118 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 119 | |
89184651 TR |
120 | /* page table definitions */ |
121 | #define SMMU_NUM_PDE 1024 | |
122 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 123 | |
89184651 TR |
124 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
125 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 126 | |
89184651 TR |
127 | #define SMMU_PDE_SHIFT 22 |
128 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 129 | |
89184651 TR |
130 | #define SMMU_PD_READABLE (1 << 31) |
131 | #define SMMU_PD_WRITABLE (1 << 30) | |
132 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 133 | |
89184651 TR |
134 | #define SMMU_PDE_READABLE (1 << 31) |
135 | #define SMMU_PDE_WRITABLE (1 << 30) | |
136 | #define SMMU_PDE_NONSECURE (1 << 29) | |
137 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 138 | |
89184651 TR |
139 | #define SMMU_PTE_READABLE (1 << 31) |
140 | #define SMMU_PTE_WRITABLE (1 << 30) | |
141 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 142 | |
89184651 TR |
143 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
144 | SMMU_PDE_NONSECURE) | |
7a31f6f4 | 145 | |
34d35f8c RK |
146 | static unsigned int iova_pd_index(unsigned long iova) |
147 | { | |
148 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
149 | } | |
150 | ||
151 | static unsigned int iova_pt_index(unsigned long iova) | |
152 | { | |
153 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
154 | } | |
155 | ||
e3c97196 | 156 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 157 | { |
e3c97196 RK |
158 | addr >>= 12; |
159 | return (addr & smmu->pfn_mask) == addr; | |
160 | } | |
4b3c7d10 | 161 | |
96d3ab80 | 162 | static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde) |
e3c97196 | 163 | { |
96d3ab80 | 164 | return (dma_addr_t)(pde & smmu->pfn_mask) << 12; |
4b3c7d10 RK |
165 | } |
166 | ||
b8fe0382 RK |
167 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
168 | { | |
169 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
170 | } | |
171 | ||
e3c97196 | 172 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 173 | unsigned long offset) |
7a31f6f4 | 174 | { |
89184651 TR |
175 | u32 value; |
176 | ||
b8fe0382 | 177 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 178 | |
b8fe0382 | 179 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
180 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
181 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 182 | #else |
b8fe0382 | 183 | value = 0; |
89184651 | 184 | #endif |
b8fe0382 | 185 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 186 | } |
89184651 | 187 | |
e3c97196 | 188 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 189 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
190 | } |
191 | ||
89184651 | 192 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 193 | { |
89184651 | 194 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
195 | } |
196 | ||
89184651 TR |
197 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
198 | unsigned long asid) | |
7a31f6f4 | 199 | { |
89184651 | 200 | u32 value; |
7a31f6f4 | 201 | |
43a0541e DO |
202 | if (smmu->soc->num_asids == 4) |
203 | value = (asid & 0x3) << 29; | |
204 | else | |
205 | value = (asid & 0x7f) << 24; | |
206 | ||
207 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
89184651 | 208 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
209 | } |
210 | ||
89184651 TR |
211 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
212 | unsigned long asid, | |
213 | unsigned long iova) | |
7a31f6f4 | 214 | { |
89184651 | 215 | u32 value; |
7a31f6f4 | 216 | |
43a0541e DO |
217 | if (smmu->soc->num_asids == 4) |
218 | value = (asid & 0x3) << 29; | |
219 | else | |
220 | value = (asid & 0x7f) << 24; | |
221 | ||
222 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
89184651 | 223 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
224 | } |
225 | ||
89184651 TR |
226 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
227 | unsigned long asid, | |
228 | unsigned long iova) | |
7a31f6f4 | 229 | { |
89184651 | 230 | u32 value; |
7a31f6f4 | 231 | |
43a0541e DO |
232 | if (smmu->soc->num_asids == 4) |
233 | value = (asid & 0x3) << 29; | |
234 | else | |
235 | value = (asid & 0x7f) << 24; | |
236 | ||
237 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
89184651 | 238 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
239 | } |
240 | ||
89184651 | 241 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 242 | { |
446152d5 | 243 | smmu_readl(smmu, SMMU_PTB_ASID); |
7a31f6f4 HD |
244 | } |
245 | ||
89184651 | 246 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 247 | { |
89184651 | 248 | unsigned long id; |
7a31f6f4 | 249 | |
89184651 | 250 | mutex_lock(&smmu->lock); |
7a31f6f4 | 251 | |
89184651 TR |
252 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
253 | if (id >= smmu->soc->num_asids) { | |
254 | mutex_unlock(&smmu->lock); | |
255 | return -ENOSPC; | |
7a31f6f4 | 256 | } |
7a31f6f4 | 257 | |
89184651 TR |
258 | set_bit(id, smmu->asids); |
259 | *idp = id; | |
260 | ||
261 | mutex_unlock(&smmu->lock); | |
262 | return 0; | |
7a31f6f4 HD |
263 | } |
264 | ||
89184651 | 265 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 266 | { |
89184651 TR |
267 | mutex_lock(&smmu->lock); |
268 | clear_bit(id, smmu->asids); | |
269 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 270 | } |
89184651 TR |
271 | |
272 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 273 | { |
89184651 | 274 | return false; |
7a31f6f4 | 275 | } |
7a31f6f4 | 276 | |
d5f1a81c | 277 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 278 | { |
89184651 | 279 | struct tegra_smmu_as *as; |
7a31f6f4 | 280 | |
d5f1a81c JR |
281 | if (type != IOMMU_DOMAIN_UNMANAGED) |
282 | return NULL; | |
283 | ||
89184651 TR |
284 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
285 | if (!as) | |
d5f1a81c | 286 | return NULL; |
7a31f6f4 | 287 | |
89184651 | 288 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 289 | |
707917cb | 290 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
291 | if (!as->pd) { |
292 | kfree(as); | |
d5f1a81c | 293 | return NULL; |
7a31f6f4 | 294 | } |
9e971a03 | 295 | |
32924c76 | 296 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
297 | if (!as->count) { |
298 | __free_page(as->pd); | |
299 | kfree(as); | |
d5f1a81c | 300 | return NULL; |
7a31f6f4 | 301 | } |
9e971a03 | 302 | |
853520fa RK |
303 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
304 | if (!as->pts) { | |
32924c76 | 305 | kfree(as->count); |
853520fa RK |
306 | __free_page(as->pd); |
307 | kfree(as); | |
308 | return NULL; | |
309 | } | |
310 | ||
471d9144 | 311 | /* setup aperture */ |
7f65ef01 JR |
312 | as->domain.geometry.aperture_start = 0; |
313 | as->domain.geometry.aperture_end = 0xffffffff; | |
314 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 315 | |
d5f1a81c | 316 | return &as->domain; |
7a31f6f4 HD |
317 | } |
318 | ||
d5f1a81c | 319 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 320 | { |
d5f1a81c | 321 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 322 | |
89184651 | 323 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 324 | |
4f97031f DO |
325 | WARN_ON_ONCE(as->use_count); |
326 | kfree(as->count); | |
327 | kfree(as->pts); | |
89184651 | 328 | kfree(as); |
7a31f6f4 HD |
329 | } |
330 | ||
89184651 TR |
331 | static const struct tegra_smmu_swgroup * |
332 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 333 | { |
89184651 TR |
334 | const struct tegra_smmu_swgroup *group = NULL; |
335 | unsigned int i; | |
7a31f6f4 | 336 | |
89184651 TR |
337 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
338 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
339 | group = &smmu->soc->swgroups[i]; | |
340 | break; | |
341 | } | |
342 | } | |
7a31f6f4 | 343 | |
89184651 | 344 | return group; |
7a31f6f4 HD |
345 | } |
346 | ||
89184651 TR |
347 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
348 | unsigned int asid) | |
7a31f6f4 | 349 | { |
89184651 TR |
350 | const struct tegra_smmu_swgroup *group; |
351 | unsigned int i; | |
352 | u32 value; | |
7a31f6f4 | 353 | |
e31e5929 NK |
354 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
355 | if (group) { | |
356 | value = smmu_readl(smmu, group->reg); | |
357 | value &= ~SMMU_ASID_MASK; | |
358 | value |= SMMU_ASID_VALUE(asid); | |
359 | value |= SMMU_ASID_ENABLE; | |
360 | smmu_writel(smmu, value, group->reg); | |
361 | } else { | |
362 | pr_warn("%s group from swgroup %u not found\n", __func__, | |
363 | swgroup); | |
364 | /* No point moving ahead if group was not found */ | |
365 | return; | |
366 | } | |
367 | ||
89184651 TR |
368 | for (i = 0; i < smmu->soc->num_clients; i++) { |
369 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 370 | |
89184651 TR |
371 | if (client->swgroup != swgroup) |
372 | continue; | |
7a31f6f4 | 373 | |
89184651 TR |
374 | value = smmu_readl(smmu, client->smmu.reg); |
375 | value |= BIT(client->smmu.bit); | |
376 | smmu_writel(smmu, value, client->smmu.reg); | |
377 | } | |
7a31f6f4 HD |
378 | } |
379 | ||
89184651 TR |
380 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
381 | unsigned int asid) | |
7a31f6f4 | 382 | { |
89184651 TR |
383 | const struct tegra_smmu_swgroup *group; |
384 | unsigned int i; | |
385 | u32 value; | |
7a31f6f4 | 386 | |
89184651 TR |
387 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
388 | if (group) { | |
389 | value = smmu_readl(smmu, group->reg); | |
390 | value &= ~SMMU_ASID_MASK; | |
391 | value |= SMMU_ASID_VALUE(asid); | |
392 | value &= ~SMMU_ASID_ENABLE; | |
393 | smmu_writel(smmu, value, group->reg); | |
394 | } | |
7a31f6f4 | 395 | |
89184651 TR |
396 | for (i = 0; i < smmu->soc->num_clients; i++) { |
397 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 398 | |
89184651 TR |
399 | if (client->swgroup != swgroup) |
400 | continue; | |
7a31f6f4 | 401 | |
89184651 TR |
402 | value = smmu_readl(smmu, client->smmu.reg); |
403 | value &= ~BIT(client->smmu.bit); | |
404 | smmu_writel(smmu, value, client->smmu.reg); | |
405 | } | |
7a31f6f4 HD |
406 | } |
407 | ||
89184651 TR |
408 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
409 | struct tegra_smmu_as *as) | |
7a31f6f4 | 410 | { |
89184651 | 411 | u32 value; |
7a31f6f4 HD |
412 | int err; |
413 | ||
89184651 TR |
414 | if (as->use_count > 0) { |
415 | as->use_count++; | |
416 | return 0; | |
7a31f6f4 | 417 | } |
7a31f6f4 | 418 | |
e3c97196 RK |
419 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
420 | DMA_TO_DEVICE); | |
421 | if (dma_mapping_error(smmu->dev, as->pd_dma)) | |
422 | return -ENOMEM; | |
423 | ||
424 | /* We can't handle 64-bit DMA addresses */ | |
425 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
426 | err = -ENOMEM; | |
427 | goto err_unmap; | |
428 | } | |
429 | ||
89184651 TR |
430 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
431 | if (err < 0) | |
e3c97196 | 432 | goto err_unmap; |
7a31f6f4 | 433 | |
e3c97196 | 434 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 435 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 436 | |
89184651 | 437 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 438 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
439 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
440 | smmu_flush(smmu); | |
7a31f6f4 | 441 | |
89184651 TR |
442 | as->smmu = smmu; |
443 | as->use_count++; | |
7a31f6f4 | 444 | |
89184651 | 445 | return 0; |
e3c97196 RK |
446 | |
447 | err_unmap: | |
448 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
449 | return err; | |
7a31f6f4 HD |
450 | } |
451 | ||
89184651 TR |
452 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
453 | struct tegra_smmu_as *as) | |
7a31f6f4 | 454 | { |
89184651 TR |
455 | if (--as->use_count > 0) |
456 | return; | |
457 | ||
458 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
459 | |
460 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
461 | ||
89184651 | 462 | as->smmu = NULL; |
7a31f6f4 HD |
463 | } |
464 | ||
89184651 TR |
465 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
466 | struct device *dev) | |
7a31f6f4 | 467 | { |
a5616e24 | 468 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
d5f1a81c | 469 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
470 | struct device_node *np = dev->of_node; |
471 | struct of_phandle_args args; | |
472 | unsigned int index = 0; | |
473 | int err = 0; | |
7a31f6f4 | 474 | |
89184651 TR |
475 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
476 | &args)) { | |
477 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 478 | |
89184651 TR |
479 | if (args.np != smmu->dev->of_node) { |
480 | of_node_put(args.np); | |
d2453b2c | 481 | continue; |
89184651 | 482 | } |
d2453b2c | 483 | |
89184651 | 484 | of_node_put(args.np); |
d2453b2c | 485 | |
89184651 TR |
486 | err = tegra_smmu_as_prepare(smmu, as); |
487 | if (err < 0) | |
488 | return err; | |
489 | ||
490 | tegra_smmu_enable(smmu, swgroup, as->id); | |
491 | index++; | |
7a31f6f4 | 492 | } |
7a31f6f4 | 493 | |
89184651 TR |
494 | if (index == 0) |
495 | return -ENODEV; | |
7a31f6f4 | 496 | |
89184651 TR |
497 | return 0; |
498 | } | |
7a31f6f4 | 499 | |
89184651 TR |
500 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
501 | { | |
d5f1a81c | 502 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
503 | struct device_node *np = dev->of_node; |
504 | struct tegra_smmu *smmu = as->smmu; | |
505 | struct of_phandle_args args; | |
506 | unsigned int index = 0; | |
7a31f6f4 | 507 | |
89184651 TR |
508 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
509 | &args)) { | |
510 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 511 | |
89184651 TR |
512 | if (args.np != smmu->dev->of_node) { |
513 | of_node_put(args.np); | |
514 | continue; | |
515 | } | |
23349902 | 516 | |
89184651 | 517 | of_node_put(args.np); |
7a31f6f4 | 518 | |
89184651 TR |
519 | tegra_smmu_disable(smmu, swgroup, as->id); |
520 | tegra_smmu_as_unprepare(smmu, as); | |
521 | index++; | |
522 | } | |
7a31f6f4 HD |
523 | } |
524 | ||
4080e99b RK |
525 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
526 | u32 value) | |
527 | { | |
528 | unsigned int pd_index = iova_pd_index(iova); | |
529 | struct tegra_smmu *smmu = as->smmu; | |
530 | u32 *pd = page_address(as->pd); | |
531 | unsigned long offset = pd_index * sizeof(*pd); | |
532 | ||
533 | /* Set the page directory entry first */ | |
534 | pd[pd_index] = value; | |
535 | ||
536 | /* The flush the page directory entry from caches */ | |
537 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
538 | sizeof(*pd), DMA_TO_DEVICE); | |
539 | ||
540 | /* And flush the iommu */ | |
541 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
542 | smmu_flush_tlb_section(smmu, as->id, iova); | |
543 | smmu_flush(smmu); | |
544 | } | |
545 | ||
0b42c7c1 RK |
546 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
547 | { | |
548 | u32 *pt = page_address(pt_page); | |
549 | ||
550 | return pt + iova_pt_index(iova); | |
551 | } | |
552 | ||
553 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 554 | dma_addr_t *dmap) |
0b42c7c1 RK |
555 | { |
556 | unsigned int pd_index = iova_pd_index(iova); | |
96d3ab80 | 557 | struct tegra_smmu *smmu = as->smmu; |
0b42c7c1 | 558 | struct page *pt_page; |
e3c97196 | 559 | u32 *pd; |
0b42c7c1 | 560 | |
853520fa RK |
561 | pt_page = as->pts[pd_index]; |
562 | if (!pt_page) | |
0b42c7c1 RK |
563 | return NULL; |
564 | ||
e3c97196 | 565 | pd = page_address(as->pd); |
96d3ab80 | 566 | *dmap = smmu_pde_to_dma(smmu, pd[pd_index]); |
0b42c7c1 RK |
567 | |
568 | return tegra_smmu_pte_offset(pt_page, iova); | |
569 | } | |
570 | ||
89184651 | 571 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
e3c97196 | 572 | dma_addr_t *dmap) |
7a31f6f4 | 573 | { |
34d35f8c | 574 | unsigned int pde = iova_pd_index(iova); |
89184651 | 575 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 576 | |
853520fa | 577 | if (!as->pts[pde]) { |
e3c97196 RK |
578 | struct page *page; |
579 | dma_addr_t dma; | |
580 | ||
707917cb | 581 | page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
582 | if (!page) |
583 | return NULL; | |
7a31f6f4 | 584 | |
e3c97196 RK |
585 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
586 | DMA_TO_DEVICE); | |
587 | if (dma_mapping_error(smmu->dev, dma)) { | |
588 | __free_page(page); | |
589 | return NULL; | |
590 | } | |
591 | ||
592 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
593 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
594 | DMA_TO_DEVICE); | |
595 | __free_page(page); | |
596 | return NULL; | |
597 | } | |
598 | ||
853520fa RK |
599 | as->pts[pde] = page; |
600 | ||
4080e99b RK |
601 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
602 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
603 | |
604 | *dmap = dma; | |
89184651 | 605 | } else { |
4080e99b RK |
606 | u32 *pd = page_address(as->pd); |
607 | ||
96d3ab80 | 608 | *dmap = smmu_pde_to_dma(smmu, pd[pde]); |
7a31f6f4 HD |
609 | } |
610 | ||
7ffc6f06 RK |
611 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
612 | } | |
0b42c7c1 | 613 | |
7ffc6f06 RK |
614 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
615 | { | |
616 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 617 | |
7ffc6f06 | 618 | as->count[pd_index]++; |
89184651 | 619 | } |
39abf8aa | 620 | |
b98e34f0 | 621 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 622 | { |
34d35f8c | 623 | unsigned int pde = iova_pd_index(iova); |
853520fa | 624 | struct page *page = as->pts[pde]; |
39abf8aa | 625 | |
89184651 TR |
626 | /* |
627 | * When no entries in this page table are used anymore, return the | |
628 | * memory page to the system. | |
629 | */ | |
32924c76 | 630 | if (--as->count[pde] == 0) { |
4080e99b RK |
631 | struct tegra_smmu *smmu = as->smmu; |
632 | u32 *pd = page_address(as->pd); | |
96d3ab80 | 633 | dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]); |
39abf8aa | 634 | |
4080e99b | 635 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 636 | |
e3c97196 | 637 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 638 | __free_page(page); |
853520fa | 639 | as->pts[pde] = NULL; |
39abf8aa | 640 | } |
39abf8aa HD |
641 | } |
642 | ||
8482ee5e | 643 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 644 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
645 | { |
646 | struct tegra_smmu *smmu = as->smmu; | |
647 | unsigned long offset = offset_in_page(pte); | |
648 | ||
649 | *pte = val; | |
650 | ||
e3c97196 RK |
651 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
652 | 4, DMA_TO_DEVICE); | |
653 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
654 | smmu_flush_tlb_group(smmu, as->id, iova); |
655 | smmu_flush(smmu); | |
656 | } | |
657 | ||
89184651 | 658 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
781ca2de | 659 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
39abf8aa | 660 | { |
d5f1a81c | 661 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 662 | dma_addr_t pte_dma; |
43d957b1 | 663 | u32 pte_attrs; |
89184651 | 664 | u32 *pte; |
39abf8aa | 665 | |
e3c97196 | 666 | pte = as_get_pte(as, iova, &pte_dma); |
89184651 TR |
667 | if (!pte) |
668 | return -ENOMEM; | |
39abf8aa | 669 | |
7ffc6f06 RK |
670 | /* If we aren't overwriting a pre-existing entry, increment use */ |
671 | if (*pte == 0) | |
672 | tegra_smmu_pte_get_use(as, iova); | |
673 | ||
43d957b1 DO |
674 | pte_attrs = SMMU_PTE_NONSECURE; |
675 | ||
676 | if (prot & IOMMU_READ) | |
677 | pte_attrs |= SMMU_PTE_READABLE; | |
678 | ||
679 | if (prot & IOMMU_WRITE) | |
680 | pte_attrs |= SMMU_PTE_WRITABLE; | |
681 | ||
e3c97196 | 682 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
43d957b1 | 683 | __phys_to_pfn(paddr) | pte_attrs); |
39abf8aa | 684 | |
39abf8aa HD |
685 | return 0; |
686 | } | |
687 | ||
89184651 | 688 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
56f8af5e | 689 | size_t size, struct iommu_iotlb_gather *gather) |
39abf8aa | 690 | { |
d5f1a81c | 691 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 692 | dma_addr_t pte_dma; |
89184651 | 693 | u32 *pte; |
39abf8aa | 694 | |
e3c97196 | 695 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 696 | if (!pte || !*pte) |
89184651 | 697 | return 0; |
39abf8aa | 698 | |
e3c97196 | 699 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
700 | tegra_smmu_pte_put_use(as, iova); |
701 | ||
89184651 | 702 | return size; |
39abf8aa HD |
703 | } |
704 | ||
89184651 TR |
705 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
706 | dma_addr_t iova) | |
39abf8aa | 707 | { |
d5f1a81c | 708 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 709 | unsigned long pfn; |
e3c97196 | 710 | dma_addr_t pte_dma; |
89184651 | 711 | u32 *pte; |
39abf8aa | 712 | |
e3c97196 | 713 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
714 | if (!pte || !*pte) |
715 | return 0; | |
716 | ||
804cb54c | 717 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 718 | |
89184651 | 719 | return PFN_PHYS(pfn); |
39abf8aa HD |
720 | } |
721 | ||
89184651 | 722 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 723 | { |
89184651 TR |
724 | struct platform_device *pdev; |
725 | struct tegra_mc *mc; | |
7a31f6f4 | 726 | |
89184651 TR |
727 | pdev = of_find_device_by_node(np); |
728 | if (!pdev) | |
729 | return NULL; | |
730 | ||
731 | mc = platform_get_drvdata(pdev); | |
732 | if (!mc) | |
733 | return NULL; | |
734 | ||
735 | return mc->smmu; | |
7a31f6f4 HD |
736 | } |
737 | ||
7f4c9176 TR |
738 | static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, |
739 | struct of_phandle_args *args) | |
740 | { | |
741 | const struct iommu_ops *ops = smmu->iommu.ops; | |
742 | int err; | |
743 | ||
744 | err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops); | |
745 | if (err < 0) { | |
746 | dev_err(dev, "failed to initialize fwspec: %d\n", err); | |
747 | return err; | |
748 | } | |
749 | ||
750 | err = ops->of_xlate(dev, args); | |
751 | if (err < 0) { | |
752 | dev_err(dev, "failed to parse SW group ID: %d\n", err); | |
753 | iommu_fwspec_free(dev); | |
754 | return err; | |
755 | } | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
b287ba73 | 760 | static struct iommu_device *tegra_smmu_probe_device(struct device *dev) |
7a31f6f4 | 761 | { |
89184651 | 762 | struct device_node *np = dev->of_node; |
7f4c9176 | 763 | struct tegra_smmu *smmu = NULL; |
89184651 TR |
764 | struct of_phandle_args args; |
765 | unsigned int index = 0; | |
7f4c9176 | 766 | int err; |
7a31f6f4 | 767 | |
89184651 TR |
768 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
769 | &args) == 0) { | |
89184651 TR |
770 | smmu = tegra_smmu_find(args.np); |
771 | if (smmu) { | |
7f4c9176 TR |
772 | err = tegra_smmu_configure(smmu, dev, &args); |
773 | of_node_put(args.np); | |
774 | ||
775 | if (err < 0) | |
b287ba73 | 776 | return ERR_PTR(err); |
7f4c9176 | 777 | |
89184651 TR |
778 | /* |
779 | * Only a single IOMMU master interface is currently | |
780 | * supported by the Linux kernel, so abort after the | |
781 | * first match. | |
782 | */ | |
a5616e24 | 783 | dev_iommu_priv_set(dev, smmu); |
0b480e44 | 784 | |
89184651 TR |
785 | break; |
786 | } | |
787 | ||
7f4c9176 | 788 | of_node_put(args.np); |
89184651 TR |
789 | index++; |
790 | } | |
791 | ||
7f4c9176 | 792 | if (!smmu) |
b287ba73 | 793 | return ERR_PTR(-ENODEV); |
d92e1f84 | 794 | |
b287ba73 | 795 | return &smmu->iommu; |
7a31f6f4 HD |
796 | } |
797 | ||
b287ba73 | 798 | static void tegra_smmu_release_device(struct device *dev) |
7a31f6f4 | 799 | { |
a5616e24 | 800 | dev_iommu_priv_set(dev, NULL); |
89184651 | 801 | } |
7a31f6f4 | 802 | |
7f4c9176 TR |
803 | static const struct tegra_smmu_group_soc * |
804 | tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) | |
805 | { | |
806 | unsigned int i, j; | |
807 | ||
808 | for (i = 0; i < smmu->soc->num_groups; i++) | |
809 | for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) | |
810 | if (smmu->soc->groups[i].swgroups[j] == swgroup) | |
811 | return &smmu->soc->groups[i]; | |
812 | ||
813 | return NULL; | |
814 | } | |
815 | ||
816 | static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu, | |
817 | unsigned int swgroup) | |
818 | { | |
819 | const struct tegra_smmu_group_soc *soc; | |
820 | struct tegra_smmu_group *group; | |
5b30fbfa | 821 | struct iommu_group *grp; |
7f4c9176 TR |
822 | |
823 | soc = tegra_smmu_find_group(smmu, swgroup); | |
824 | if (!soc) | |
825 | return NULL; | |
826 | ||
827 | mutex_lock(&smmu->lock); | |
828 | ||
829 | list_for_each_entry(group, &smmu->groups, list) | |
830 | if (group->soc == soc) { | |
5b30fbfa | 831 | grp = iommu_group_ref_get(group->group); |
7f4c9176 | 832 | mutex_unlock(&smmu->lock); |
5b30fbfa | 833 | return grp; |
7f4c9176 TR |
834 | } |
835 | ||
836 | group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL); | |
837 | if (!group) { | |
838 | mutex_unlock(&smmu->lock); | |
839 | return NULL; | |
840 | } | |
841 | ||
842 | INIT_LIST_HEAD(&group->list); | |
843 | group->soc = soc; | |
844 | ||
845 | group->group = iommu_group_alloc(); | |
83476bfa | 846 | if (IS_ERR(group->group)) { |
7f4c9176 TR |
847 | devm_kfree(smmu->dev, group); |
848 | mutex_unlock(&smmu->lock); | |
849 | return NULL; | |
850 | } | |
851 | ||
00295702 | 852 | iommu_group_set_name(group->group, soc->name); |
7f4c9176 TR |
853 | list_add_tail(&group->list, &smmu->groups); |
854 | mutex_unlock(&smmu->lock); | |
855 | ||
856 | return group->group; | |
857 | } | |
858 | ||
859 | static struct iommu_group *tegra_smmu_device_group(struct device *dev) | |
860 | { | |
db5d6a70 | 861 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
a5616e24 | 862 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
7f4c9176 TR |
863 | struct iommu_group *group; |
864 | ||
865 | group = tegra_smmu_group_get(smmu, fwspec->ids[0]); | |
866 | if (!group) | |
867 | group = generic_device_group(dev); | |
868 | ||
869 | return group; | |
870 | } | |
871 | ||
872 | static int tegra_smmu_of_xlate(struct device *dev, | |
873 | struct of_phandle_args *args) | |
874 | { | |
875 | u32 id = args->args[0]; | |
876 | ||
877 | return iommu_fwspec_add_ids(dev, &id, 1); | |
878 | } | |
879 | ||
89184651 TR |
880 | static const struct iommu_ops tegra_smmu_ops = { |
881 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
882 | .domain_alloc = tegra_smmu_domain_alloc, |
883 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
884 | .attach_dev = tegra_smmu_attach_dev, |
885 | .detach_dev = tegra_smmu_detach_dev, | |
b287ba73 JR |
886 | .probe_device = tegra_smmu_probe_device, |
887 | .release_device = tegra_smmu_release_device, | |
7f4c9176 | 888 | .device_group = tegra_smmu_device_group, |
89184651 TR |
889 | .map = tegra_smmu_map, |
890 | .unmap = tegra_smmu_unmap, | |
89184651 | 891 | .iova_to_phys = tegra_smmu_iova_to_phys, |
7f4c9176 | 892 | .of_xlate = tegra_smmu_of_xlate, |
89184651 TR |
893 | .pgsize_bitmap = SZ_4K, |
894 | }; | |
7a31f6f4 | 895 | |
89184651 TR |
896 | static void tegra_smmu_ahb_enable(void) |
897 | { | |
898 | static const struct of_device_id ahb_match[] = { | |
899 | { .compatible = "nvidia,tegra30-ahb", }, | |
900 | { } | |
901 | }; | |
902 | struct device_node *ahb; | |
7a31f6f4 | 903 | |
89184651 TR |
904 | ahb = of_find_matching_node(NULL, ahb_match); |
905 | if (ahb) { | |
906 | tegra_ahb_enable_smmu(ahb); | |
907 | of_node_put(ahb); | |
7a31f6f4 | 908 | } |
89184651 | 909 | } |
7a31f6f4 | 910 | |
d1313e78 TR |
911 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
912 | { | |
913 | struct tegra_smmu *smmu = s->private; | |
914 | unsigned int i; | |
915 | u32 value; | |
916 | ||
917 | seq_printf(s, "swgroup enabled ASID\n"); | |
918 | seq_printf(s, "------------------------\n"); | |
919 | ||
920 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
921 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
922 | const char *status; | |
923 | unsigned int asid; | |
924 | ||
925 | value = smmu_readl(smmu, group->reg); | |
926 | ||
927 | if (value & SMMU_ASID_ENABLE) | |
928 | status = "yes"; | |
929 | else | |
930 | status = "no"; | |
931 | ||
932 | asid = value & SMMU_ASID_MASK; | |
933 | ||
934 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
935 | asid); | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
062e52a5 | 941 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups); |
d1313e78 TR |
942 | |
943 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
944 | { | |
945 | struct tegra_smmu *smmu = s->private; | |
946 | unsigned int i; | |
947 | u32 value; | |
948 | ||
949 | seq_printf(s, "client enabled\n"); | |
950 | seq_printf(s, "--------------------\n"); | |
951 | ||
952 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
953 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
954 | const char *status; | |
955 | ||
956 | value = smmu_readl(smmu, client->smmu.reg); | |
957 | ||
958 | if (value & BIT(client->smmu.bit)) | |
959 | status = "yes"; | |
960 | else | |
961 | status = "no"; | |
962 | ||
963 | seq_printf(s, "%-12s %s\n", client->name, status); | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
062e52a5 | 969 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients); |
d1313e78 TR |
970 | |
971 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
972 | { | |
973 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
974 | if (!smmu->debugfs) | |
975 | return; | |
976 | ||
977 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
978 | &tegra_smmu_swgroups_fops); | |
979 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
980 | &tegra_smmu_clients_fops); | |
981 | } | |
982 | ||
983 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
984 | { | |
985 | debugfs_remove_recursive(smmu->debugfs); | |
986 | } | |
987 | ||
89184651 TR |
988 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
989 | const struct tegra_smmu_soc *soc, | |
990 | struct tegra_mc *mc) | |
991 | { | |
992 | struct tegra_smmu *smmu; | |
993 | size_t size; | |
994 | u32 value; | |
995 | int err; | |
7a31f6f4 | 996 | |
89184651 TR |
997 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
998 | if (!smmu) | |
999 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 1000 | |
89184651 TR |
1001 | /* |
1002 | * This is a bit of a hack. Ideally we'd want to simply return this | |
1003 | * value. However the IOMMU registration process will attempt to add | |
1004 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
1005 | * not to rely on global variables to track the IOMMU instance, we | |
b287ba73 | 1006 | * set it here so that it can be looked up from the .probe_device() |
89184651 TR |
1007 | * callback via the IOMMU device's .drvdata field. |
1008 | */ | |
1009 | mc->smmu = smmu; | |
0760e8fa | 1010 | |
89184651 | 1011 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 1012 | |
89184651 TR |
1013 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
1014 | if (!smmu->asids) | |
1015 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 1016 | |
7f4c9176 | 1017 | INIT_LIST_HEAD(&smmu->groups); |
89184651 | 1018 | mutex_init(&smmu->lock); |
7a31f6f4 | 1019 | |
89184651 TR |
1020 | smmu->regs = mc->regs; |
1021 | smmu->soc = soc; | |
1022 | smmu->dev = dev; | |
1023 | smmu->mc = mc; | |
7a31f6f4 | 1024 | |
804cb54c TR |
1025 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
1026 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
1027 | mc->soc->num_address_bits, smmu->pfn_mask); | |
11cec15b TR |
1028 | smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; |
1029 | dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, | |
1030 | smmu->tlb_mask); | |
804cb54c | 1031 | |
89184651 | 1032 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 1033 | |
89184651 TR |
1034 | if (soc->supports_request_limit) |
1035 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 1036 | |
89184651 | 1037 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 1038 | |
89184651 | 1039 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
11cec15b | 1040 | SMMU_TLB_CONFIG_ACTIVE_LINES(smmu); |
7a31f6f4 | 1041 | |
89184651 TR |
1042 | if (soc->supports_round_robin_arbitration) |
1043 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 1044 | |
89184651 | 1045 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 1046 | |
b8fe0382 | 1047 | smmu_flush_ptc_all(smmu); |
89184651 TR |
1048 | smmu_flush_tlb(smmu); |
1049 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
1050 | smmu_flush(smmu); | |
1051 | ||
1052 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 1053 | |
0b480e44 JR |
1054 | err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev)); |
1055 | if (err) | |
1056 | return ERR_PTR(err); | |
1057 | ||
1058 | iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops); | |
7f4c9176 | 1059 | iommu_device_set_fwnode(&smmu->iommu, dev->fwnode); |
0b480e44 JR |
1060 | |
1061 | err = iommu_device_register(&smmu->iommu); | |
1062 | if (err) { | |
1063 | iommu_device_sysfs_remove(&smmu->iommu); | |
1064 | return ERR_PTR(err); | |
1065 | } | |
1066 | ||
96302d89 JR |
1067 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
1068 | if (err < 0) { | |
1069 | iommu_device_unregister(&smmu->iommu); | |
1070 | iommu_device_sysfs_remove(&smmu->iommu); | |
1071 | return ERR_PTR(err); | |
1072 | } | |
1073 | ||
d1313e78 TR |
1074 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1075 | tegra_smmu_debugfs_init(smmu); | |
1076 | ||
89184651 TR |
1077 | return smmu; |
1078 | } | |
d1313e78 TR |
1079 | |
1080 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
1081 | { | |
0b480e44 JR |
1082 | iommu_device_unregister(&smmu->iommu); |
1083 | iommu_device_sysfs_remove(&smmu->iommu); | |
1084 | ||
d1313e78 TR |
1085 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1086 | tegra_smmu_debugfs_exit(smmu); | |
1087 | } |