Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7a31f6f4 | 2 | /* |
89184651 | 3 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 HD |
4 | */ |
5 | ||
804cb54c | 6 | #include <linux/bitops.h> |
d1313e78 | 7 | #include <linux/debugfs.h> |
bc5e6dea | 8 | #include <linux/err.h> |
7a31f6f4 | 9 | #include <linux/iommu.h> |
89184651 | 10 | #include <linux/kernel.h> |
0760e8fa | 11 | #include <linux/of.h> |
89184651 TR |
12 | #include <linux/of_device.h> |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/slab.h> | |
404d0b30 | 15 | #include <linux/spinlock.h> |
461a6946 | 16 | #include <linux/dma-mapping.h> |
306a7f91 TR |
17 | |
18 | #include <soc/tegra/ahb.h> | |
89184651 | 19 | #include <soc/tegra/mc.h> |
7a31f6f4 | 20 | |
7f4c9176 TR |
21 | struct tegra_smmu_group { |
22 | struct list_head list; | |
1ea5440e | 23 | struct tegra_smmu *smmu; |
7f4c9176 TR |
24 | const struct tegra_smmu_group_soc *soc; |
25 | struct iommu_group *group; | |
26 | }; | |
27 | ||
89184651 TR |
28 | struct tegra_smmu { |
29 | void __iomem *regs; | |
30 | struct device *dev; | |
e6bc5933 | 31 | |
89184651 TR |
32 | struct tegra_mc *mc; |
33 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 34 | |
7f4c9176 TR |
35 | struct list_head groups; |
36 | ||
804cb54c | 37 | unsigned long pfn_mask; |
11cec15b | 38 | unsigned long tlb_mask; |
804cb54c | 39 | |
89184651 TR |
40 | unsigned long *asids; |
41 | struct mutex lock; | |
39abf8aa | 42 | |
89184651 | 43 | struct list_head list; |
d1313e78 TR |
44 | |
45 | struct dentry *debugfs; | |
0b480e44 JR |
46 | |
47 | struct iommu_device iommu; /* IOMMU Core code handle */ | |
7a31f6f4 | 48 | }; |
7a31f6f4 | 49 | |
89184651 | 50 | struct tegra_smmu_as { |
d5f1a81c | 51 | struct iommu_domain domain; |
89184651 TR |
52 | struct tegra_smmu *smmu; |
53 | unsigned int use_count; | |
404d0b30 | 54 | spinlock_t lock; |
32924c76 | 55 | u32 *count; |
853520fa | 56 | struct page **pts; |
89184651 | 57 | struct page *pd; |
e3c97196 | 58 | dma_addr_t pd_dma; |
89184651 TR |
59 | unsigned id; |
60 | u32 attr; | |
7a31f6f4 HD |
61 | }; |
62 | ||
d5f1a81c JR |
63 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
64 | { | |
65 | return container_of(dom, struct tegra_smmu_as, domain); | |
66 | } | |
67 | ||
89184651 TR |
68 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
69 | unsigned long offset) | |
70 | { | |
71 | writel(value, smmu->regs + offset); | |
72 | } | |
7a31f6f4 | 73 | |
89184651 TR |
74 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
75 | { | |
76 | return readl(smmu->regs + offset); | |
77 | } | |
5a2c937a | 78 | |
89184651 TR |
79 | #define SMMU_CONFIG 0x010 |
80 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 81 | |
89184651 TR |
82 | #define SMMU_TLB_CONFIG 0x14 |
83 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
84 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
11cec15b TR |
85 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ |
86 | ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask) | |
0760e8fa | 87 | |
89184651 TR |
88 | #define SMMU_PTC_CONFIG 0x18 |
89 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
90 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
91 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 92 | |
89184651 TR |
93 | #define SMMU_PTB_ASID 0x01c |
94 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 95 | |
89184651 | 96 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 97 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 98 | |
e3c97196 | 99 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 100 | |
89184651 TR |
101 | #define SMMU_TLB_FLUSH 0x030 |
102 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
103 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
104 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
89184651 TR |
105 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
106 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
107 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
108 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
109 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 110 | |
89184651 TR |
111 | #define SMMU_PTC_FLUSH 0x034 |
112 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
113 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 114 | |
89184651 TR |
115 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
116 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 117 | |
89184651 TR |
118 | /* per-SWGROUP SMMU_*_ASID register */ |
119 | #define SMMU_ASID_ENABLE (1 << 31) | |
120 | #define SMMU_ASID_MASK 0x7f | |
121 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 122 | |
89184651 TR |
123 | /* page table definitions */ |
124 | #define SMMU_NUM_PDE 1024 | |
125 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 126 | |
89184651 TR |
127 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
128 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 129 | |
89184651 TR |
130 | #define SMMU_PDE_SHIFT 22 |
131 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 132 | |
89184651 TR |
133 | #define SMMU_PD_READABLE (1 << 31) |
134 | #define SMMU_PD_WRITABLE (1 << 30) | |
135 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 136 | |
89184651 TR |
137 | #define SMMU_PDE_READABLE (1 << 31) |
138 | #define SMMU_PDE_WRITABLE (1 << 30) | |
139 | #define SMMU_PDE_NONSECURE (1 << 29) | |
140 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 141 | |
89184651 TR |
142 | #define SMMU_PTE_READABLE (1 << 31) |
143 | #define SMMU_PTE_WRITABLE (1 << 30) | |
144 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 145 | |
89184651 TR |
146 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
147 | SMMU_PDE_NONSECURE) | |
7a31f6f4 | 148 | |
34d35f8c RK |
149 | static unsigned int iova_pd_index(unsigned long iova) |
150 | { | |
151 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
152 | } | |
153 | ||
154 | static unsigned int iova_pt_index(unsigned long iova) | |
155 | { | |
156 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
157 | } | |
158 | ||
e3c97196 | 159 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 160 | { |
e3c97196 RK |
161 | addr >>= 12; |
162 | return (addr & smmu->pfn_mask) == addr; | |
163 | } | |
4b3c7d10 | 164 | |
96d3ab80 | 165 | static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde) |
e3c97196 | 166 | { |
96d3ab80 | 167 | return (dma_addr_t)(pde & smmu->pfn_mask) << 12; |
4b3c7d10 RK |
168 | } |
169 | ||
b8fe0382 RK |
170 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
171 | { | |
172 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
173 | } | |
174 | ||
e3c97196 | 175 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 176 | unsigned long offset) |
7a31f6f4 | 177 | { |
89184651 TR |
178 | u32 value; |
179 | ||
b8fe0382 | 180 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 181 | |
b8fe0382 | 182 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
183 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
184 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 185 | #else |
b8fe0382 | 186 | value = 0; |
89184651 | 187 | #endif |
b8fe0382 | 188 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 189 | } |
89184651 | 190 | |
e3c97196 | 191 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 192 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
193 | } |
194 | ||
89184651 | 195 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 196 | { |
89184651 | 197 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
198 | } |
199 | ||
89184651 TR |
200 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
201 | unsigned long asid) | |
7a31f6f4 | 202 | { |
89184651 | 203 | u32 value; |
7a31f6f4 | 204 | |
43a0541e DO |
205 | if (smmu->soc->num_asids == 4) |
206 | value = (asid & 0x3) << 29; | |
207 | else | |
208 | value = (asid & 0x7f) << 24; | |
209 | ||
210 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
89184651 | 211 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
212 | } |
213 | ||
89184651 TR |
214 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
215 | unsigned long asid, | |
216 | unsigned long iova) | |
7a31f6f4 | 217 | { |
89184651 | 218 | u32 value; |
7a31f6f4 | 219 | |
43a0541e DO |
220 | if (smmu->soc->num_asids == 4) |
221 | value = (asid & 0x3) << 29; | |
222 | else | |
223 | value = (asid & 0x7f) << 24; | |
224 | ||
225 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
89184651 | 226 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
227 | } |
228 | ||
89184651 TR |
229 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
230 | unsigned long asid, | |
231 | unsigned long iova) | |
7a31f6f4 | 232 | { |
89184651 | 233 | u32 value; |
7a31f6f4 | 234 | |
43a0541e DO |
235 | if (smmu->soc->num_asids == 4) |
236 | value = (asid & 0x3) << 29; | |
237 | else | |
238 | value = (asid & 0x7f) << 24; | |
239 | ||
240 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
89184651 | 241 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
242 | } |
243 | ||
89184651 | 244 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 245 | { |
446152d5 | 246 | smmu_readl(smmu, SMMU_PTB_ASID); |
7a31f6f4 HD |
247 | } |
248 | ||
89184651 | 249 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 250 | { |
89184651 | 251 | unsigned long id; |
7a31f6f4 | 252 | |
89184651 | 253 | mutex_lock(&smmu->lock); |
7a31f6f4 | 254 | |
89184651 TR |
255 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
256 | if (id >= smmu->soc->num_asids) { | |
257 | mutex_unlock(&smmu->lock); | |
258 | return -ENOSPC; | |
7a31f6f4 | 259 | } |
7a31f6f4 | 260 | |
89184651 TR |
261 | set_bit(id, smmu->asids); |
262 | *idp = id; | |
263 | ||
264 | mutex_unlock(&smmu->lock); | |
265 | return 0; | |
7a31f6f4 HD |
266 | } |
267 | ||
89184651 | 268 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 269 | { |
89184651 TR |
270 | mutex_lock(&smmu->lock); |
271 | clear_bit(id, smmu->asids); | |
272 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 273 | } |
89184651 TR |
274 | |
275 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 276 | { |
89184651 | 277 | return false; |
7a31f6f4 | 278 | } |
7a31f6f4 | 279 | |
d5f1a81c | 280 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 281 | { |
89184651 | 282 | struct tegra_smmu_as *as; |
7a31f6f4 | 283 | |
d5f1a81c JR |
284 | if (type != IOMMU_DOMAIN_UNMANAGED) |
285 | return NULL; | |
286 | ||
89184651 TR |
287 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
288 | if (!as) | |
d5f1a81c | 289 | return NULL; |
7a31f6f4 | 290 | |
89184651 | 291 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 292 | |
707917cb | 293 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
294 | if (!as->pd) { |
295 | kfree(as); | |
d5f1a81c | 296 | return NULL; |
7a31f6f4 | 297 | } |
9e971a03 | 298 | |
32924c76 | 299 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
300 | if (!as->count) { |
301 | __free_page(as->pd); | |
302 | kfree(as); | |
d5f1a81c | 303 | return NULL; |
7a31f6f4 | 304 | } |
9e971a03 | 305 | |
853520fa RK |
306 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
307 | if (!as->pts) { | |
32924c76 | 308 | kfree(as->count); |
853520fa RK |
309 | __free_page(as->pd); |
310 | kfree(as); | |
311 | return NULL; | |
312 | } | |
313 | ||
404d0b30 DO |
314 | spin_lock_init(&as->lock); |
315 | ||
471d9144 | 316 | /* setup aperture */ |
7f65ef01 JR |
317 | as->domain.geometry.aperture_start = 0; |
318 | as->domain.geometry.aperture_end = 0xffffffff; | |
319 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 320 | |
d5f1a81c | 321 | return &as->domain; |
7a31f6f4 HD |
322 | } |
323 | ||
d5f1a81c | 324 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 325 | { |
d5f1a81c | 326 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 327 | |
89184651 | 328 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 329 | |
4f97031f DO |
330 | WARN_ON_ONCE(as->use_count); |
331 | kfree(as->count); | |
332 | kfree(as->pts); | |
89184651 | 333 | kfree(as); |
7a31f6f4 HD |
334 | } |
335 | ||
89184651 TR |
336 | static const struct tegra_smmu_swgroup * |
337 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 338 | { |
89184651 TR |
339 | const struct tegra_smmu_swgroup *group = NULL; |
340 | unsigned int i; | |
7a31f6f4 | 341 | |
89184651 TR |
342 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
343 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
344 | group = &smmu->soc->swgroups[i]; | |
345 | break; | |
346 | } | |
347 | } | |
7a31f6f4 | 348 | |
89184651 | 349 | return group; |
7a31f6f4 HD |
350 | } |
351 | ||
89184651 TR |
352 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
353 | unsigned int asid) | |
7a31f6f4 | 354 | { |
89184651 TR |
355 | const struct tegra_smmu_swgroup *group; |
356 | unsigned int i; | |
357 | u32 value; | |
7a31f6f4 | 358 | |
e31e5929 NK |
359 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
360 | if (group) { | |
361 | value = smmu_readl(smmu, group->reg); | |
362 | value &= ~SMMU_ASID_MASK; | |
363 | value |= SMMU_ASID_VALUE(asid); | |
364 | value |= SMMU_ASID_ENABLE; | |
365 | smmu_writel(smmu, value, group->reg); | |
366 | } else { | |
367 | pr_warn("%s group from swgroup %u not found\n", __func__, | |
368 | swgroup); | |
369 | /* No point moving ahead if group was not found */ | |
370 | return; | |
371 | } | |
372 | ||
89184651 TR |
373 | for (i = 0; i < smmu->soc->num_clients; i++) { |
374 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 375 | |
89184651 TR |
376 | if (client->swgroup != swgroup) |
377 | continue; | |
7a31f6f4 | 378 | |
89184651 TR |
379 | value = smmu_readl(smmu, client->smmu.reg); |
380 | value |= BIT(client->smmu.bit); | |
381 | smmu_writel(smmu, value, client->smmu.reg); | |
382 | } | |
7a31f6f4 HD |
383 | } |
384 | ||
89184651 TR |
385 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
386 | unsigned int asid) | |
7a31f6f4 | 387 | { |
89184651 TR |
388 | const struct tegra_smmu_swgroup *group; |
389 | unsigned int i; | |
390 | u32 value; | |
7a31f6f4 | 391 | |
89184651 TR |
392 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
393 | if (group) { | |
394 | value = smmu_readl(smmu, group->reg); | |
395 | value &= ~SMMU_ASID_MASK; | |
396 | value |= SMMU_ASID_VALUE(asid); | |
397 | value &= ~SMMU_ASID_ENABLE; | |
398 | smmu_writel(smmu, value, group->reg); | |
399 | } | |
7a31f6f4 | 400 | |
89184651 TR |
401 | for (i = 0; i < smmu->soc->num_clients; i++) { |
402 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 403 | |
89184651 TR |
404 | if (client->swgroup != swgroup) |
405 | continue; | |
7a31f6f4 | 406 | |
89184651 TR |
407 | value = smmu_readl(smmu, client->smmu.reg); |
408 | value &= ~BIT(client->smmu.bit); | |
409 | smmu_writel(smmu, value, client->smmu.reg); | |
410 | } | |
7a31f6f4 HD |
411 | } |
412 | ||
89184651 TR |
413 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
414 | struct tegra_smmu_as *as) | |
7a31f6f4 | 415 | { |
89184651 | 416 | u32 value; |
7a31f6f4 HD |
417 | int err; |
418 | ||
89184651 TR |
419 | if (as->use_count > 0) { |
420 | as->use_count++; | |
421 | return 0; | |
7a31f6f4 | 422 | } |
7a31f6f4 | 423 | |
e3c97196 RK |
424 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
425 | DMA_TO_DEVICE); | |
426 | if (dma_mapping_error(smmu->dev, as->pd_dma)) | |
427 | return -ENOMEM; | |
428 | ||
429 | /* We can't handle 64-bit DMA addresses */ | |
430 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
431 | err = -ENOMEM; | |
432 | goto err_unmap; | |
433 | } | |
434 | ||
89184651 TR |
435 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
436 | if (err < 0) | |
e3c97196 | 437 | goto err_unmap; |
7a31f6f4 | 438 | |
e3c97196 | 439 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 440 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 441 | |
89184651 | 442 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 443 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
444 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
445 | smmu_flush(smmu); | |
7a31f6f4 | 446 | |
89184651 TR |
447 | as->smmu = smmu; |
448 | as->use_count++; | |
7a31f6f4 | 449 | |
89184651 | 450 | return 0; |
e3c97196 RK |
451 | |
452 | err_unmap: | |
453 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
454 | return err; | |
7a31f6f4 HD |
455 | } |
456 | ||
89184651 TR |
457 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
458 | struct tegra_smmu_as *as) | |
7a31f6f4 | 459 | { |
89184651 TR |
460 | if (--as->use_count > 0) |
461 | return; | |
462 | ||
463 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
464 | |
465 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
466 | ||
89184651 | 467 | as->smmu = NULL; |
7a31f6f4 HD |
468 | } |
469 | ||
89184651 TR |
470 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
471 | struct device *dev) | |
7a31f6f4 | 472 | { |
a5616e24 | 473 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
d5f1a81c | 474 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
475 | struct device_node *np = dev->of_node; |
476 | struct of_phandle_args args; | |
477 | unsigned int index = 0; | |
478 | int err = 0; | |
7a31f6f4 | 479 | |
89184651 TR |
480 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
481 | &args)) { | |
482 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 483 | |
89184651 TR |
484 | if (args.np != smmu->dev->of_node) { |
485 | of_node_put(args.np); | |
d2453b2c | 486 | continue; |
89184651 | 487 | } |
d2453b2c | 488 | |
89184651 | 489 | of_node_put(args.np); |
d2453b2c | 490 | |
89184651 TR |
491 | err = tegra_smmu_as_prepare(smmu, as); |
492 | if (err < 0) | |
493 | return err; | |
494 | ||
495 | tegra_smmu_enable(smmu, swgroup, as->id); | |
496 | index++; | |
7a31f6f4 | 497 | } |
7a31f6f4 | 498 | |
89184651 TR |
499 | if (index == 0) |
500 | return -ENODEV; | |
7a31f6f4 | 501 | |
89184651 TR |
502 | return 0; |
503 | } | |
7a31f6f4 | 504 | |
89184651 TR |
505 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
506 | { | |
d5f1a81c | 507 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
508 | struct device_node *np = dev->of_node; |
509 | struct tegra_smmu *smmu = as->smmu; | |
510 | struct of_phandle_args args; | |
511 | unsigned int index = 0; | |
7a31f6f4 | 512 | |
89184651 TR |
513 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
514 | &args)) { | |
515 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 516 | |
89184651 TR |
517 | if (args.np != smmu->dev->of_node) { |
518 | of_node_put(args.np); | |
519 | continue; | |
520 | } | |
23349902 | 521 | |
89184651 | 522 | of_node_put(args.np); |
7a31f6f4 | 523 | |
89184651 TR |
524 | tegra_smmu_disable(smmu, swgroup, as->id); |
525 | tegra_smmu_as_unprepare(smmu, as); | |
526 | index++; | |
527 | } | |
7a31f6f4 HD |
528 | } |
529 | ||
4080e99b RK |
530 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
531 | u32 value) | |
532 | { | |
533 | unsigned int pd_index = iova_pd_index(iova); | |
534 | struct tegra_smmu *smmu = as->smmu; | |
535 | u32 *pd = page_address(as->pd); | |
536 | unsigned long offset = pd_index * sizeof(*pd); | |
537 | ||
538 | /* Set the page directory entry first */ | |
539 | pd[pd_index] = value; | |
540 | ||
541 | /* The flush the page directory entry from caches */ | |
542 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
543 | sizeof(*pd), DMA_TO_DEVICE); | |
544 | ||
545 | /* And flush the iommu */ | |
546 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
547 | smmu_flush_tlb_section(smmu, as->id, iova); | |
548 | smmu_flush(smmu); | |
549 | } | |
550 | ||
0b42c7c1 RK |
551 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
552 | { | |
553 | u32 *pt = page_address(pt_page); | |
554 | ||
555 | return pt + iova_pt_index(iova); | |
556 | } | |
557 | ||
558 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 559 | dma_addr_t *dmap) |
0b42c7c1 RK |
560 | { |
561 | unsigned int pd_index = iova_pd_index(iova); | |
96d3ab80 | 562 | struct tegra_smmu *smmu = as->smmu; |
0b42c7c1 | 563 | struct page *pt_page; |
e3c97196 | 564 | u32 *pd; |
0b42c7c1 | 565 | |
853520fa RK |
566 | pt_page = as->pts[pd_index]; |
567 | if (!pt_page) | |
0b42c7c1 RK |
568 | return NULL; |
569 | ||
e3c97196 | 570 | pd = page_address(as->pd); |
96d3ab80 | 571 | *dmap = smmu_pde_to_dma(smmu, pd[pd_index]); |
0b42c7c1 RK |
572 | |
573 | return tegra_smmu_pte_offset(pt_page, iova); | |
574 | } | |
575 | ||
89184651 | 576 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
404d0b30 | 577 | dma_addr_t *dmap, struct page *page) |
7a31f6f4 | 578 | { |
34d35f8c | 579 | unsigned int pde = iova_pd_index(iova); |
89184651 | 580 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 581 | |
853520fa | 582 | if (!as->pts[pde]) { |
e3c97196 RK |
583 | dma_addr_t dma; |
584 | ||
e3c97196 RK |
585 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
586 | DMA_TO_DEVICE); | |
587 | if (dma_mapping_error(smmu->dev, dma)) { | |
588 | __free_page(page); | |
589 | return NULL; | |
590 | } | |
591 | ||
592 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
593 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
594 | DMA_TO_DEVICE); | |
595 | __free_page(page); | |
596 | return NULL; | |
597 | } | |
598 | ||
853520fa RK |
599 | as->pts[pde] = page; |
600 | ||
4080e99b RK |
601 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
602 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
603 | |
604 | *dmap = dma; | |
89184651 | 605 | } else { |
4080e99b RK |
606 | u32 *pd = page_address(as->pd); |
607 | ||
96d3ab80 | 608 | *dmap = smmu_pde_to_dma(smmu, pd[pde]); |
7a31f6f4 HD |
609 | } |
610 | ||
7ffc6f06 RK |
611 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
612 | } | |
0b42c7c1 | 613 | |
7ffc6f06 RK |
614 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
615 | { | |
616 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 617 | |
7ffc6f06 | 618 | as->count[pd_index]++; |
89184651 | 619 | } |
39abf8aa | 620 | |
b98e34f0 | 621 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 622 | { |
34d35f8c | 623 | unsigned int pde = iova_pd_index(iova); |
853520fa | 624 | struct page *page = as->pts[pde]; |
39abf8aa | 625 | |
89184651 TR |
626 | /* |
627 | * When no entries in this page table are used anymore, return the | |
628 | * memory page to the system. | |
629 | */ | |
32924c76 | 630 | if (--as->count[pde] == 0) { |
4080e99b RK |
631 | struct tegra_smmu *smmu = as->smmu; |
632 | u32 *pd = page_address(as->pd); | |
96d3ab80 | 633 | dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]); |
39abf8aa | 634 | |
4080e99b | 635 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 636 | |
e3c97196 | 637 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 638 | __free_page(page); |
853520fa | 639 | as->pts[pde] = NULL; |
39abf8aa | 640 | } |
39abf8aa HD |
641 | } |
642 | ||
8482ee5e | 643 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 644 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
645 | { |
646 | struct tegra_smmu *smmu = as->smmu; | |
647 | unsigned long offset = offset_in_page(pte); | |
648 | ||
649 | *pte = val; | |
650 | ||
e3c97196 RK |
651 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
652 | 4, DMA_TO_DEVICE); | |
653 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
654 | smmu_flush_tlb_group(smmu, as->id, iova); |
655 | smmu_flush(smmu); | |
656 | } | |
657 | ||
404d0b30 DO |
658 | static struct page *as_get_pde_page(struct tegra_smmu_as *as, |
659 | unsigned long iova, gfp_t gfp, | |
660 | unsigned long *flags) | |
661 | { | |
662 | unsigned int pde = iova_pd_index(iova); | |
663 | struct page *page = as->pts[pde]; | |
664 | ||
665 | /* at first check whether allocation needs to be done at all */ | |
666 | if (page) | |
667 | return page; | |
668 | ||
669 | /* | |
670 | * In order to prevent exhaustion of the atomic memory pool, we | |
671 | * allocate page in a sleeping context if GFP flags permit. Hence | |
672 | * spinlock needs to be unlocked and re-locked after allocation. | |
673 | */ | |
674 | if (!(gfp & __GFP_ATOMIC)) | |
675 | spin_unlock_irqrestore(&as->lock, *flags); | |
676 | ||
677 | page = alloc_page(gfp | __GFP_DMA | __GFP_ZERO); | |
678 | ||
679 | if (!(gfp & __GFP_ATOMIC)) | |
680 | spin_lock_irqsave(&as->lock, *flags); | |
681 | ||
682 | /* | |
683 | * In a case of blocking allocation, a concurrent mapping may win | |
684 | * the PDE allocation. In this case the allocated page isn't needed | |
685 | * if allocation succeeded and the allocation failure isn't fatal. | |
686 | */ | |
687 | if (as->pts[pde]) { | |
688 | if (page) | |
689 | __free_page(page); | |
690 | ||
691 | page = as->pts[pde]; | |
692 | } | |
693 | ||
694 | return page; | |
695 | } | |
696 | ||
697 | static int | |
698 | __tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
699 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp, | |
700 | unsigned long *flags) | |
39abf8aa | 701 | { |
d5f1a81c | 702 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 703 | dma_addr_t pte_dma; |
404d0b30 | 704 | struct page *page; |
43d957b1 | 705 | u32 pte_attrs; |
89184651 | 706 | u32 *pte; |
39abf8aa | 707 | |
404d0b30 DO |
708 | page = as_get_pde_page(as, iova, gfp, flags); |
709 | if (!page) | |
710 | return -ENOMEM; | |
711 | ||
712 | pte = as_get_pte(as, iova, &pte_dma, page); | |
89184651 TR |
713 | if (!pte) |
714 | return -ENOMEM; | |
39abf8aa | 715 | |
7ffc6f06 RK |
716 | /* If we aren't overwriting a pre-existing entry, increment use */ |
717 | if (*pte == 0) | |
718 | tegra_smmu_pte_get_use(as, iova); | |
719 | ||
43d957b1 DO |
720 | pte_attrs = SMMU_PTE_NONSECURE; |
721 | ||
722 | if (prot & IOMMU_READ) | |
723 | pte_attrs |= SMMU_PTE_READABLE; | |
724 | ||
725 | if (prot & IOMMU_WRITE) | |
726 | pte_attrs |= SMMU_PTE_WRITABLE; | |
727 | ||
e3c97196 | 728 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
43d957b1 | 729 | __phys_to_pfn(paddr) | pte_attrs); |
39abf8aa | 730 | |
39abf8aa HD |
731 | return 0; |
732 | } | |
733 | ||
404d0b30 DO |
734 | static size_t |
735 | __tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
736 | size_t size, struct iommu_iotlb_gather *gather) | |
39abf8aa | 737 | { |
d5f1a81c | 738 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 739 | dma_addr_t pte_dma; |
89184651 | 740 | u32 *pte; |
39abf8aa | 741 | |
e3c97196 | 742 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 743 | if (!pte || !*pte) |
89184651 | 744 | return 0; |
39abf8aa | 745 | |
e3c97196 | 746 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
747 | tegra_smmu_pte_put_use(as, iova); |
748 | ||
89184651 | 749 | return size; |
39abf8aa HD |
750 | } |
751 | ||
404d0b30 DO |
752 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
753 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) | |
754 | { | |
755 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
756 | unsigned long flags; | |
757 | int ret; | |
758 | ||
759 | spin_lock_irqsave(&as->lock, flags); | |
760 | ret = __tegra_smmu_map(domain, iova, paddr, size, prot, gfp, &flags); | |
761 | spin_unlock_irqrestore(&as->lock, flags); | |
762 | ||
763 | return ret; | |
764 | } | |
765 | ||
766 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
767 | size_t size, struct iommu_iotlb_gather *gather) | |
768 | { | |
769 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
770 | unsigned long flags; | |
771 | ||
772 | spin_lock_irqsave(&as->lock, flags); | |
773 | size = __tegra_smmu_unmap(domain, iova, size, gather); | |
774 | spin_unlock_irqrestore(&as->lock, flags); | |
775 | ||
776 | return size; | |
777 | } | |
778 | ||
89184651 TR |
779 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
780 | dma_addr_t iova) | |
39abf8aa | 781 | { |
d5f1a81c | 782 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 783 | unsigned long pfn; |
e3c97196 | 784 | dma_addr_t pte_dma; |
89184651 | 785 | u32 *pte; |
39abf8aa | 786 | |
e3c97196 | 787 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
788 | if (!pte || !*pte) |
789 | return 0; | |
790 | ||
804cb54c | 791 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 792 | |
89184651 | 793 | return PFN_PHYS(pfn); |
39abf8aa HD |
794 | } |
795 | ||
89184651 | 796 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 797 | { |
89184651 TR |
798 | struct platform_device *pdev; |
799 | struct tegra_mc *mc; | |
7a31f6f4 | 800 | |
89184651 TR |
801 | pdev = of_find_device_by_node(np); |
802 | if (!pdev) | |
803 | return NULL; | |
804 | ||
805 | mc = platform_get_drvdata(pdev); | |
806 | if (!mc) | |
807 | return NULL; | |
808 | ||
809 | return mc->smmu; | |
7a31f6f4 HD |
810 | } |
811 | ||
7f4c9176 TR |
812 | static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, |
813 | struct of_phandle_args *args) | |
814 | { | |
815 | const struct iommu_ops *ops = smmu->iommu.ops; | |
816 | int err; | |
817 | ||
818 | err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops); | |
819 | if (err < 0) { | |
820 | dev_err(dev, "failed to initialize fwspec: %d\n", err); | |
821 | return err; | |
822 | } | |
823 | ||
824 | err = ops->of_xlate(dev, args); | |
825 | if (err < 0) { | |
826 | dev_err(dev, "failed to parse SW group ID: %d\n", err); | |
827 | iommu_fwspec_free(dev); | |
828 | return err; | |
829 | } | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
b287ba73 | 834 | static struct iommu_device *tegra_smmu_probe_device(struct device *dev) |
7a31f6f4 | 835 | { |
89184651 | 836 | struct device_node *np = dev->of_node; |
7f4c9176 | 837 | struct tegra_smmu *smmu = NULL; |
89184651 TR |
838 | struct of_phandle_args args; |
839 | unsigned int index = 0; | |
7f4c9176 | 840 | int err; |
7a31f6f4 | 841 | |
89184651 TR |
842 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
843 | &args) == 0) { | |
89184651 TR |
844 | smmu = tegra_smmu_find(args.np); |
845 | if (smmu) { | |
7f4c9176 TR |
846 | err = tegra_smmu_configure(smmu, dev, &args); |
847 | of_node_put(args.np); | |
848 | ||
849 | if (err < 0) | |
b287ba73 | 850 | return ERR_PTR(err); |
7f4c9176 | 851 | |
89184651 TR |
852 | /* |
853 | * Only a single IOMMU master interface is currently | |
854 | * supported by the Linux kernel, so abort after the | |
855 | * first match. | |
856 | */ | |
a5616e24 | 857 | dev_iommu_priv_set(dev, smmu); |
0b480e44 | 858 | |
89184651 TR |
859 | break; |
860 | } | |
861 | ||
7f4c9176 | 862 | of_node_put(args.np); |
89184651 TR |
863 | index++; |
864 | } | |
865 | ||
7f4c9176 | 866 | if (!smmu) |
b287ba73 | 867 | return ERR_PTR(-ENODEV); |
d92e1f84 | 868 | |
b287ba73 | 869 | return &smmu->iommu; |
7a31f6f4 HD |
870 | } |
871 | ||
b287ba73 | 872 | static void tegra_smmu_release_device(struct device *dev) |
7a31f6f4 | 873 | { |
a5616e24 | 874 | dev_iommu_priv_set(dev, NULL); |
89184651 | 875 | } |
7a31f6f4 | 876 | |
7f4c9176 TR |
877 | static const struct tegra_smmu_group_soc * |
878 | tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) | |
879 | { | |
880 | unsigned int i, j; | |
881 | ||
882 | for (i = 0; i < smmu->soc->num_groups; i++) | |
883 | for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) | |
884 | if (smmu->soc->groups[i].swgroups[j] == swgroup) | |
885 | return &smmu->soc->groups[i]; | |
886 | ||
887 | return NULL; | |
888 | } | |
889 | ||
1ea5440e TR |
890 | static void tegra_smmu_group_release(void *iommu_data) |
891 | { | |
892 | struct tegra_smmu_group *group = iommu_data; | |
893 | struct tegra_smmu *smmu = group->smmu; | |
894 | ||
895 | mutex_lock(&smmu->lock); | |
896 | list_del(&group->list); | |
897 | mutex_unlock(&smmu->lock); | |
898 | } | |
899 | ||
7f4c9176 TR |
900 | static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu, |
901 | unsigned int swgroup) | |
902 | { | |
903 | const struct tegra_smmu_group_soc *soc; | |
904 | struct tegra_smmu_group *group; | |
5b30fbfa | 905 | struct iommu_group *grp; |
7f4c9176 TR |
906 | |
907 | soc = tegra_smmu_find_group(smmu, swgroup); | |
908 | if (!soc) | |
909 | return NULL; | |
910 | ||
911 | mutex_lock(&smmu->lock); | |
912 | ||
913 | list_for_each_entry(group, &smmu->groups, list) | |
914 | if (group->soc == soc) { | |
5b30fbfa | 915 | grp = iommu_group_ref_get(group->group); |
7f4c9176 | 916 | mutex_unlock(&smmu->lock); |
5b30fbfa | 917 | return grp; |
7f4c9176 TR |
918 | } |
919 | ||
920 | group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL); | |
921 | if (!group) { | |
922 | mutex_unlock(&smmu->lock); | |
923 | return NULL; | |
924 | } | |
925 | ||
926 | INIT_LIST_HEAD(&group->list); | |
1ea5440e | 927 | group->smmu = smmu; |
7f4c9176 TR |
928 | group->soc = soc; |
929 | ||
930 | group->group = iommu_group_alloc(); | |
83476bfa | 931 | if (IS_ERR(group->group)) { |
7f4c9176 TR |
932 | devm_kfree(smmu->dev, group); |
933 | mutex_unlock(&smmu->lock); | |
934 | return NULL; | |
935 | } | |
936 | ||
1ea5440e | 937 | iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release); |
00295702 | 938 | iommu_group_set_name(group->group, soc->name); |
7f4c9176 TR |
939 | list_add_tail(&group->list, &smmu->groups); |
940 | mutex_unlock(&smmu->lock); | |
941 | ||
942 | return group->group; | |
943 | } | |
944 | ||
945 | static struct iommu_group *tegra_smmu_device_group(struct device *dev) | |
946 | { | |
db5d6a70 | 947 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
a5616e24 | 948 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
7f4c9176 TR |
949 | struct iommu_group *group; |
950 | ||
951 | group = tegra_smmu_group_get(smmu, fwspec->ids[0]); | |
952 | if (!group) | |
953 | group = generic_device_group(dev); | |
954 | ||
955 | return group; | |
956 | } | |
957 | ||
958 | static int tegra_smmu_of_xlate(struct device *dev, | |
959 | struct of_phandle_args *args) | |
960 | { | |
961 | u32 id = args->args[0]; | |
962 | ||
963 | return iommu_fwspec_add_ids(dev, &id, 1); | |
964 | } | |
965 | ||
89184651 TR |
966 | static const struct iommu_ops tegra_smmu_ops = { |
967 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
968 | .domain_alloc = tegra_smmu_domain_alloc, |
969 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
970 | .attach_dev = tegra_smmu_attach_dev, |
971 | .detach_dev = tegra_smmu_detach_dev, | |
b287ba73 JR |
972 | .probe_device = tegra_smmu_probe_device, |
973 | .release_device = tegra_smmu_release_device, | |
7f4c9176 | 974 | .device_group = tegra_smmu_device_group, |
89184651 TR |
975 | .map = tegra_smmu_map, |
976 | .unmap = tegra_smmu_unmap, | |
89184651 | 977 | .iova_to_phys = tegra_smmu_iova_to_phys, |
7f4c9176 | 978 | .of_xlate = tegra_smmu_of_xlate, |
89184651 TR |
979 | .pgsize_bitmap = SZ_4K, |
980 | }; | |
7a31f6f4 | 981 | |
89184651 TR |
982 | static void tegra_smmu_ahb_enable(void) |
983 | { | |
984 | static const struct of_device_id ahb_match[] = { | |
985 | { .compatible = "nvidia,tegra30-ahb", }, | |
986 | { } | |
987 | }; | |
988 | struct device_node *ahb; | |
7a31f6f4 | 989 | |
89184651 TR |
990 | ahb = of_find_matching_node(NULL, ahb_match); |
991 | if (ahb) { | |
992 | tegra_ahb_enable_smmu(ahb); | |
993 | of_node_put(ahb); | |
7a31f6f4 | 994 | } |
89184651 | 995 | } |
7a31f6f4 | 996 | |
d1313e78 TR |
997 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
998 | { | |
999 | struct tegra_smmu *smmu = s->private; | |
1000 | unsigned int i; | |
1001 | u32 value; | |
1002 | ||
1003 | seq_printf(s, "swgroup enabled ASID\n"); | |
1004 | seq_printf(s, "------------------------\n"); | |
1005 | ||
1006 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
1007 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
1008 | const char *status; | |
1009 | unsigned int asid; | |
1010 | ||
1011 | value = smmu_readl(smmu, group->reg); | |
1012 | ||
1013 | if (value & SMMU_ASID_ENABLE) | |
1014 | status = "yes"; | |
1015 | else | |
1016 | status = "no"; | |
1017 | ||
1018 | asid = value & SMMU_ASID_MASK; | |
1019 | ||
1020 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
1021 | asid); | |
1022 | } | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
062e52a5 | 1027 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups); |
d1313e78 TR |
1028 | |
1029 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
1030 | { | |
1031 | struct tegra_smmu *smmu = s->private; | |
1032 | unsigned int i; | |
1033 | u32 value; | |
1034 | ||
1035 | seq_printf(s, "client enabled\n"); | |
1036 | seq_printf(s, "--------------------\n"); | |
1037 | ||
1038 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
1039 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
1040 | const char *status; | |
1041 | ||
1042 | value = smmu_readl(smmu, client->smmu.reg); | |
1043 | ||
1044 | if (value & BIT(client->smmu.bit)) | |
1045 | status = "yes"; | |
1046 | else | |
1047 | status = "no"; | |
1048 | ||
1049 | seq_printf(s, "%-12s %s\n", client->name, status); | |
1050 | } | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
062e52a5 | 1055 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients); |
d1313e78 TR |
1056 | |
1057 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
1058 | { | |
1059 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
1060 | if (!smmu->debugfs) | |
1061 | return; | |
1062 | ||
1063 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
1064 | &tegra_smmu_swgroups_fops); | |
1065 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
1066 | &tegra_smmu_clients_fops); | |
1067 | } | |
1068 | ||
1069 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
1070 | { | |
1071 | debugfs_remove_recursive(smmu->debugfs); | |
1072 | } | |
1073 | ||
89184651 TR |
1074 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
1075 | const struct tegra_smmu_soc *soc, | |
1076 | struct tegra_mc *mc) | |
1077 | { | |
1078 | struct tegra_smmu *smmu; | |
1079 | size_t size; | |
1080 | u32 value; | |
1081 | int err; | |
7a31f6f4 | 1082 | |
89184651 TR |
1083 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
1084 | if (!smmu) | |
1085 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 1086 | |
89184651 TR |
1087 | /* |
1088 | * This is a bit of a hack. Ideally we'd want to simply return this | |
1089 | * value. However the IOMMU registration process will attempt to add | |
1090 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
1091 | * not to rely on global variables to track the IOMMU instance, we | |
b287ba73 | 1092 | * set it here so that it can be looked up from the .probe_device() |
89184651 TR |
1093 | * callback via the IOMMU device's .drvdata field. |
1094 | */ | |
1095 | mc->smmu = smmu; | |
0760e8fa | 1096 | |
89184651 | 1097 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 1098 | |
89184651 TR |
1099 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
1100 | if (!smmu->asids) | |
1101 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 1102 | |
7f4c9176 | 1103 | INIT_LIST_HEAD(&smmu->groups); |
89184651 | 1104 | mutex_init(&smmu->lock); |
7a31f6f4 | 1105 | |
89184651 TR |
1106 | smmu->regs = mc->regs; |
1107 | smmu->soc = soc; | |
1108 | smmu->dev = dev; | |
1109 | smmu->mc = mc; | |
7a31f6f4 | 1110 | |
804cb54c TR |
1111 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
1112 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
1113 | mc->soc->num_address_bits, smmu->pfn_mask); | |
11cec15b TR |
1114 | smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; |
1115 | dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, | |
1116 | smmu->tlb_mask); | |
804cb54c | 1117 | |
89184651 | 1118 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 1119 | |
89184651 TR |
1120 | if (soc->supports_request_limit) |
1121 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 1122 | |
89184651 | 1123 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 1124 | |
89184651 | 1125 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
11cec15b | 1126 | SMMU_TLB_CONFIG_ACTIVE_LINES(smmu); |
7a31f6f4 | 1127 | |
89184651 TR |
1128 | if (soc->supports_round_robin_arbitration) |
1129 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 1130 | |
89184651 | 1131 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 1132 | |
b8fe0382 | 1133 | smmu_flush_ptc_all(smmu); |
89184651 TR |
1134 | smmu_flush_tlb(smmu); |
1135 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
1136 | smmu_flush(smmu); | |
1137 | ||
1138 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 1139 | |
0b480e44 JR |
1140 | err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev)); |
1141 | if (err) | |
1142 | return ERR_PTR(err); | |
1143 | ||
1144 | iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops); | |
7f4c9176 | 1145 | iommu_device_set_fwnode(&smmu->iommu, dev->fwnode); |
0b480e44 JR |
1146 | |
1147 | err = iommu_device_register(&smmu->iommu); | |
1148 | if (err) { | |
1149 | iommu_device_sysfs_remove(&smmu->iommu); | |
1150 | return ERR_PTR(err); | |
1151 | } | |
1152 | ||
96302d89 JR |
1153 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
1154 | if (err < 0) { | |
1155 | iommu_device_unregister(&smmu->iommu); | |
1156 | iommu_device_sysfs_remove(&smmu->iommu); | |
1157 | return ERR_PTR(err); | |
1158 | } | |
1159 | ||
d1313e78 TR |
1160 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1161 | tegra_smmu_debugfs_init(smmu); | |
1162 | ||
89184651 TR |
1163 | return smmu; |
1164 | } | |
d1313e78 TR |
1165 | |
1166 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
1167 | { | |
0b480e44 JR |
1168 | iommu_device_unregister(&smmu->iommu); |
1169 | iommu_device_sysfs_remove(&smmu->iommu); | |
1170 | ||
d1313e78 TR |
1171 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1172 | tegra_smmu_debugfs_exit(smmu); | |
1173 | } |