Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
d1313e78 | 10 | #include <linux/debugfs.h> |
bc5e6dea | 11 | #include <linux/err.h> |
7a31f6f4 | 12 | #include <linux/iommu.h> |
89184651 | 13 | #include <linux/kernel.h> |
0760e8fa | 14 | #include <linux/of.h> |
89184651 TR |
15 | #include <linux/of_device.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
89184651 TR |
22 | struct tegra_smmu { |
23 | void __iomem *regs; | |
24 | struct device *dev; | |
e6bc5933 | 25 | |
89184651 TR |
26 | struct tegra_mc *mc; |
27 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 28 | |
804cb54c TR |
29 | unsigned long pfn_mask; |
30 | ||
89184651 TR |
31 | unsigned long *asids; |
32 | struct mutex lock; | |
39abf8aa | 33 | |
89184651 | 34 | struct list_head list; |
d1313e78 TR |
35 | |
36 | struct dentry *debugfs; | |
7a31f6f4 | 37 | }; |
7a31f6f4 | 38 | |
89184651 | 39 | struct tegra_smmu_as { |
d5f1a81c | 40 | struct iommu_domain domain; |
89184651 TR |
41 | struct tegra_smmu *smmu; |
42 | unsigned int use_count; | |
43 | struct page *count; | |
44 | struct page *pd; | |
45 | unsigned id; | |
46 | u32 attr; | |
7a31f6f4 HD |
47 | }; |
48 | ||
d5f1a81c JR |
49 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
50 | { | |
51 | return container_of(dom, struct tegra_smmu_as, domain); | |
52 | } | |
53 | ||
89184651 TR |
54 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
55 | unsigned long offset) | |
56 | { | |
57 | writel(value, smmu->regs + offset); | |
58 | } | |
7a31f6f4 | 59 | |
89184651 TR |
60 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
61 | { | |
62 | return readl(smmu->regs + offset); | |
63 | } | |
5a2c937a | 64 | |
89184651 TR |
65 | #define SMMU_CONFIG 0x010 |
66 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 67 | |
89184651 TR |
68 | #define SMMU_TLB_CONFIG 0x14 |
69 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
70 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
71 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) | |
0760e8fa | 72 | |
89184651 TR |
73 | #define SMMU_PTC_CONFIG 0x18 |
74 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
75 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
76 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 77 | |
89184651 TR |
78 | #define SMMU_PTB_ASID 0x01c |
79 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 80 | |
89184651 TR |
81 | #define SMMU_PTB_DATA 0x020 |
82 | #define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr)) | |
7a31f6f4 | 83 | |
89184651 | 84 | #define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 85 | |
89184651 TR |
86 | #define SMMU_TLB_FLUSH 0x030 |
87 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
88 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
89 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
90 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
91 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
92 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
93 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
94 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
95 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 96 | |
89184651 TR |
97 | #define SMMU_PTC_FLUSH 0x034 |
98 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
99 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 100 | |
89184651 TR |
101 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
102 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 103 | |
89184651 TR |
104 | /* per-SWGROUP SMMU_*_ASID register */ |
105 | #define SMMU_ASID_ENABLE (1 << 31) | |
106 | #define SMMU_ASID_MASK 0x7f | |
107 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 108 | |
89184651 TR |
109 | /* page table definitions */ |
110 | #define SMMU_NUM_PDE 1024 | |
111 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 112 | |
89184651 TR |
113 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
114 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 115 | |
89184651 TR |
116 | #define SMMU_PDE_SHIFT 22 |
117 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 118 | |
89184651 TR |
119 | #define SMMU_PD_READABLE (1 << 31) |
120 | #define SMMU_PD_WRITABLE (1 << 30) | |
121 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 122 | |
89184651 TR |
123 | #define SMMU_PDE_READABLE (1 << 31) |
124 | #define SMMU_PDE_WRITABLE (1 << 30) | |
125 | #define SMMU_PDE_NONSECURE (1 << 29) | |
126 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 127 | |
89184651 TR |
128 | #define SMMU_PTE_READABLE (1 << 31) |
129 | #define SMMU_PTE_WRITABLE (1 << 30) | |
130 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 131 | |
89184651 TR |
132 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
133 | SMMU_PDE_NONSECURE) | |
134 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
135 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 136 | |
34d35f8c RK |
137 | static unsigned int iova_pd_index(unsigned long iova) |
138 | { | |
139 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
140 | } | |
141 | ||
142 | static unsigned int iova_pt_index(unsigned long iova) | |
143 | { | |
144 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
145 | } | |
146 | ||
89184651 TR |
147 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, |
148 | unsigned long offset) | |
7a31f6f4 | 149 | { |
89184651 TR |
150 | phys_addr_t phys = page ? page_to_phys(page) : 0; |
151 | u32 value; | |
152 | ||
153 | if (page) { | |
154 | offset &= ~(smmu->mc->soc->atom_size - 1); | |
155 | ||
156 | if (smmu->mc->soc->num_address_bits > 32) { | |
157 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
158 | value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
159 | #else | |
160 | value = 0; | |
161 | #endif | |
162 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); | |
7a31f6f4 | 163 | } |
7a31f6f4 | 164 | |
89184651 TR |
165 | value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
166 | } else { | |
167 | value = SMMU_PTC_FLUSH_TYPE_ALL; | |
7a31f6f4 | 168 | } |
89184651 TR |
169 | |
170 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); | |
7a31f6f4 HD |
171 | } |
172 | ||
89184651 | 173 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 174 | { |
89184651 | 175 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
176 | } |
177 | ||
89184651 TR |
178 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
179 | unsigned long asid) | |
7a31f6f4 | 180 | { |
89184651 | 181 | u32 value; |
7a31f6f4 | 182 | |
89184651 TR |
183 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
184 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
185 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
186 | } |
187 | ||
89184651 TR |
188 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
189 | unsigned long asid, | |
190 | unsigned long iova) | |
7a31f6f4 | 191 | { |
89184651 | 192 | u32 value; |
7a31f6f4 | 193 | |
89184651 TR |
194 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
195 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
196 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
197 | } |
198 | ||
89184651 TR |
199 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
200 | unsigned long asid, | |
201 | unsigned long iova) | |
7a31f6f4 | 202 | { |
89184651 | 203 | u32 value; |
7a31f6f4 | 204 | |
89184651 TR |
205 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
206 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
207 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
208 | } |
209 | ||
89184651 | 210 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 211 | { |
89184651 | 212 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
213 | } |
214 | ||
89184651 | 215 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 216 | { |
89184651 | 217 | unsigned long id; |
7a31f6f4 | 218 | |
89184651 | 219 | mutex_lock(&smmu->lock); |
7a31f6f4 | 220 | |
89184651 TR |
221 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
222 | if (id >= smmu->soc->num_asids) { | |
223 | mutex_unlock(&smmu->lock); | |
224 | return -ENOSPC; | |
7a31f6f4 | 225 | } |
7a31f6f4 | 226 | |
89184651 TR |
227 | set_bit(id, smmu->asids); |
228 | *idp = id; | |
229 | ||
230 | mutex_unlock(&smmu->lock); | |
231 | return 0; | |
7a31f6f4 HD |
232 | } |
233 | ||
89184651 | 234 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 235 | { |
89184651 TR |
236 | mutex_lock(&smmu->lock); |
237 | clear_bit(id, smmu->asids); | |
238 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 239 | } |
89184651 TR |
240 | |
241 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 242 | { |
89184651 | 243 | return false; |
7a31f6f4 | 244 | } |
7a31f6f4 | 245 | |
d5f1a81c | 246 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 247 | { |
89184651 TR |
248 | struct tegra_smmu_as *as; |
249 | unsigned int i; | |
250 | uint32_t *pd; | |
7a31f6f4 | 251 | |
d5f1a81c JR |
252 | if (type != IOMMU_DOMAIN_UNMANAGED) |
253 | return NULL; | |
254 | ||
89184651 TR |
255 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
256 | if (!as) | |
d5f1a81c | 257 | return NULL; |
7a31f6f4 | 258 | |
89184651 | 259 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 260 | |
89184651 TR |
261 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
262 | if (!as->pd) { | |
263 | kfree(as); | |
d5f1a81c | 264 | return NULL; |
7a31f6f4 | 265 | } |
9e971a03 | 266 | |
89184651 TR |
267 | as->count = alloc_page(GFP_KERNEL); |
268 | if (!as->count) { | |
269 | __free_page(as->pd); | |
270 | kfree(as); | |
d5f1a81c | 271 | return NULL; |
7a31f6f4 | 272 | } |
9e971a03 | 273 | |
89184651 TR |
274 | /* clear PDEs */ |
275 | pd = page_address(as->pd); | |
276 | SetPageReserved(as->pd); | |
9e971a03 | 277 | |
89184651 TR |
278 | for (i = 0; i < SMMU_NUM_PDE; i++) |
279 | pd[i] = 0; | |
7a31f6f4 | 280 | |
89184651 TR |
281 | /* clear PDE usage counters */ |
282 | pd = page_address(as->count); | |
283 | SetPageReserved(as->count); | |
7a31f6f4 | 284 | |
89184651 TR |
285 | for (i = 0; i < SMMU_NUM_PDE; i++) |
286 | pd[i] = 0; | |
9e971a03 | 287 | |
471d9144 | 288 | /* setup aperture */ |
7f65ef01 JR |
289 | as->domain.geometry.aperture_start = 0; |
290 | as->domain.geometry.aperture_end = 0xffffffff; | |
291 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 292 | |
d5f1a81c | 293 | return &as->domain; |
7a31f6f4 HD |
294 | } |
295 | ||
d5f1a81c | 296 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 297 | { |
d5f1a81c | 298 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 299 | |
89184651 TR |
300 | /* TODO: free page directory and page tables */ |
301 | ClearPageReserved(as->pd); | |
7a31f6f4 | 302 | |
89184651 | 303 | kfree(as); |
7a31f6f4 HD |
304 | } |
305 | ||
89184651 TR |
306 | static const struct tegra_smmu_swgroup * |
307 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 308 | { |
89184651 TR |
309 | const struct tegra_smmu_swgroup *group = NULL; |
310 | unsigned int i; | |
7a31f6f4 | 311 | |
89184651 TR |
312 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
313 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
314 | group = &smmu->soc->swgroups[i]; | |
315 | break; | |
316 | } | |
317 | } | |
7a31f6f4 | 318 | |
89184651 | 319 | return group; |
7a31f6f4 HD |
320 | } |
321 | ||
89184651 TR |
322 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
323 | unsigned int asid) | |
7a31f6f4 | 324 | { |
89184651 TR |
325 | const struct tegra_smmu_swgroup *group; |
326 | unsigned int i; | |
327 | u32 value; | |
7a31f6f4 | 328 | |
89184651 TR |
329 | for (i = 0; i < smmu->soc->num_clients; i++) { |
330 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 331 | |
89184651 TR |
332 | if (client->swgroup != swgroup) |
333 | continue; | |
7a31f6f4 | 334 | |
89184651 TR |
335 | value = smmu_readl(smmu, client->smmu.reg); |
336 | value |= BIT(client->smmu.bit); | |
337 | smmu_writel(smmu, value, client->smmu.reg); | |
338 | } | |
7a31f6f4 | 339 | |
89184651 TR |
340 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
341 | if (group) { | |
342 | value = smmu_readl(smmu, group->reg); | |
343 | value &= ~SMMU_ASID_MASK; | |
344 | value |= SMMU_ASID_VALUE(asid); | |
345 | value |= SMMU_ASID_ENABLE; | |
346 | smmu_writel(smmu, value, group->reg); | |
347 | } | |
7a31f6f4 HD |
348 | } |
349 | ||
89184651 TR |
350 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
351 | unsigned int asid) | |
7a31f6f4 | 352 | { |
89184651 TR |
353 | const struct tegra_smmu_swgroup *group; |
354 | unsigned int i; | |
355 | u32 value; | |
7a31f6f4 | 356 | |
89184651 TR |
357 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
358 | if (group) { | |
359 | value = smmu_readl(smmu, group->reg); | |
360 | value &= ~SMMU_ASID_MASK; | |
361 | value |= SMMU_ASID_VALUE(asid); | |
362 | value &= ~SMMU_ASID_ENABLE; | |
363 | smmu_writel(smmu, value, group->reg); | |
364 | } | |
7a31f6f4 | 365 | |
89184651 TR |
366 | for (i = 0; i < smmu->soc->num_clients; i++) { |
367 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 368 | |
89184651 TR |
369 | if (client->swgroup != swgroup) |
370 | continue; | |
7a31f6f4 | 371 | |
89184651 TR |
372 | value = smmu_readl(smmu, client->smmu.reg); |
373 | value &= ~BIT(client->smmu.bit); | |
374 | smmu_writel(smmu, value, client->smmu.reg); | |
375 | } | |
7a31f6f4 HD |
376 | } |
377 | ||
89184651 TR |
378 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
379 | struct tegra_smmu_as *as) | |
7a31f6f4 | 380 | { |
89184651 | 381 | u32 value; |
7a31f6f4 HD |
382 | int err; |
383 | ||
89184651 TR |
384 | if (as->use_count > 0) { |
385 | as->use_count++; | |
386 | return 0; | |
7a31f6f4 | 387 | } |
7a31f6f4 | 388 | |
89184651 TR |
389 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
390 | if (err < 0) | |
391 | return err; | |
7a31f6f4 | 392 | |
89184651 TR |
393 | smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD); |
394 | smmu_flush_ptc(smmu, as->pd, 0); | |
395 | smmu_flush_tlb_asid(smmu, as->id); | |
7a31f6f4 | 396 | |
89184651 TR |
397 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
398 | value = SMMU_PTB_DATA_VALUE(as->pd, as->attr); | |
399 | smmu_writel(smmu, value, SMMU_PTB_DATA); | |
400 | smmu_flush(smmu); | |
7a31f6f4 | 401 | |
89184651 TR |
402 | as->smmu = smmu; |
403 | as->use_count++; | |
7a31f6f4 | 404 | |
89184651 | 405 | return 0; |
7a31f6f4 HD |
406 | } |
407 | ||
89184651 TR |
408 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
409 | struct tegra_smmu_as *as) | |
7a31f6f4 | 410 | { |
89184651 TR |
411 | if (--as->use_count > 0) |
412 | return; | |
413 | ||
414 | tegra_smmu_free_asid(smmu, as->id); | |
415 | as->smmu = NULL; | |
7a31f6f4 HD |
416 | } |
417 | ||
89184651 TR |
418 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
419 | struct device *dev) | |
7a31f6f4 | 420 | { |
89184651 | 421 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 422 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
423 | struct device_node *np = dev->of_node; |
424 | struct of_phandle_args args; | |
425 | unsigned int index = 0; | |
426 | int err = 0; | |
7a31f6f4 | 427 | |
89184651 TR |
428 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
429 | &args)) { | |
430 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 431 | |
89184651 TR |
432 | if (args.np != smmu->dev->of_node) { |
433 | of_node_put(args.np); | |
d2453b2c | 434 | continue; |
89184651 | 435 | } |
d2453b2c | 436 | |
89184651 | 437 | of_node_put(args.np); |
d2453b2c | 438 | |
89184651 TR |
439 | err = tegra_smmu_as_prepare(smmu, as); |
440 | if (err < 0) | |
441 | return err; | |
442 | ||
443 | tegra_smmu_enable(smmu, swgroup, as->id); | |
444 | index++; | |
7a31f6f4 | 445 | } |
7a31f6f4 | 446 | |
89184651 TR |
447 | if (index == 0) |
448 | return -ENODEV; | |
7a31f6f4 | 449 | |
89184651 TR |
450 | return 0; |
451 | } | |
7a31f6f4 | 452 | |
89184651 TR |
453 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
454 | { | |
d5f1a81c | 455 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
456 | struct device_node *np = dev->of_node; |
457 | struct tegra_smmu *smmu = as->smmu; | |
458 | struct of_phandle_args args; | |
459 | unsigned int index = 0; | |
7a31f6f4 | 460 | |
89184651 TR |
461 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
462 | &args)) { | |
463 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 464 | |
89184651 TR |
465 | if (args.np != smmu->dev->of_node) { |
466 | of_node_put(args.np); | |
467 | continue; | |
468 | } | |
23349902 | 469 | |
89184651 | 470 | of_node_put(args.np); |
7a31f6f4 | 471 | |
89184651 TR |
472 | tegra_smmu_disable(smmu, swgroup, as->id); |
473 | tegra_smmu_as_unprepare(smmu, as); | |
474 | index++; | |
475 | } | |
7a31f6f4 HD |
476 | } |
477 | ||
89184651 TR |
478 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
479 | struct page **pagep) | |
7a31f6f4 | 480 | { |
89184651 | 481 | u32 *pd = page_address(as->pd), *pt, *count; |
34d35f8c RK |
482 | unsigned int pde = iova_pd_index(iova); |
483 | unsigned int pte = iova_pt_index(iova); | |
89184651 TR |
484 | struct tegra_smmu *smmu = as->smmu; |
485 | struct page *page; | |
486 | unsigned int i; | |
487 | ||
488 | if (pd[pde] == 0) { | |
489 | page = alloc_page(GFP_KERNEL | __GFP_DMA); | |
490 | if (!page) | |
491 | return NULL; | |
7a31f6f4 | 492 | |
89184651 TR |
493 | pt = page_address(page); |
494 | SetPageReserved(page); | |
7a31f6f4 | 495 | |
89184651 TR |
496 | for (i = 0; i < SMMU_NUM_PTE; i++) |
497 | pt[i] = 0; | |
7a31f6f4 | 498 | |
89184651 | 499 | smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT); |
7a31f6f4 | 500 | |
89184651 | 501 | pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
7a31f6f4 | 502 | |
89184651 TR |
503 | smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4); |
504 | smmu_flush_ptc(smmu, as->pd, pde << 2); | |
505 | smmu_flush_tlb_section(smmu, as->id, iova); | |
506 | smmu_flush(smmu); | |
507 | } else { | |
804cb54c | 508 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
89184651 | 509 | pt = page_address(page); |
7a31f6f4 HD |
510 | } |
511 | ||
89184651 | 512 | *pagep = page; |
7a31f6f4 | 513 | |
89184651 TR |
514 | /* Keep track of entries in this page table. */ |
515 | count = page_address(as->count); | |
516 | if (pt[pte] == 0) | |
517 | count[pde]++; | |
7a31f6f4 | 518 | |
89184651 TR |
519 | return &pt[pte]; |
520 | } | |
39abf8aa | 521 | |
b98e34f0 | 522 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 523 | { |
b98e34f0 | 524 | struct tegra_smmu *smmu = as->smmu; |
34d35f8c | 525 | unsigned int pde = iova_pd_index(iova); |
89184651 | 526 | u32 *count = page_address(as->count); |
b98e34f0 | 527 | u32 *pd = page_address(as->pd); |
89184651 | 528 | struct page *page; |
39abf8aa | 529 | |
b98e34f0 | 530 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
39abf8aa | 531 | |
89184651 TR |
532 | /* |
533 | * When no entries in this page table are used anymore, return the | |
534 | * memory page to the system. | |
535 | */ | |
b98e34f0 RK |
536 | if (--count[pde] == 0) { |
537 | unsigned int offset = pde * sizeof(*pd); | |
39abf8aa | 538 | |
b98e34f0 RK |
539 | /* Clear the page directory entry first */ |
540 | pd[pde] = 0; | |
541 | ||
542 | /* Flush the page directory entry */ | |
543 | smmu->soc->ops->flush_dcache(as->pd, offset, sizeof(*pd)); | |
544 | smmu_flush_ptc(smmu, as->pd, offset); | |
545 | smmu_flush_tlb_section(smmu, as->id, iova); | |
546 | smmu_flush(smmu); | |
547 | ||
548 | /* Finally, free the page */ | |
549 | ClearPageReserved(page); | |
550 | __free_page(page); | |
39abf8aa | 551 | } |
39abf8aa HD |
552 | } |
553 | ||
8482ee5e RK |
554 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
555 | u32 *pte, struct page *pte_page, u32 val) | |
556 | { | |
557 | struct tegra_smmu *smmu = as->smmu; | |
558 | unsigned long offset = offset_in_page(pte); | |
559 | ||
560 | *pte = val; | |
561 | ||
562 | smmu->soc->ops->flush_dcache(pte_page, offset, 4); | |
563 | smmu_flush_ptc(smmu, pte_page, offset); | |
564 | smmu_flush_tlb_group(smmu, as->id, iova); | |
565 | smmu_flush(smmu); | |
566 | } | |
567 | ||
89184651 TR |
568 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
569 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 570 | { |
d5f1a81c | 571 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
572 | struct page *page; |
573 | u32 *pte; | |
39abf8aa | 574 | |
89184651 TR |
575 | pte = as_get_pte(as, iova, &page); |
576 | if (!pte) | |
577 | return -ENOMEM; | |
39abf8aa | 578 | |
8482ee5e RK |
579 | tegra_smmu_set_pte(as, iova, pte, page, |
580 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); | |
39abf8aa | 581 | |
39abf8aa HD |
582 | return 0; |
583 | } | |
584 | ||
89184651 TR |
585 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
586 | size_t size) | |
39abf8aa | 587 | { |
d5f1a81c | 588 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
589 | struct page *page; |
590 | u32 *pte; | |
39abf8aa | 591 | |
89184651 | 592 | pte = as_get_pte(as, iova, &page); |
b98e34f0 | 593 | if (!pte || !*pte) |
89184651 | 594 | return 0; |
39abf8aa | 595 | |
8482ee5e | 596 | tegra_smmu_set_pte(as, iova, pte, page, 0); |
b98e34f0 RK |
597 | tegra_smmu_pte_put_use(as, iova); |
598 | ||
89184651 | 599 | return size; |
39abf8aa HD |
600 | } |
601 | ||
89184651 TR |
602 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
603 | dma_addr_t iova) | |
39abf8aa | 604 | { |
d5f1a81c | 605 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
606 | struct page *page; |
607 | unsigned long pfn; | |
608 | u32 *pte; | |
39abf8aa | 609 | |
89184651 | 610 | pte = as_get_pte(as, iova, &page); |
9113785c RK |
611 | if (!pte || !*pte) |
612 | return 0; | |
613 | ||
804cb54c | 614 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 615 | |
89184651 | 616 | return PFN_PHYS(pfn); |
39abf8aa HD |
617 | } |
618 | ||
89184651 | 619 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 620 | { |
89184651 TR |
621 | struct platform_device *pdev; |
622 | struct tegra_mc *mc; | |
7a31f6f4 | 623 | |
89184651 TR |
624 | pdev = of_find_device_by_node(np); |
625 | if (!pdev) | |
626 | return NULL; | |
627 | ||
628 | mc = platform_get_drvdata(pdev); | |
629 | if (!mc) | |
630 | return NULL; | |
631 | ||
632 | return mc->smmu; | |
7a31f6f4 HD |
633 | } |
634 | ||
89184651 | 635 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 636 | { |
89184651 TR |
637 | struct device_node *np = dev->of_node; |
638 | struct of_phandle_args args; | |
639 | unsigned int index = 0; | |
7a31f6f4 | 640 | |
89184651 TR |
641 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
642 | &args) == 0) { | |
643 | struct tegra_smmu *smmu; | |
644 | ||
645 | smmu = tegra_smmu_find(args.np); | |
646 | if (smmu) { | |
647 | /* | |
648 | * Only a single IOMMU master interface is currently | |
649 | * supported by the Linux kernel, so abort after the | |
650 | * first match. | |
651 | */ | |
652 | dev->archdata.iommu = smmu; | |
653 | break; | |
654 | } | |
655 | ||
656 | index++; | |
657 | } | |
658 | ||
659 | return 0; | |
7a31f6f4 HD |
660 | } |
661 | ||
89184651 | 662 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 663 | { |
89184651 TR |
664 | dev->archdata.iommu = NULL; |
665 | } | |
7a31f6f4 | 666 | |
89184651 TR |
667 | static const struct iommu_ops tegra_smmu_ops = { |
668 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
669 | .domain_alloc = tegra_smmu_domain_alloc, |
670 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
671 | .attach_dev = tegra_smmu_attach_dev, |
672 | .detach_dev = tegra_smmu_detach_dev, | |
673 | .add_device = tegra_smmu_add_device, | |
674 | .remove_device = tegra_smmu_remove_device, | |
675 | .map = tegra_smmu_map, | |
676 | .unmap = tegra_smmu_unmap, | |
677 | .map_sg = default_iommu_map_sg, | |
678 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 679 | |
89184651 TR |
680 | .pgsize_bitmap = SZ_4K, |
681 | }; | |
7a31f6f4 | 682 | |
89184651 TR |
683 | static void tegra_smmu_ahb_enable(void) |
684 | { | |
685 | static const struct of_device_id ahb_match[] = { | |
686 | { .compatible = "nvidia,tegra30-ahb", }, | |
687 | { } | |
688 | }; | |
689 | struct device_node *ahb; | |
7a31f6f4 | 690 | |
89184651 TR |
691 | ahb = of_find_matching_node(NULL, ahb_match); |
692 | if (ahb) { | |
693 | tegra_ahb_enable_smmu(ahb); | |
694 | of_node_put(ahb); | |
7a31f6f4 | 695 | } |
89184651 | 696 | } |
7a31f6f4 | 697 | |
d1313e78 TR |
698 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
699 | { | |
700 | struct tegra_smmu *smmu = s->private; | |
701 | unsigned int i; | |
702 | u32 value; | |
703 | ||
704 | seq_printf(s, "swgroup enabled ASID\n"); | |
705 | seq_printf(s, "------------------------\n"); | |
706 | ||
707 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
708 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
709 | const char *status; | |
710 | unsigned int asid; | |
711 | ||
712 | value = smmu_readl(smmu, group->reg); | |
713 | ||
714 | if (value & SMMU_ASID_ENABLE) | |
715 | status = "yes"; | |
716 | else | |
717 | status = "no"; | |
718 | ||
719 | asid = value & SMMU_ASID_MASK; | |
720 | ||
721 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
722 | asid); | |
723 | } | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) | |
729 | { | |
730 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); | |
731 | } | |
732 | ||
733 | static const struct file_operations tegra_smmu_swgroups_fops = { | |
734 | .open = tegra_smmu_swgroups_open, | |
735 | .read = seq_read, | |
736 | .llseek = seq_lseek, | |
737 | .release = single_release, | |
738 | }; | |
739 | ||
740 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
741 | { | |
742 | struct tegra_smmu *smmu = s->private; | |
743 | unsigned int i; | |
744 | u32 value; | |
745 | ||
746 | seq_printf(s, "client enabled\n"); | |
747 | seq_printf(s, "--------------------\n"); | |
748 | ||
749 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
750 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
751 | const char *status; | |
752 | ||
753 | value = smmu_readl(smmu, client->smmu.reg); | |
754 | ||
755 | if (value & BIT(client->smmu.bit)) | |
756 | status = "yes"; | |
757 | else | |
758 | status = "no"; | |
759 | ||
760 | seq_printf(s, "%-12s %s\n", client->name, status); | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) | |
767 | { | |
768 | return single_open(file, tegra_smmu_clients_show, inode->i_private); | |
769 | } | |
770 | ||
771 | static const struct file_operations tegra_smmu_clients_fops = { | |
772 | .open = tegra_smmu_clients_open, | |
773 | .read = seq_read, | |
774 | .llseek = seq_lseek, | |
775 | .release = single_release, | |
776 | }; | |
777 | ||
778 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
779 | { | |
780 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
781 | if (!smmu->debugfs) | |
782 | return; | |
783 | ||
784 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
785 | &tegra_smmu_swgroups_fops); | |
786 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
787 | &tegra_smmu_clients_fops); | |
788 | } | |
789 | ||
790 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
791 | { | |
792 | debugfs_remove_recursive(smmu->debugfs); | |
793 | } | |
794 | ||
89184651 TR |
795 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
796 | const struct tegra_smmu_soc *soc, | |
797 | struct tegra_mc *mc) | |
798 | { | |
799 | struct tegra_smmu *smmu; | |
800 | size_t size; | |
801 | u32 value; | |
802 | int err; | |
7a31f6f4 | 803 | |
89184651 TR |
804 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
805 | if (!soc) | |
806 | return NULL; | |
0760e8fa | 807 | |
89184651 TR |
808 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
809 | if (!smmu) | |
810 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 811 | |
89184651 TR |
812 | /* |
813 | * This is a bit of a hack. Ideally we'd want to simply return this | |
814 | * value. However the IOMMU registration process will attempt to add | |
815 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
816 | * not to rely on global variables to track the IOMMU instance, we | |
817 | * set it here so that it can be looked up from the .add_device() | |
818 | * callback via the IOMMU device's .drvdata field. | |
819 | */ | |
820 | mc->smmu = smmu; | |
0760e8fa | 821 | |
89184651 | 822 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 823 | |
89184651 TR |
824 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
825 | if (!smmu->asids) | |
826 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 827 | |
89184651 | 828 | mutex_init(&smmu->lock); |
7a31f6f4 | 829 | |
89184651 TR |
830 | smmu->regs = mc->regs; |
831 | smmu->soc = soc; | |
832 | smmu->dev = dev; | |
833 | smmu->mc = mc; | |
7a31f6f4 | 834 | |
804cb54c TR |
835 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
836 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
837 | mc->soc->num_address_bits, smmu->pfn_mask); | |
838 | ||
89184651 | 839 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 840 | |
89184651 TR |
841 | if (soc->supports_request_limit) |
842 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 843 | |
89184651 | 844 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 845 | |
89184651 TR |
846 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
847 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); | |
7a31f6f4 | 848 | |
89184651 TR |
849 | if (soc->supports_round_robin_arbitration) |
850 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 851 | |
89184651 | 852 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 853 | |
89184651 TR |
854 | smmu_flush_ptc(smmu, NULL, 0); |
855 | smmu_flush_tlb(smmu); | |
856 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
857 | smmu_flush(smmu); | |
858 | ||
859 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 860 | |
89184651 TR |
861 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
862 | if (err < 0) | |
863 | return ERR_PTR(err); | |
7a31f6f4 | 864 | |
d1313e78 TR |
865 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
866 | tegra_smmu_debugfs_init(smmu); | |
867 | ||
89184651 TR |
868 | return smmu; |
869 | } | |
d1313e78 TR |
870 | |
871 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
872 | { | |
873 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
874 | tegra_smmu_debugfs_exit(smmu); | |
875 | } |