Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
d1313e78 | 10 | #include <linux/debugfs.h> |
bc5e6dea | 11 | #include <linux/err.h> |
7a31f6f4 | 12 | #include <linux/iommu.h> |
89184651 | 13 | #include <linux/kernel.h> |
0760e8fa | 14 | #include <linux/of.h> |
89184651 TR |
15 | #include <linux/of_device.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
89184651 TR |
22 | struct tegra_smmu { |
23 | void __iomem *regs; | |
24 | struct device *dev; | |
e6bc5933 | 25 | |
89184651 TR |
26 | struct tegra_mc *mc; |
27 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 28 | |
804cb54c TR |
29 | unsigned long pfn_mask; |
30 | ||
89184651 TR |
31 | unsigned long *asids; |
32 | struct mutex lock; | |
39abf8aa | 33 | |
89184651 | 34 | struct list_head list; |
d1313e78 TR |
35 | |
36 | struct dentry *debugfs; | |
7a31f6f4 | 37 | }; |
7a31f6f4 | 38 | |
89184651 | 39 | struct tegra_smmu_as { |
d5f1a81c | 40 | struct iommu_domain domain; |
89184651 TR |
41 | struct tegra_smmu *smmu; |
42 | unsigned int use_count; | |
32924c76 | 43 | u32 *count; |
853520fa | 44 | struct page **pts; |
89184651 | 45 | struct page *pd; |
e3c97196 | 46 | dma_addr_t pd_dma; |
89184651 TR |
47 | unsigned id; |
48 | u32 attr; | |
7a31f6f4 HD |
49 | }; |
50 | ||
d5f1a81c JR |
51 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
52 | { | |
53 | return container_of(dom, struct tegra_smmu_as, domain); | |
54 | } | |
55 | ||
89184651 TR |
56 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
57 | unsigned long offset) | |
58 | { | |
59 | writel(value, smmu->regs + offset); | |
60 | } | |
7a31f6f4 | 61 | |
89184651 TR |
62 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
63 | { | |
64 | return readl(smmu->regs + offset); | |
65 | } | |
5a2c937a | 66 | |
89184651 TR |
67 | #define SMMU_CONFIG 0x010 |
68 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 69 | |
89184651 TR |
70 | #define SMMU_TLB_CONFIG 0x14 |
71 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
72 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
73 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) | |
0760e8fa | 74 | |
89184651 TR |
75 | #define SMMU_PTC_CONFIG 0x18 |
76 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
77 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
78 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 79 | |
89184651 TR |
80 | #define SMMU_PTB_ASID 0x01c |
81 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 82 | |
89184651 | 83 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 84 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 85 | |
e3c97196 | 86 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 87 | |
89184651 TR |
88 | #define SMMU_TLB_FLUSH 0x030 |
89 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
90 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
91 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
92 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
93 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
94 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
95 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
96 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
97 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 98 | |
89184651 TR |
99 | #define SMMU_PTC_FLUSH 0x034 |
100 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
101 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 102 | |
89184651 TR |
103 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
104 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 105 | |
89184651 TR |
106 | /* per-SWGROUP SMMU_*_ASID register */ |
107 | #define SMMU_ASID_ENABLE (1 << 31) | |
108 | #define SMMU_ASID_MASK 0x7f | |
109 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 110 | |
89184651 TR |
111 | /* page table definitions */ |
112 | #define SMMU_NUM_PDE 1024 | |
113 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 114 | |
89184651 TR |
115 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
116 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 117 | |
89184651 TR |
118 | #define SMMU_PDE_SHIFT 22 |
119 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 120 | |
89184651 TR |
121 | #define SMMU_PD_READABLE (1 << 31) |
122 | #define SMMU_PD_WRITABLE (1 << 30) | |
123 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 124 | |
89184651 TR |
125 | #define SMMU_PDE_READABLE (1 << 31) |
126 | #define SMMU_PDE_WRITABLE (1 << 30) | |
127 | #define SMMU_PDE_NONSECURE (1 << 29) | |
128 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 129 | |
89184651 TR |
130 | #define SMMU_PTE_READABLE (1 << 31) |
131 | #define SMMU_PTE_WRITABLE (1 << 30) | |
132 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 133 | |
89184651 TR |
134 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
135 | SMMU_PDE_NONSECURE) | |
136 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
137 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 138 | |
34d35f8c RK |
139 | static unsigned int iova_pd_index(unsigned long iova) |
140 | { | |
141 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
142 | } | |
143 | ||
144 | static unsigned int iova_pt_index(unsigned long iova) | |
145 | { | |
146 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
147 | } | |
148 | ||
e3c97196 | 149 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 150 | { |
e3c97196 RK |
151 | addr >>= 12; |
152 | return (addr & smmu->pfn_mask) == addr; | |
153 | } | |
4b3c7d10 | 154 | |
e3c97196 RK |
155 | static dma_addr_t smmu_pde_to_dma(u32 pde) |
156 | { | |
157 | return pde << 12; | |
4b3c7d10 RK |
158 | } |
159 | ||
b8fe0382 RK |
160 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
161 | { | |
162 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
163 | } | |
164 | ||
e3c97196 | 165 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 166 | unsigned long offset) |
7a31f6f4 | 167 | { |
89184651 TR |
168 | u32 value; |
169 | ||
b8fe0382 | 170 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 171 | |
b8fe0382 | 172 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
173 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
174 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 175 | #else |
b8fe0382 | 176 | value = 0; |
89184651 | 177 | #endif |
b8fe0382 | 178 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 179 | } |
89184651 | 180 | |
e3c97196 | 181 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 182 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
183 | } |
184 | ||
89184651 | 185 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 186 | { |
89184651 | 187 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
188 | } |
189 | ||
89184651 TR |
190 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
191 | unsigned long asid) | |
7a31f6f4 | 192 | { |
89184651 | 193 | u32 value; |
7a31f6f4 | 194 | |
89184651 TR |
195 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
196 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
197 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
198 | } |
199 | ||
89184651 TR |
200 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
201 | unsigned long asid, | |
202 | unsigned long iova) | |
7a31f6f4 | 203 | { |
89184651 | 204 | u32 value; |
7a31f6f4 | 205 | |
89184651 TR |
206 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
207 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
208 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
209 | } |
210 | ||
89184651 TR |
211 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
212 | unsigned long asid, | |
213 | unsigned long iova) | |
7a31f6f4 | 214 | { |
89184651 | 215 | u32 value; |
7a31f6f4 | 216 | |
89184651 TR |
217 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
218 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
219 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
220 | } |
221 | ||
89184651 | 222 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 223 | { |
89184651 | 224 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
225 | } |
226 | ||
89184651 | 227 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 228 | { |
89184651 | 229 | unsigned long id; |
7a31f6f4 | 230 | |
89184651 | 231 | mutex_lock(&smmu->lock); |
7a31f6f4 | 232 | |
89184651 TR |
233 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
234 | if (id >= smmu->soc->num_asids) { | |
235 | mutex_unlock(&smmu->lock); | |
236 | return -ENOSPC; | |
7a31f6f4 | 237 | } |
7a31f6f4 | 238 | |
89184651 TR |
239 | set_bit(id, smmu->asids); |
240 | *idp = id; | |
241 | ||
242 | mutex_unlock(&smmu->lock); | |
243 | return 0; | |
7a31f6f4 HD |
244 | } |
245 | ||
89184651 | 246 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 247 | { |
89184651 TR |
248 | mutex_lock(&smmu->lock); |
249 | clear_bit(id, smmu->asids); | |
250 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 251 | } |
89184651 TR |
252 | |
253 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 254 | { |
89184651 | 255 | return false; |
7a31f6f4 | 256 | } |
7a31f6f4 | 257 | |
d5f1a81c | 258 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 259 | { |
89184651 TR |
260 | struct tegra_smmu_as *as; |
261 | unsigned int i; | |
262 | uint32_t *pd; | |
7a31f6f4 | 263 | |
d5f1a81c JR |
264 | if (type != IOMMU_DOMAIN_UNMANAGED) |
265 | return NULL; | |
266 | ||
89184651 TR |
267 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
268 | if (!as) | |
d5f1a81c | 269 | return NULL; |
7a31f6f4 | 270 | |
89184651 | 271 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 272 | |
89184651 TR |
273 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
274 | if (!as->pd) { | |
275 | kfree(as); | |
d5f1a81c | 276 | return NULL; |
7a31f6f4 | 277 | } |
9e971a03 | 278 | |
32924c76 | 279 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
280 | if (!as->count) { |
281 | __free_page(as->pd); | |
282 | kfree(as); | |
d5f1a81c | 283 | return NULL; |
7a31f6f4 | 284 | } |
9e971a03 | 285 | |
853520fa RK |
286 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
287 | if (!as->pts) { | |
32924c76 | 288 | kfree(as->count); |
853520fa RK |
289 | __free_page(as->pd); |
290 | kfree(as); | |
291 | return NULL; | |
292 | } | |
293 | ||
89184651 TR |
294 | /* clear PDEs */ |
295 | pd = page_address(as->pd); | |
9e971a03 | 296 | |
89184651 TR |
297 | for (i = 0; i < SMMU_NUM_PDE; i++) |
298 | pd[i] = 0; | |
9e971a03 | 299 | |
471d9144 | 300 | /* setup aperture */ |
7f65ef01 JR |
301 | as->domain.geometry.aperture_start = 0; |
302 | as->domain.geometry.aperture_end = 0xffffffff; | |
303 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 304 | |
d5f1a81c | 305 | return &as->domain; |
7a31f6f4 HD |
306 | } |
307 | ||
d5f1a81c | 308 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 309 | { |
d5f1a81c | 310 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 311 | |
89184651 | 312 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 313 | |
89184651 | 314 | kfree(as); |
7a31f6f4 HD |
315 | } |
316 | ||
89184651 TR |
317 | static const struct tegra_smmu_swgroup * |
318 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 319 | { |
89184651 TR |
320 | const struct tegra_smmu_swgroup *group = NULL; |
321 | unsigned int i; | |
7a31f6f4 | 322 | |
89184651 TR |
323 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
324 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
325 | group = &smmu->soc->swgroups[i]; | |
326 | break; | |
327 | } | |
328 | } | |
7a31f6f4 | 329 | |
89184651 | 330 | return group; |
7a31f6f4 HD |
331 | } |
332 | ||
89184651 TR |
333 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
334 | unsigned int asid) | |
7a31f6f4 | 335 | { |
89184651 TR |
336 | const struct tegra_smmu_swgroup *group; |
337 | unsigned int i; | |
338 | u32 value; | |
7a31f6f4 | 339 | |
89184651 TR |
340 | for (i = 0; i < smmu->soc->num_clients; i++) { |
341 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 342 | |
89184651 TR |
343 | if (client->swgroup != swgroup) |
344 | continue; | |
7a31f6f4 | 345 | |
89184651 TR |
346 | value = smmu_readl(smmu, client->smmu.reg); |
347 | value |= BIT(client->smmu.bit); | |
348 | smmu_writel(smmu, value, client->smmu.reg); | |
349 | } | |
7a31f6f4 | 350 | |
89184651 TR |
351 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
352 | if (group) { | |
353 | value = smmu_readl(smmu, group->reg); | |
354 | value &= ~SMMU_ASID_MASK; | |
355 | value |= SMMU_ASID_VALUE(asid); | |
356 | value |= SMMU_ASID_ENABLE; | |
357 | smmu_writel(smmu, value, group->reg); | |
358 | } | |
7a31f6f4 HD |
359 | } |
360 | ||
89184651 TR |
361 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
362 | unsigned int asid) | |
7a31f6f4 | 363 | { |
89184651 TR |
364 | const struct tegra_smmu_swgroup *group; |
365 | unsigned int i; | |
366 | u32 value; | |
7a31f6f4 | 367 | |
89184651 TR |
368 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
369 | if (group) { | |
370 | value = smmu_readl(smmu, group->reg); | |
371 | value &= ~SMMU_ASID_MASK; | |
372 | value |= SMMU_ASID_VALUE(asid); | |
373 | value &= ~SMMU_ASID_ENABLE; | |
374 | smmu_writel(smmu, value, group->reg); | |
375 | } | |
7a31f6f4 | 376 | |
89184651 TR |
377 | for (i = 0; i < smmu->soc->num_clients; i++) { |
378 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 379 | |
89184651 TR |
380 | if (client->swgroup != swgroup) |
381 | continue; | |
7a31f6f4 | 382 | |
89184651 TR |
383 | value = smmu_readl(smmu, client->smmu.reg); |
384 | value &= ~BIT(client->smmu.bit); | |
385 | smmu_writel(smmu, value, client->smmu.reg); | |
386 | } | |
7a31f6f4 HD |
387 | } |
388 | ||
89184651 TR |
389 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
390 | struct tegra_smmu_as *as) | |
7a31f6f4 | 391 | { |
89184651 | 392 | u32 value; |
7a31f6f4 HD |
393 | int err; |
394 | ||
89184651 TR |
395 | if (as->use_count > 0) { |
396 | as->use_count++; | |
397 | return 0; | |
7a31f6f4 | 398 | } |
7a31f6f4 | 399 | |
e3c97196 RK |
400 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
401 | DMA_TO_DEVICE); | |
402 | if (dma_mapping_error(smmu->dev, as->pd_dma)) | |
403 | return -ENOMEM; | |
404 | ||
405 | /* We can't handle 64-bit DMA addresses */ | |
406 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
407 | err = -ENOMEM; | |
408 | goto err_unmap; | |
409 | } | |
410 | ||
89184651 TR |
411 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
412 | if (err < 0) | |
e3c97196 | 413 | goto err_unmap; |
7a31f6f4 | 414 | |
e3c97196 | 415 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 416 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 417 | |
89184651 | 418 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 419 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
420 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
421 | smmu_flush(smmu); | |
7a31f6f4 | 422 | |
89184651 TR |
423 | as->smmu = smmu; |
424 | as->use_count++; | |
7a31f6f4 | 425 | |
89184651 | 426 | return 0; |
e3c97196 RK |
427 | |
428 | err_unmap: | |
429 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
430 | return err; | |
7a31f6f4 HD |
431 | } |
432 | ||
89184651 TR |
433 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
434 | struct tegra_smmu_as *as) | |
7a31f6f4 | 435 | { |
89184651 TR |
436 | if (--as->use_count > 0) |
437 | return; | |
438 | ||
439 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
440 | |
441 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
442 | ||
89184651 | 443 | as->smmu = NULL; |
7a31f6f4 HD |
444 | } |
445 | ||
89184651 TR |
446 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
447 | struct device *dev) | |
7a31f6f4 | 448 | { |
89184651 | 449 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 450 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
451 | struct device_node *np = dev->of_node; |
452 | struct of_phandle_args args; | |
453 | unsigned int index = 0; | |
454 | int err = 0; | |
7a31f6f4 | 455 | |
89184651 TR |
456 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
457 | &args)) { | |
458 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 459 | |
89184651 TR |
460 | if (args.np != smmu->dev->of_node) { |
461 | of_node_put(args.np); | |
d2453b2c | 462 | continue; |
89184651 | 463 | } |
d2453b2c | 464 | |
89184651 | 465 | of_node_put(args.np); |
d2453b2c | 466 | |
89184651 TR |
467 | err = tegra_smmu_as_prepare(smmu, as); |
468 | if (err < 0) | |
469 | return err; | |
470 | ||
471 | tegra_smmu_enable(smmu, swgroup, as->id); | |
472 | index++; | |
7a31f6f4 | 473 | } |
7a31f6f4 | 474 | |
89184651 TR |
475 | if (index == 0) |
476 | return -ENODEV; | |
7a31f6f4 | 477 | |
89184651 TR |
478 | return 0; |
479 | } | |
7a31f6f4 | 480 | |
89184651 TR |
481 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
482 | { | |
d5f1a81c | 483 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
484 | struct device_node *np = dev->of_node; |
485 | struct tegra_smmu *smmu = as->smmu; | |
486 | struct of_phandle_args args; | |
487 | unsigned int index = 0; | |
7a31f6f4 | 488 | |
89184651 TR |
489 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
490 | &args)) { | |
491 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 492 | |
89184651 TR |
493 | if (args.np != smmu->dev->of_node) { |
494 | of_node_put(args.np); | |
495 | continue; | |
496 | } | |
23349902 | 497 | |
89184651 | 498 | of_node_put(args.np); |
7a31f6f4 | 499 | |
89184651 TR |
500 | tegra_smmu_disable(smmu, swgroup, as->id); |
501 | tegra_smmu_as_unprepare(smmu, as); | |
502 | index++; | |
503 | } | |
7a31f6f4 HD |
504 | } |
505 | ||
0b42c7c1 RK |
506 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
507 | { | |
508 | u32 *pt = page_address(pt_page); | |
509 | ||
510 | return pt + iova_pt_index(iova); | |
511 | } | |
512 | ||
513 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 514 | dma_addr_t *dmap) |
0b42c7c1 RK |
515 | { |
516 | unsigned int pd_index = iova_pd_index(iova); | |
517 | struct page *pt_page; | |
e3c97196 | 518 | u32 *pd; |
0b42c7c1 | 519 | |
853520fa RK |
520 | pt_page = as->pts[pd_index]; |
521 | if (!pt_page) | |
0b42c7c1 RK |
522 | return NULL; |
523 | ||
e3c97196 RK |
524 | pd = page_address(as->pd); |
525 | *dmap = smmu_pde_to_dma(pd[pd_index]); | |
0b42c7c1 RK |
526 | |
527 | return tegra_smmu_pte_offset(pt_page, iova); | |
528 | } | |
529 | ||
89184651 | 530 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
e3c97196 | 531 | dma_addr_t *dmap) |
7a31f6f4 | 532 | { |
32924c76 | 533 | u32 *pd = page_address(as->pd), *pt; |
34d35f8c | 534 | unsigned int pde = iova_pd_index(iova); |
89184651 | 535 | struct tegra_smmu *smmu = as->smmu; |
89184651 TR |
536 | unsigned int i; |
537 | ||
853520fa | 538 | if (!as->pts[pde]) { |
e3c97196 RK |
539 | struct page *page; |
540 | dma_addr_t dma; | |
541 | ||
89184651 TR |
542 | page = alloc_page(GFP_KERNEL | __GFP_DMA); |
543 | if (!page) | |
544 | return NULL; | |
7a31f6f4 | 545 | |
89184651 | 546 | pt = page_address(page); |
7a31f6f4 | 547 | |
89184651 TR |
548 | for (i = 0; i < SMMU_NUM_PTE; i++) |
549 | pt[i] = 0; | |
7a31f6f4 | 550 | |
e3c97196 RK |
551 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
552 | DMA_TO_DEVICE); | |
553 | if (dma_mapping_error(smmu->dev, dma)) { | |
554 | __free_page(page); | |
555 | return NULL; | |
556 | } | |
557 | ||
558 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
559 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
560 | DMA_TO_DEVICE); | |
561 | __free_page(page); | |
562 | return NULL; | |
563 | } | |
564 | ||
853520fa RK |
565 | as->pts[pde] = page; |
566 | ||
e3c97196 | 567 | pd[pde] = SMMU_MK_PDE(dma, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
7a31f6f4 | 568 | |
e3c97196 RK |
569 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, |
570 | pde << 2, 4, DMA_TO_DEVICE); | |
571 | smmu_flush_ptc(smmu, as->pd_dma, pde << 2); | |
89184651 TR |
572 | smmu_flush_tlb_section(smmu, as->id, iova); |
573 | smmu_flush(smmu); | |
e3c97196 RK |
574 | |
575 | *dmap = dma; | |
89184651 | 576 | } else { |
e3c97196 | 577 | *dmap = smmu_pde_to_dma(pd[pde]); |
7a31f6f4 HD |
578 | } |
579 | ||
e3c97196 | 580 | pt = tegra_smmu_pte_offset(as->pts[pde], iova); |
0b42c7c1 | 581 | |
89184651 | 582 | /* Keep track of entries in this page table. */ |
e3c97196 | 583 | if (*pt == 0) |
32924c76 | 584 | as->count[pde]++; |
7a31f6f4 | 585 | |
e3c97196 | 586 | return pt; |
89184651 | 587 | } |
39abf8aa | 588 | |
b98e34f0 | 589 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 590 | { |
b98e34f0 | 591 | struct tegra_smmu *smmu = as->smmu; |
34d35f8c | 592 | unsigned int pde = iova_pd_index(iova); |
b98e34f0 | 593 | u32 *pd = page_address(as->pd); |
853520fa | 594 | struct page *page = as->pts[pde]; |
39abf8aa | 595 | |
89184651 TR |
596 | /* |
597 | * When no entries in this page table are used anymore, return the | |
598 | * memory page to the system. | |
599 | */ | |
32924c76 | 600 | if (--as->count[pde] == 0) { |
b98e34f0 | 601 | unsigned int offset = pde * sizeof(*pd); |
e3c97196 | 602 | dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]); |
39abf8aa | 603 | |
b98e34f0 RK |
604 | /* Clear the page directory entry first */ |
605 | pd[pde] = 0; | |
606 | ||
607 | /* Flush the page directory entry */ | |
e3c97196 RK |
608 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, |
609 | sizeof(*pd), DMA_TO_DEVICE); | |
610 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
b98e34f0 RK |
611 | smmu_flush_tlb_section(smmu, as->id, iova); |
612 | smmu_flush(smmu); | |
613 | ||
614 | /* Finally, free the page */ | |
e3c97196 | 615 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 616 | __free_page(page); |
853520fa | 617 | as->pts[pde] = NULL; |
39abf8aa | 618 | } |
39abf8aa HD |
619 | } |
620 | ||
8482ee5e | 621 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 622 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
623 | { |
624 | struct tegra_smmu *smmu = as->smmu; | |
625 | unsigned long offset = offset_in_page(pte); | |
626 | ||
627 | *pte = val; | |
628 | ||
e3c97196 RK |
629 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
630 | 4, DMA_TO_DEVICE); | |
631 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
632 | smmu_flush_tlb_group(smmu, as->id, iova); |
633 | smmu_flush(smmu); | |
634 | } | |
635 | ||
89184651 TR |
636 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
637 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 638 | { |
d5f1a81c | 639 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 640 | dma_addr_t pte_dma; |
89184651 | 641 | u32 *pte; |
39abf8aa | 642 | |
e3c97196 | 643 | pte = as_get_pte(as, iova, &pte_dma); |
89184651 TR |
644 | if (!pte) |
645 | return -ENOMEM; | |
39abf8aa | 646 | |
e3c97196 | 647 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
8482ee5e | 648 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); |
39abf8aa | 649 | |
39abf8aa HD |
650 | return 0; |
651 | } | |
652 | ||
89184651 TR |
653 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
654 | size_t size) | |
39abf8aa | 655 | { |
d5f1a81c | 656 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 657 | dma_addr_t pte_dma; |
89184651 | 658 | u32 *pte; |
39abf8aa | 659 | |
e3c97196 | 660 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 661 | if (!pte || !*pte) |
89184651 | 662 | return 0; |
39abf8aa | 663 | |
e3c97196 | 664 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
665 | tegra_smmu_pte_put_use(as, iova); |
666 | ||
89184651 | 667 | return size; |
39abf8aa HD |
668 | } |
669 | ||
89184651 TR |
670 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
671 | dma_addr_t iova) | |
39abf8aa | 672 | { |
d5f1a81c | 673 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 674 | unsigned long pfn; |
e3c97196 | 675 | dma_addr_t pte_dma; |
89184651 | 676 | u32 *pte; |
39abf8aa | 677 | |
e3c97196 | 678 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
679 | if (!pte || !*pte) |
680 | return 0; | |
681 | ||
804cb54c | 682 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 683 | |
89184651 | 684 | return PFN_PHYS(pfn); |
39abf8aa HD |
685 | } |
686 | ||
89184651 | 687 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 688 | { |
89184651 TR |
689 | struct platform_device *pdev; |
690 | struct tegra_mc *mc; | |
7a31f6f4 | 691 | |
89184651 TR |
692 | pdev = of_find_device_by_node(np); |
693 | if (!pdev) | |
694 | return NULL; | |
695 | ||
696 | mc = platform_get_drvdata(pdev); | |
697 | if (!mc) | |
698 | return NULL; | |
699 | ||
700 | return mc->smmu; | |
7a31f6f4 HD |
701 | } |
702 | ||
89184651 | 703 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 704 | { |
89184651 TR |
705 | struct device_node *np = dev->of_node; |
706 | struct of_phandle_args args; | |
707 | unsigned int index = 0; | |
7a31f6f4 | 708 | |
89184651 TR |
709 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
710 | &args) == 0) { | |
711 | struct tegra_smmu *smmu; | |
712 | ||
713 | smmu = tegra_smmu_find(args.np); | |
714 | if (smmu) { | |
715 | /* | |
716 | * Only a single IOMMU master interface is currently | |
717 | * supported by the Linux kernel, so abort after the | |
718 | * first match. | |
719 | */ | |
720 | dev->archdata.iommu = smmu; | |
721 | break; | |
722 | } | |
723 | ||
724 | index++; | |
725 | } | |
726 | ||
727 | return 0; | |
7a31f6f4 HD |
728 | } |
729 | ||
89184651 | 730 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 731 | { |
89184651 TR |
732 | dev->archdata.iommu = NULL; |
733 | } | |
7a31f6f4 | 734 | |
89184651 TR |
735 | static const struct iommu_ops tegra_smmu_ops = { |
736 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
737 | .domain_alloc = tegra_smmu_domain_alloc, |
738 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
739 | .attach_dev = tegra_smmu_attach_dev, |
740 | .detach_dev = tegra_smmu_detach_dev, | |
741 | .add_device = tegra_smmu_add_device, | |
742 | .remove_device = tegra_smmu_remove_device, | |
743 | .map = tegra_smmu_map, | |
744 | .unmap = tegra_smmu_unmap, | |
745 | .map_sg = default_iommu_map_sg, | |
746 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 747 | |
89184651 TR |
748 | .pgsize_bitmap = SZ_4K, |
749 | }; | |
7a31f6f4 | 750 | |
89184651 TR |
751 | static void tegra_smmu_ahb_enable(void) |
752 | { | |
753 | static const struct of_device_id ahb_match[] = { | |
754 | { .compatible = "nvidia,tegra30-ahb", }, | |
755 | { } | |
756 | }; | |
757 | struct device_node *ahb; | |
7a31f6f4 | 758 | |
89184651 TR |
759 | ahb = of_find_matching_node(NULL, ahb_match); |
760 | if (ahb) { | |
761 | tegra_ahb_enable_smmu(ahb); | |
762 | of_node_put(ahb); | |
7a31f6f4 | 763 | } |
89184651 | 764 | } |
7a31f6f4 | 765 | |
d1313e78 TR |
766 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
767 | { | |
768 | struct tegra_smmu *smmu = s->private; | |
769 | unsigned int i; | |
770 | u32 value; | |
771 | ||
772 | seq_printf(s, "swgroup enabled ASID\n"); | |
773 | seq_printf(s, "------------------------\n"); | |
774 | ||
775 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
776 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
777 | const char *status; | |
778 | unsigned int asid; | |
779 | ||
780 | value = smmu_readl(smmu, group->reg); | |
781 | ||
782 | if (value & SMMU_ASID_ENABLE) | |
783 | status = "yes"; | |
784 | else | |
785 | status = "no"; | |
786 | ||
787 | asid = value & SMMU_ASID_MASK; | |
788 | ||
789 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
790 | asid); | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) | |
797 | { | |
798 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); | |
799 | } | |
800 | ||
801 | static const struct file_operations tegra_smmu_swgroups_fops = { | |
802 | .open = tegra_smmu_swgroups_open, | |
803 | .read = seq_read, | |
804 | .llseek = seq_lseek, | |
805 | .release = single_release, | |
806 | }; | |
807 | ||
808 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
809 | { | |
810 | struct tegra_smmu *smmu = s->private; | |
811 | unsigned int i; | |
812 | u32 value; | |
813 | ||
814 | seq_printf(s, "client enabled\n"); | |
815 | seq_printf(s, "--------------------\n"); | |
816 | ||
817 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
818 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
819 | const char *status; | |
820 | ||
821 | value = smmu_readl(smmu, client->smmu.reg); | |
822 | ||
823 | if (value & BIT(client->smmu.bit)) | |
824 | status = "yes"; | |
825 | else | |
826 | status = "no"; | |
827 | ||
828 | seq_printf(s, "%-12s %s\n", client->name, status); | |
829 | } | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) | |
835 | { | |
836 | return single_open(file, tegra_smmu_clients_show, inode->i_private); | |
837 | } | |
838 | ||
839 | static const struct file_operations tegra_smmu_clients_fops = { | |
840 | .open = tegra_smmu_clients_open, | |
841 | .read = seq_read, | |
842 | .llseek = seq_lseek, | |
843 | .release = single_release, | |
844 | }; | |
845 | ||
846 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
847 | { | |
848 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
849 | if (!smmu->debugfs) | |
850 | return; | |
851 | ||
852 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
853 | &tegra_smmu_swgroups_fops); | |
854 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
855 | &tegra_smmu_clients_fops); | |
856 | } | |
857 | ||
858 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
859 | { | |
860 | debugfs_remove_recursive(smmu->debugfs); | |
861 | } | |
862 | ||
89184651 TR |
863 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
864 | const struct tegra_smmu_soc *soc, | |
865 | struct tegra_mc *mc) | |
866 | { | |
867 | struct tegra_smmu *smmu; | |
868 | size_t size; | |
869 | u32 value; | |
870 | int err; | |
7a31f6f4 | 871 | |
89184651 TR |
872 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
873 | if (!soc) | |
874 | return NULL; | |
0760e8fa | 875 | |
89184651 TR |
876 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
877 | if (!smmu) | |
878 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 879 | |
89184651 TR |
880 | /* |
881 | * This is a bit of a hack. Ideally we'd want to simply return this | |
882 | * value. However the IOMMU registration process will attempt to add | |
883 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
884 | * not to rely on global variables to track the IOMMU instance, we | |
885 | * set it here so that it can be looked up from the .add_device() | |
886 | * callback via the IOMMU device's .drvdata field. | |
887 | */ | |
888 | mc->smmu = smmu; | |
0760e8fa | 889 | |
89184651 | 890 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 891 | |
89184651 TR |
892 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
893 | if (!smmu->asids) | |
894 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 895 | |
89184651 | 896 | mutex_init(&smmu->lock); |
7a31f6f4 | 897 | |
89184651 TR |
898 | smmu->regs = mc->regs; |
899 | smmu->soc = soc; | |
900 | smmu->dev = dev; | |
901 | smmu->mc = mc; | |
7a31f6f4 | 902 | |
804cb54c TR |
903 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
904 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
905 | mc->soc->num_address_bits, smmu->pfn_mask); | |
906 | ||
89184651 | 907 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 908 | |
89184651 TR |
909 | if (soc->supports_request_limit) |
910 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 911 | |
89184651 | 912 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 913 | |
89184651 TR |
914 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
915 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); | |
7a31f6f4 | 916 | |
89184651 TR |
917 | if (soc->supports_round_robin_arbitration) |
918 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 919 | |
89184651 | 920 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 921 | |
b8fe0382 | 922 | smmu_flush_ptc_all(smmu); |
89184651 TR |
923 | smmu_flush_tlb(smmu); |
924 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
925 | smmu_flush(smmu); | |
926 | ||
927 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 928 | |
89184651 TR |
929 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
930 | if (err < 0) | |
931 | return ERR_PTR(err); | |
7a31f6f4 | 932 | |
d1313e78 TR |
933 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
934 | tegra_smmu_debugfs_init(smmu); | |
935 | ||
89184651 TR |
936 | return smmu; |
937 | } | |
d1313e78 TR |
938 | |
939 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
940 | { | |
941 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
942 | tegra_smmu_debugfs_exit(smmu); | |
943 | } |