Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7a31f6f4 | 2 | /* |
89184651 | 3 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 HD |
4 | */ |
5 | ||
804cb54c | 6 | #include <linux/bitops.h> |
d1313e78 | 7 | #include <linux/debugfs.h> |
bc5e6dea | 8 | #include <linux/err.h> |
7a31f6f4 | 9 | #include <linux/iommu.h> |
89184651 | 10 | #include <linux/kernel.h> |
0760e8fa | 11 | #include <linux/of.h> |
89184651 | 12 | #include <linux/of_device.h> |
541f29bb | 13 | #include <linux/pci.h> |
89184651 TR |
14 | #include <linux/platform_device.h> |
15 | #include <linux/slab.h> | |
404d0b30 | 16 | #include <linux/spinlock.h> |
461a6946 | 17 | #include <linux/dma-mapping.h> |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
7f4c9176 TR |
22 | struct tegra_smmu_group { |
23 | struct list_head list; | |
1ea5440e | 24 | struct tegra_smmu *smmu; |
7f4c9176 TR |
25 | const struct tegra_smmu_group_soc *soc; |
26 | struct iommu_group *group; | |
21d3c040 | 27 | unsigned int swgroup; |
7f4c9176 TR |
28 | }; |
29 | ||
89184651 TR |
30 | struct tegra_smmu { |
31 | void __iomem *regs; | |
32 | struct device *dev; | |
e6bc5933 | 33 | |
89184651 TR |
34 | struct tegra_mc *mc; |
35 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 36 | |
7f4c9176 TR |
37 | struct list_head groups; |
38 | ||
804cb54c | 39 | unsigned long pfn_mask; |
11cec15b | 40 | unsigned long tlb_mask; |
804cb54c | 41 | |
89184651 TR |
42 | unsigned long *asids; |
43 | struct mutex lock; | |
39abf8aa | 44 | |
89184651 | 45 | struct list_head list; |
d1313e78 TR |
46 | |
47 | struct dentry *debugfs; | |
0b480e44 JR |
48 | |
49 | struct iommu_device iommu; /* IOMMU Core code handle */ | |
7a31f6f4 | 50 | }; |
7a31f6f4 | 51 | |
89184651 | 52 | struct tegra_smmu_as { |
d5f1a81c | 53 | struct iommu_domain domain; |
89184651 TR |
54 | struct tegra_smmu *smmu; |
55 | unsigned int use_count; | |
404d0b30 | 56 | spinlock_t lock; |
32924c76 | 57 | u32 *count; |
853520fa | 58 | struct page **pts; |
89184651 | 59 | struct page *pd; |
e3c97196 | 60 | dma_addr_t pd_dma; |
89184651 TR |
61 | unsigned id; |
62 | u32 attr; | |
7a31f6f4 HD |
63 | }; |
64 | ||
d5f1a81c JR |
65 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
66 | { | |
67 | return container_of(dom, struct tegra_smmu_as, domain); | |
68 | } | |
69 | ||
89184651 TR |
70 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
71 | unsigned long offset) | |
72 | { | |
73 | writel(value, smmu->regs + offset); | |
74 | } | |
7a31f6f4 | 75 | |
89184651 TR |
76 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
77 | { | |
78 | return readl(smmu->regs + offset); | |
79 | } | |
5a2c937a | 80 | |
89184651 TR |
81 | #define SMMU_CONFIG 0x010 |
82 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 83 | |
89184651 TR |
84 | #define SMMU_TLB_CONFIG 0x14 |
85 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
86 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
11cec15b TR |
87 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ |
88 | ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask) | |
0760e8fa | 89 | |
89184651 TR |
90 | #define SMMU_PTC_CONFIG 0x18 |
91 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
92 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
93 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 94 | |
89184651 TR |
95 | #define SMMU_PTB_ASID 0x01c |
96 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 97 | |
89184651 | 98 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 99 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 100 | |
e3c97196 | 101 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 102 | |
89184651 TR |
103 | #define SMMU_TLB_FLUSH 0x030 |
104 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
105 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
106 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
89184651 TR |
107 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
108 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
109 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
110 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
111 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 112 | |
89184651 TR |
113 | #define SMMU_PTC_FLUSH 0x034 |
114 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
115 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 116 | |
89184651 TR |
117 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
118 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 119 | |
89184651 TR |
120 | /* per-SWGROUP SMMU_*_ASID register */ |
121 | #define SMMU_ASID_ENABLE (1 << 31) | |
122 | #define SMMU_ASID_MASK 0x7f | |
123 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 124 | |
89184651 TR |
125 | /* page table definitions */ |
126 | #define SMMU_NUM_PDE 1024 | |
127 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 128 | |
89184651 TR |
129 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
130 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 131 | |
89184651 TR |
132 | #define SMMU_PDE_SHIFT 22 |
133 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 134 | |
82fa58e8 NC |
135 | #define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1)) |
136 | #define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK) | |
137 | #define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT) | |
138 | #define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT)) | |
139 | ||
89184651 TR |
140 | #define SMMU_PD_READABLE (1 << 31) |
141 | #define SMMU_PD_WRITABLE (1 << 30) | |
142 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 143 | |
89184651 TR |
144 | #define SMMU_PDE_READABLE (1 << 31) |
145 | #define SMMU_PDE_WRITABLE (1 << 30) | |
146 | #define SMMU_PDE_NONSECURE (1 << 29) | |
147 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 148 | |
89184651 TR |
149 | #define SMMU_PTE_READABLE (1 << 31) |
150 | #define SMMU_PTE_WRITABLE (1 << 30) | |
151 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 152 | |
89184651 TR |
153 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
154 | SMMU_PDE_NONSECURE) | |
7a31f6f4 | 155 | |
34d35f8c RK |
156 | static unsigned int iova_pd_index(unsigned long iova) |
157 | { | |
158 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
159 | } | |
160 | ||
161 | static unsigned int iova_pt_index(unsigned long iova) | |
162 | { | |
163 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
164 | } | |
165 | ||
e3c97196 | 166 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 167 | { |
e3c97196 RK |
168 | addr >>= 12; |
169 | return (addr & smmu->pfn_mask) == addr; | |
170 | } | |
4b3c7d10 | 171 | |
96d3ab80 | 172 | static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde) |
e3c97196 | 173 | { |
96d3ab80 | 174 | return (dma_addr_t)(pde & smmu->pfn_mask) << 12; |
4b3c7d10 RK |
175 | } |
176 | ||
b8fe0382 RK |
177 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
178 | { | |
179 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
180 | } | |
181 | ||
e3c97196 | 182 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 183 | unsigned long offset) |
7a31f6f4 | 184 | { |
89184651 TR |
185 | u32 value; |
186 | ||
b8fe0382 | 187 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 188 | |
b8fe0382 | 189 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
190 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
191 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 192 | #else |
b8fe0382 | 193 | value = 0; |
89184651 | 194 | #endif |
b8fe0382 | 195 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 196 | } |
89184651 | 197 | |
e3c97196 | 198 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 199 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
200 | } |
201 | ||
89184651 | 202 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 203 | { |
89184651 | 204 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
205 | } |
206 | ||
89184651 TR |
207 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
208 | unsigned long asid) | |
7a31f6f4 | 209 | { |
89184651 | 210 | u32 value; |
7a31f6f4 | 211 | |
43a0541e DO |
212 | if (smmu->soc->num_asids == 4) |
213 | value = (asid & 0x3) << 29; | |
214 | else | |
215 | value = (asid & 0x7f) << 24; | |
216 | ||
217 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
89184651 | 218 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
219 | } |
220 | ||
89184651 TR |
221 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
222 | unsigned long asid, | |
223 | unsigned long iova) | |
7a31f6f4 | 224 | { |
89184651 | 225 | u32 value; |
7a31f6f4 | 226 | |
43a0541e DO |
227 | if (smmu->soc->num_asids == 4) |
228 | value = (asid & 0x3) << 29; | |
229 | else | |
230 | value = (asid & 0x7f) << 24; | |
231 | ||
232 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
89184651 | 233 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
234 | } |
235 | ||
89184651 TR |
236 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
237 | unsigned long asid, | |
238 | unsigned long iova) | |
7a31f6f4 | 239 | { |
89184651 | 240 | u32 value; |
7a31f6f4 | 241 | |
43a0541e DO |
242 | if (smmu->soc->num_asids == 4) |
243 | value = (asid & 0x3) << 29; | |
244 | else | |
245 | value = (asid & 0x7f) << 24; | |
246 | ||
247 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
89184651 | 248 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
249 | } |
250 | ||
89184651 | 251 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 252 | { |
446152d5 | 253 | smmu_readl(smmu, SMMU_PTB_ASID); |
7a31f6f4 HD |
254 | } |
255 | ||
89184651 | 256 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 257 | { |
89184651 | 258 | unsigned long id; |
7a31f6f4 | 259 | |
89184651 | 260 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
d5f583bf | 261 | if (id >= smmu->soc->num_asids) |
89184651 | 262 | return -ENOSPC; |
7a31f6f4 | 263 | |
89184651 TR |
264 | set_bit(id, smmu->asids); |
265 | *idp = id; | |
266 | ||
89184651 | 267 | return 0; |
7a31f6f4 HD |
268 | } |
269 | ||
89184651 | 270 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 271 | { |
89184651 | 272 | clear_bit(id, smmu->asids); |
7a31f6f4 | 273 | } |
89184651 | 274 | |
d5f1a81c | 275 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 276 | { |
89184651 | 277 | struct tegra_smmu_as *as; |
7a31f6f4 | 278 | |
d5f1a81c JR |
279 | if (type != IOMMU_DOMAIN_UNMANAGED) |
280 | return NULL; | |
281 | ||
89184651 TR |
282 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
283 | if (!as) | |
d5f1a81c | 284 | return NULL; |
7a31f6f4 | 285 | |
89184651 | 286 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 287 | |
707917cb | 288 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
289 | if (!as->pd) { |
290 | kfree(as); | |
d5f1a81c | 291 | return NULL; |
7a31f6f4 | 292 | } |
9e971a03 | 293 | |
32924c76 | 294 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
295 | if (!as->count) { |
296 | __free_page(as->pd); | |
297 | kfree(as); | |
d5f1a81c | 298 | return NULL; |
7a31f6f4 | 299 | } |
9e971a03 | 300 | |
853520fa RK |
301 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
302 | if (!as->pts) { | |
32924c76 | 303 | kfree(as->count); |
853520fa RK |
304 | __free_page(as->pd); |
305 | kfree(as); | |
306 | return NULL; | |
307 | } | |
308 | ||
404d0b30 DO |
309 | spin_lock_init(&as->lock); |
310 | ||
471d9144 | 311 | /* setup aperture */ |
7f65ef01 JR |
312 | as->domain.geometry.aperture_start = 0; |
313 | as->domain.geometry.aperture_end = 0xffffffff; | |
314 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 315 | |
d5f1a81c | 316 | return &as->domain; |
7a31f6f4 HD |
317 | } |
318 | ||
d5f1a81c | 319 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 320 | { |
d5f1a81c | 321 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 322 | |
89184651 | 323 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 324 | |
4f97031f DO |
325 | WARN_ON_ONCE(as->use_count); |
326 | kfree(as->count); | |
327 | kfree(as->pts); | |
89184651 | 328 | kfree(as); |
7a31f6f4 HD |
329 | } |
330 | ||
89184651 TR |
331 | static const struct tegra_smmu_swgroup * |
332 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 333 | { |
89184651 TR |
334 | const struct tegra_smmu_swgroup *group = NULL; |
335 | unsigned int i; | |
7a31f6f4 | 336 | |
89184651 TR |
337 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
338 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
339 | group = &smmu->soc->swgroups[i]; | |
340 | break; | |
341 | } | |
342 | } | |
7a31f6f4 | 343 | |
89184651 | 344 | return group; |
7a31f6f4 HD |
345 | } |
346 | ||
89184651 TR |
347 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
348 | unsigned int asid) | |
7a31f6f4 | 349 | { |
89184651 TR |
350 | const struct tegra_smmu_swgroup *group; |
351 | unsigned int i; | |
352 | u32 value; | |
7a31f6f4 | 353 | |
e31e5929 NK |
354 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
355 | if (group) { | |
356 | value = smmu_readl(smmu, group->reg); | |
357 | value &= ~SMMU_ASID_MASK; | |
358 | value |= SMMU_ASID_VALUE(asid); | |
359 | value |= SMMU_ASID_ENABLE; | |
360 | smmu_writel(smmu, value, group->reg); | |
361 | } else { | |
362 | pr_warn("%s group from swgroup %u not found\n", __func__, | |
363 | swgroup); | |
364 | /* No point moving ahead if group was not found */ | |
365 | return; | |
366 | } | |
367 | ||
89184651 TR |
368 | for (i = 0; i < smmu->soc->num_clients; i++) { |
369 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 370 | |
89184651 TR |
371 | if (client->swgroup != swgroup) |
372 | continue; | |
7a31f6f4 | 373 | |
4f1ac76e TR |
374 | value = smmu_readl(smmu, client->regs.smmu.reg); |
375 | value |= BIT(client->regs.smmu.bit); | |
376 | smmu_writel(smmu, value, client->regs.smmu.reg); | |
89184651 | 377 | } |
7a31f6f4 HD |
378 | } |
379 | ||
89184651 TR |
380 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
381 | unsigned int asid) | |
7a31f6f4 | 382 | { |
89184651 TR |
383 | const struct tegra_smmu_swgroup *group; |
384 | unsigned int i; | |
385 | u32 value; | |
7a31f6f4 | 386 | |
89184651 TR |
387 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
388 | if (group) { | |
389 | value = smmu_readl(smmu, group->reg); | |
390 | value &= ~SMMU_ASID_MASK; | |
391 | value |= SMMU_ASID_VALUE(asid); | |
392 | value &= ~SMMU_ASID_ENABLE; | |
393 | smmu_writel(smmu, value, group->reg); | |
394 | } | |
7a31f6f4 | 395 | |
89184651 TR |
396 | for (i = 0; i < smmu->soc->num_clients; i++) { |
397 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 398 | |
89184651 TR |
399 | if (client->swgroup != swgroup) |
400 | continue; | |
7a31f6f4 | 401 | |
4f1ac76e TR |
402 | value = smmu_readl(smmu, client->regs.smmu.reg); |
403 | value &= ~BIT(client->regs.smmu.bit); | |
404 | smmu_writel(smmu, value, client->regs.smmu.reg); | |
89184651 | 405 | } |
7a31f6f4 HD |
406 | } |
407 | ||
89184651 TR |
408 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
409 | struct tegra_smmu_as *as) | |
7a31f6f4 | 410 | { |
89184651 | 411 | u32 value; |
d5f583bf NC |
412 | int err = 0; |
413 | ||
414 | mutex_lock(&smmu->lock); | |
7a31f6f4 | 415 | |
89184651 TR |
416 | if (as->use_count > 0) { |
417 | as->use_count++; | |
d5f583bf | 418 | goto unlock; |
7a31f6f4 | 419 | } |
7a31f6f4 | 420 | |
e3c97196 RK |
421 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
422 | DMA_TO_DEVICE); | |
d5f583bf NC |
423 | if (dma_mapping_error(smmu->dev, as->pd_dma)) { |
424 | err = -ENOMEM; | |
425 | goto unlock; | |
426 | } | |
e3c97196 RK |
427 | |
428 | /* We can't handle 64-bit DMA addresses */ | |
429 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
430 | err = -ENOMEM; | |
431 | goto err_unmap; | |
432 | } | |
433 | ||
89184651 TR |
434 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
435 | if (err < 0) | |
e3c97196 | 436 | goto err_unmap; |
7a31f6f4 | 437 | |
e3c97196 | 438 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 439 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 440 | |
89184651 | 441 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 442 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
443 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
444 | smmu_flush(smmu); | |
7a31f6f4 | 445 | |
89184651 TR |
446 | as->smmu = smmu; |
447 | as->use_count++; | |
7a31f6f4 | 448 | |
d5f583bf NC |
449 | mutex_unlock(&smmu->lock); |
450 | ||
89184651 | 451 | return 0; |
e3c97196 RK |
452 | |
453 | err_unmap: | |
454 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
d5f583bf NC |
455 | unlock: |
456 | mutex_unlock(&smmu->lock); | |
457 | ||
e3c97196 | 458 | return err; |
7a31f6f4 HD |
459 | } |
460 | ||
89184651 TR |
461 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
462 | struct tegra_smmu_as *as) | |
7a31f6f4 | 463 | { |
d5f583bf NC |
464 | mutex_lock(&smmu->lock); |
465 | ||
466 | if (--as->use_count > 0) { | |
467 | mutex_unlock(&smmu->lock); | |
89184651 | 468 | return; |
d5f583bf | 469 | } |
89184651 TR |
470 | |
471 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
472 | |
473 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
474 | ||
89184651 | 475 | as->smmu = NULL; |
d5f583bf NC |
476 | |
477 | mutex_unlock(&smmu->lock); | |
7a31f6f4 HD |
478 | } |
479 | ||
89184651 TR |
480 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
481 | struct device *dev) | |
7a31f6f4 | 482 | { |
8750d207 | 483 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
a5616e24 | 484 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
d5f1a81c | 485 | struct tegra_smmu_as *as = to_smmu_as(domain); |
8750d207 NC |
486 | unsigned int index; |
487 | int err; | |
d2453b2c | 488 | |
8750d207 NC |
489 | if (!fwspec) |
490 | return -ENOENT; | |
d2453b2c | 491 | |
8750d207 | 492 | for (index = 0; index < fwspec->num_ids; index++) { |
89184651 | 493 | err = tegra_smmu_as_prepare(smmu, as); |
8750d207 NC |
494 | if (err) |
495 | goto disable; | |
89184651 | 496 | |
8750d207 | 497 | tegra_smmu_enable(smmu, fwspec->ids[index], as->id); |
7a31f6f4 | 498 | } |
7a31f6f4 | 499 | |
89184651 TR |
500 | if (index == 0) |
501 | return -ENODEV; | |
7a31f6f4 | 502 | |
89184651 | 503 | return 0; |
8750d207 NC |
504 | |
505 | disable: | |
506 | while (index--) { | |
507 | tegra_smmu_disable(smmu, fwspec->ids[index], as->id); | |
508 | tegra_smmu_as_unprepare(smmu, as); | |
509 | } | |
510 | ||
511 | return err; | |
89184651 | 512 | } |
7a31f6f4 | 513 | |
89184651 TR |
514 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
515 | { | |
8750d207 | 516 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
d5f1a81c | 517 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 518 | struct tegra_smmu *smmu = as->smmu; |
8750d207 | 519 | unsigned int index; |
7a31f6f4 | 520 | |
8750d207 NC |
521 | if (!fwspec) |
522 | return; | |
7a31f6f4 | 523 | |
8750d207 NC |
524 | for (index = 0; index < fwspec->num_ids; index++) { |
525 | tegra_smmu_disable(smmu, fwspec->ids[index], as->id); | |
89184651 | 526 | tegra_smmu_as_unprepare(smmu, as); |
89184651 | 527 | } |
7a31f6f4 HD |
528 | } |
529 | ||
4080e99b RK |
530 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
531 | u32 value) | |
532 | { | |
533 | unsigned int pd_index = iova_pd_index(iova); | |
534 | struct tegra_smmu *smmu = as->smmu; | |
535 | u32 *pd = page_address(as->pd); | |
536 | unsigned long offset = pd_index * sizeof(*pd); | |
537 | ||
538 | /* Set the page directory entry first */ | |
539 | pd[pd_index] = value; | |
540 | ||
541 | /* The flush the page directory entry from caches */ | |
542 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
543 | sizeof(*pd), DMA_TO_DEVICE); | |
544 | ||
545 | /* And flush the iommu */ | |
546 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
547 | smmu_flush_tlb_section(smmu, as->id, iova); | |
548 | smmu_flush(smmu); | |
549 | } | |
550 | ||
0b42c7c1 RK |
551 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
552 | { | |
553 | u32 *pt = page_address(pt_page); | |
554 | ||
555 | return pt + iova_pt_index(iova); | |
556 | } | |
557 | ||
558 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 559 | dma_addr_t *dmap) |
0b42c7c1 RK |
560 | { |
561 | unsigned int pd_index = iova_pd_index(iova); | |
96d3ab80 | 562 | struct tegra_smmu *smmu = as->smmu; |
0b42c7c1 | 563 | struct page *pt_page; |
e3c97196 | 564 | u32 *pd; |
0b42c7c1 | 565 | |
853520fa RK |
566 | pt_page = as->pts[pd_index]; |
567 | if (!pt_page) | |
0b42c7c1 RK |
568 | return NULL; |
569 | ||
e3c97196 | 570 | pd = page_address(as->pd); |
96d3ab80 | 571 | *dmap = smmu_pde_to_dma(smmu, pd[pd_index]); |
0b42c7c1 RK |
572 | |
573 | return tegra_smmu_pte_offset(pt_page, iova); | |
574 | } | |
575 | ||
89184651 | 576 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
404d0b30 | 577 | dma_addr_t *dmap, struct page *page) |
7a31f6f4 | 578 | { |
34d35f8c | 579 | unsigned int pde = iova_pd_index(iova); |
89184651 | 580 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 581 | |
853520fa | 582 | if (!as->pts[pde]) { |
e3c97196 RK |
583 | dma_addr_t dma; |
584 | ||
e3c97196 RK |
585 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
586 | DMA_TO_DEVICE); | |
587 | if (dma_mapping_error(smmu->dev, dma)) { | |
588 | __free_page(page); | |
589 | return NULL; | |
590 | } | |
591 | ||
592 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
593 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
594 | DMA_TO_DEVICE); | |
595 | __free_page(page); | |
596 | return NULL; | |
597 | } | |
598 | ||
853520fa RK |
599 | as->pts[pde] = page; |
600 | ||
4080e99b RK |
601 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
602 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
603 | |
604 | *dmap = dma; | |
89184651 | 605 | } else { |
4080e99b RK |
606 | u32 *pd = page_address(as->pd); |
607 | ||
96d3ab80 | 608 | *dmap = smmu_pde_to_dma(smmu, pd[pde]); |
7a31f6f4 HD |
609 | } |
610 | ||
7ffc6f06 RK |
611 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
612 | } | |
0b42c7c1 | 613 | |
7ffc6f06 RK |
614 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
615 | { | |
616 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 617 | |
7ffc6f06 | 618 | as->count[pd_index]++; |
89184651 | 619 | } |
39abf8aa | 620 | |
b98e34f0 | 621 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 622 | { |
34d35f8c | 623 | unsigned int pde = iova_pd_index(iova); |
853520fa | 624 | struct page *page = as->pts[pde]; |
39abf8aa | 625 | |
89184651 TR |
626 | /* |
627 | * When no entries in this page table are used anymore, return the | |
628 | * memory page to the system. | |
629 | */ | |
32924c76 | 630 | if (--as->count[pde] == 0) { |
4080e99b RK |
631 | struct tegra_smmu *smmu = as->smmu; |
632 | u32 *pd = page_address(as->pd); | |
96d3ab80 | 633 | dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]); |
39abf8aa | 634 | |
4080e99b | 635 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 636 | |
e3c97196 | 637 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 638 | __free_page(page); |
853520fa | 639 | as->pts[pde] = NULL; |
39abf8aa | 640 | } |
39abf8aa HD |
641 | } |
642 | ||
8482ee5e | 643 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 644 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
645 | { |
646 | struct tegra_smmu *smmu = as->smmu; | |
82fa58e8 | 647 | unsigned long offset = SMMU_OFFSET_IN_PAGE(pte); |
8482ee5e RK |
648 | |
649 | *pte = val; | |
650 | ||
e3c97196 RK |
651 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
652 | 4, DMA_TO_DEVICE); | |
653 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
654 | smmu_flush_tlb_group(smmu, as->id, iova); |
655 | smmu_flush(smmu); | |
656 | } | |
657 | ||
404d0b30 DO |
658 | static struct page *as_get_pde_page(struct tegra_smmu_as *as, |
659 | unsigned long iova, gfp_t gfp, | |
660 | unsigned long *flags) | |
661 | { | |
662 | unsigned int pde = iova_pd_index(iova); | |
663 | struct page *page = as->pts[pde]; | |
664 | ||
665 | /* at first check whether allocation needs to be done at all */ | |
666 | if (page) | |
667 | return page; | |
668 | ||
669 | /* | |
670 | * In order to prevent exhaustion of the atomic memory pool, we | |
671 | * allocate page in a sleeping context if GFP flags permit. Hence | |
672 | * spinlock needs to be unlocked and re-locked after allocation. | |
673 | */ | |
674 | if (!(gfp & __GFP_ATOMIC)) | |
675 | spin_unlock_irqrestore(&as->lock, *flags); | |
676 | ||
677 | page = alloc_page(gfp | __GFP_DMA | __GFP_ZERO); | |
678 | ||
679 | if (!(gfp & __GFP_ATOMIC)) | |
680 | spin_lock_irqsave(&as->lock, *flags); | |
681 | ||
682 | /* | |
683 | * In a case of blocking allocation, a concurrent mapping may win | |
684 | * the PDE allocation. In this case the allocated page isn't needed | |
685 | * if allocation succeeded and the allocation failure isn't fatal. | |
686 | */ | |
687 | if (as->pts[pde]) { | |
688 | if (page) | |
689 | __free_page(page); | |
690 | ||
691 | page = as->pts[pde]; | |
692 | } | |
693 | ||
694 | return page; | |
695 | } | |
696 | ||
697 | static int | |
698 | __tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
699 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp, | |
700 | unsigned long *flags) | |
39abf8aa | 701 | { |
d5f1a81c | 702 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 703 | dma_addr_t pte_dma; |
404d0b30 | 704 | struct page *page; |
43d957b1 | 705 | u32 pte_attrs; |
89184651 | 706 | u32 *pte; |
39abf8aa | 707 | |
404d0b30 DO |
708 | page = as_get_pde_page(as, iova, gfp, flags); |
709 | if (!page) | |
710 | return -ENOMEM; | |
711 | ||
712 | pte = as_get_pte(as, iova, &pte_dma, page); | |
89184651 TR |
713 | if (!pte) |
714 | return -ENOMEM; | |
39abf8aa | 715 | |
7ffc6f06 RK |
716 | /* If we aren't overwriting a pre-existing entry, increment use */ |
717 | if (*pte == 0) | |
718 | tegra_smmu_pte_get_use(as, iova); | |
719 | ||
43d957b1 DO |
720 | pte_attrs = SMMU_PTE_NONSECURE; |
721 | ||
722 | if (prot & IOMMU_READ) | |
723 | pte_attrs |= SMMU_PTE_READABLE; | |
724 | ||
725 | if (prot & IOMMU_WRITE) | |
726 | pte_attrs |= SMMU_PTE_WRITABLE; | |
727 | ||
e3c97196 | 728 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
82fa58e8 | 729 | SMMU_PHYS_PFN(paddr) | pte_attrs); |
39abf8aa | 730 | |
39abf8aa HD |
731 | return 0; |
732 | } | |
733 | ||
404d0b30 DO |
734 | static size_t |
735 | __tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
736 | size_t size, struct iommu_iotlb_gather *gather) | |
39abf8aa | 737 | { |
d5f1a81c | 738 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 739 | dma_addr_t pte_dma; |
89184651 | 740 | u32 *pte; |
39abf8aa | 741 | |
e3c97196 | 742 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 743 | if (!pte || !*pte) |
89184651 | 744 | return 0; |
39abf8aa | 745 | |
e3c97196 | 746 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
747 | tegra_smmu_pte_put_use(as, iova); |
748 | ||
89184651 | 749 | return size; |
39abf8aa HD |
750 | } |
751 | ||
404d0b30 DO |
752 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
753 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) | |
754 | { | |
755 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
756 | unsigned long flags; | |
757 | int ret; | |
758 | ||
759 | spin_lock_irqsave(&as->lock, flags); | |
760 | ret = __tegra_smmu_map(domain, iova, paddr, size, prot, gfp, &flags); | |
761 | spin_unlock_irqrestore(&as->lock, flags); | |
762 | ||
763 | return ret; | |
764 | } | |
765 | ||
766 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
767 | size_t size, struct iommu_iotlb_gather *gather) | |
768 | { | |
769 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
770 | unsigned long flags; | |
771 | ||
772 | spin_lock_irqsave(&as->lock, flags); | |
773 | size = __tegra_smmu_unmap(domain, iova, size, gather); | |
774 | spin_unlock_irqrestore(&as->lock, flags); | |
775 | ||
776 | return size; | |
777 | } | |
778 | ||
89184651 TR |
779 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
780 | dma_addr_t iova) | |
39abf8aa | 781 | { |
d5f1a81c | 782 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 783 | unsigned long pfn; |
e3c97196 | 784 | dma_addr_t pte_dma; |
89184651 | 785 | u32 *pte; |
39abf8aa | 786 | |
e3c97196 | 787 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
788 | if (!pte || !*pte) |
789 | return 0; | |
790 | ||
804cb54c | 791 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 792 | |
4fba9885 | 793 | return SMMU_PFN_PHYS(pfn) + SMMU_OFFSET_IN_PAGE(iova); |
39abf8aa HD |
794 | } |
795 | ||
765a9d1d NC |
796 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
797 | { | |
798 | struct platform_device *pdev; | |
799 | struct tegra_mc *mc; | |
800 | ||
801 | pdev = of_find_device_by_node(np); | |
802 | if (!pdev) | |
803 | return NULL; | |
804 | ||
805 | mc = platform_get_drvdata(pdev); | |
9826e393 ML |
806 | if (!mc) { |
807 | put_device(&pdev->dev); | |
765a9d1d | 808 | return NULL; |
9826e393 | 809 | } |
765a9d1d NC |
810 | |
811 | return mc->smmu; | |
812 | } | |
813 | ||
814 | static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, | |
815 | struct of_phandle_args *args) | |
816 | { | |
817 | const struct iommu_ops *ops = smmu->iommu.ops; | |
818 | int err; | |
819 | ||
820 | err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops); | |
821 | if (err < 0) { | |
822 | dev_err(dev, "failed to initialize fwspec: %d\n", err); | |
823 | return err; | |
824 | } | |
825 | ||
826 | err = ops->of_xlate(dev, args); | |
827 | if (err < 0) { | |
828 | dev_err(dev, "failed to parse SW group ID: %d\n", err); | |
829 | iommu_fwspec_free(dev); | |
830 | return err; | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
b287ba73 | 836 | static struct iommu_device *tegra_smmu_probe_device(struct device *dev) |
7a31f6f4 | 837 | { |
765a9d1d NC |
838 | struct device_node *np = dev->of_node; |
839 | struct tegra_smmu *smmu = NULL; | |
840 | struct of_phandle_args args; | |
841 | unsigned int index = 0; | |
842 | int err; | |
843 | ||
844 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, | |
845 | &args) == 0) { | |
846 | smmu = tegra_smmu_find(args.np); | |
847 | if (smmu) { | |
848 | err = tegra_smmu_configure(smmu, dev, &args); | |
89184651 | 849 | |
8dfd0fa6 DO |
850 | if (err < 0) { |
851 | of_node_put(args.np); | |
765a9d1d | 852 | return ERR_PTR(err); |
8dfd0fa6 | 853 | } |
765a9d1d NC |
854 | } |
855 | ||
856 | of_node_put(args.np); | |
857 | index++; | |
858 | } | |
859 | ||
860 | smmu = dev_iommu_priv_get(dev); | |
7f4c9176 | 861 | if (!smmu) |
b287ba73 | 862 | return ERR_PTR(-ENODEV); |
d92e1f84 | 863 | |
b287ba73 | 864 | return &smmu->iommu; |
7a31f6f4 HD |
865 | } |
866 | ||
7f4c9176 TR |
867 | static const struct tegra_smmu_group_soc * |
868 | tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) | |
869 | { | |
870 | unsigned int i, j; | |
871 | ||
872 | for (i = 0; i < smmu->soc->num_groups; i++) | |
873 | for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) | |
874 | if (smmu->soc->groups[i].swgroups[j] == swgroup) | |
875 | return &smmu->soc->groups[i]; | |
876 | ||
877 | return NULL; | |
878 | } | |
879 | ||
1ea5440e TR |
880 | static void tegra_smmu_group_release(void *iommu_data) |
881 | { | |
882 | struct tegra_smmu_group *group = iommu_data; | |
883 | struct tegra_smmu *smmu = group->smmu; | |
884 | ||
885 | mutex_lock(&smmu->lock); | |
886 | list_del(&group->list); | |
887 | mutex_unlock(&smmu->lock); | |
888 | } | |
889 | ||
cf910f61 | 890 | static struct iommu_group *tegra_smmu_device_group(struct device *dev) |
7f4c9176 | 891 | { |
cf910f61 NC |
892 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
893 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); | |
7f4c9176 | 894 | const struct tegra_smmu_group_soc *soc; |
cf910f61 | 895 | unsigned int swgroup = fwspec->ids[0]; |
7f4c9176 | 896 | struct tegra_smmu_group *group; |
5b30fbfa | 897 | struct iommu_group *grp; |
7f4c9176 | 898 | |
21d3c040 | 899 | /* Find group_soc associating with swgroup */ |
7f4c9176 | 900 | soc = tegra_smmu_find_group(smmu, swgroup); |
7f4c9176 TR |
901 | |
902 | mutex_lock(&smmu->lock); | |
903 | ||
21d3c040 | 904 | /* Find existing iommu_group associating with swgroup or group_soc */ |
7f4c9176 | 905 | list_for_each_entry(group, &smmu->groups, list) |
21d3c040 | 906 | if ((group->swgroup == swgroup) || (soc && group->soc == soc)) { |
5b30fbfa | 907 | grp = iommu_group_ref_get(group->group); |
7f4c9176 | 908 | mutex_unlock(&smmu->lock); |
5b30fbfa | 909 | return grp; |
7f4c9176 TR |
910 | } |
911 | ||
912 | group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL); | |
913 | if (!group) { | |
914 | mutex_unlock(&smmu->lock); | |
915 | return NULL; | |
916 | } | |
917 | ||
918 | INIT_LIST_HEAD(&group->list); | |
21d3c040 | 919 | group->swgroup = swgroup; |
1ea5440e | 920 | group->smmu = smmu; |
7f4c9176 TR |
921 | group->soc = soc; |
922 | ||
541f29bb NC |
923 | if (dev_is_pci(dev)) |
924 | group->group = pci_device_group(dev); | |
925 | else | |
926 | group->group = generic_device_group(dev); | |
927 | ||
83476bfa | 928 | if (IS_ERR(group->group)) { |
7f4c9176 TR |
929 | devm_kfree(smmu->dev, group); |
930 | mutex_unlock(&smmu->lock); | |
931 | return NULL; | |
932 | } | |
933 | ||
1ea5440e | 934 | iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release); |
21d3c040 NC |
935 | if (soc) |
936 | iommu_group_set_name(group->group, soc->name); | |
7f4c9176 TR |
937 | list_add_tail(&group->list, &smmu->groups); |
938 | mutex_unlock(&smmu->lock); | |
939 | ||
940 | return group->group; | |
941 | } | |
942 | ||
7f4c9176 TR |
943 | static int tegra_smmu_of_xlate(struct device *dev, |
944 | struct of_phandle_args *args) | |
945 | { | |
25938c73 NC |
946 | struct platform_device *iommu_pdev = of_find_device_by_node(args->np); |
947 | struct tegra_mc *mc = platform_get_drvdata(iommu_pdev); | |
7f4c9176 TR |
948 | u32 id = args->args[0]; |
949 | ||
25938c73 NC |
950 | /* |
951 | * Note: we are here releasing the reference of &iommu_pdev->dev, which | |
952 | * is mc->dev. Although some functions in tegra_smmu_ops may keep using | |
953 | * its private data beyond this point, it's still safe to do so because | |
954 | * the SMMU parent device is the same as the MC, so the reference count | |
955 | * isn't strictly necessary. | |
956 | */ | |
957 | put_device(&iommu_pdev->dev); | |
958 | ||
959 | dev_iommu_priv_set(dev, mc->smmu); | |
960 | ||
7f4c9176 TR |
961 | return iommu_fwspec_add_ids(dev, &id, 1); |
962 | } | |
963 | ||
89184651 | 964 | static const struct iommu_ops tegra_smmu_ops = { |
d5f1a81c | 965 | .domain_alloc = tegra_smmu_domain_alloc, |
b287ba73 | 966 | .probe_device = tegra_smmu_probe_device, |
7f4c9176 | 967 | .device_group = tegra_smmu_device_group, |
7f4c9176 | 968 | .of_xlate = tegra_smmu_of_xlate, |
89184651 | 969 | .pgsize_bitmap = SZ_4K, |
9a630a4b LB |
970 | .default_domain_ops = &(const struct iommu_domain_ops) { |
971 | .attach_dev = tegra_smmu_attach_dev, | |
972 | .detach_dev = tegra_smmu_detach_dev, | |
973 | .map = tegra_smmu_map, | |
974 | .unmap = tegra_smmu_unmap, | |
975 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
976 | .free = tegra_smmu_domain_free, | |
977 | } | |
89184651 | 978 | }; |
7a31f6f4 | 979 | |
89184651 TR |
980 | static void tegra_smmu_ahb_enable(void) |
981 | { | |
982 | static const struct of_device_id ahb_match[] = { | |
983 | { .compatible = "nvidia,tegra30-ahb", }, | |
984 | { } | |
985 | }; | |
986 | struct device_node *ahb; | |
7a31f6f4 | 987 | |
89184651 TR |
988 | ahb = of_find_matching_node(NULL, ahb_match); |
989 | if (ahb) { | |
990 | tegra_ahb_enable_smmu(ahb); | |
991 | of_node_put(ahb); | |
7a31f6f4 | 992 | } |
89184651 | 993 | } |
7a31f6f4 | 994 | |
d1313e78 TR |
995 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
996 | { | |
997 | struct tegra_smmu *smmu = s->private; | |
998 | unsigned int i; | |
999 | u32 value; | |
1000 | ||
1001 | seq_printf(s, "swgroup enabled ASID\n"); | |
1002 | seq_printf(s, "------------------------\n"); | |
1003 | ||
1004 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
1005 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
1006 | const char *status; | |
1007 | unsigned int asid; | |
1008 | ||
1009 | value = smmu_readl(smmu, group->reg); | |
1010 | ||
1011 | if (value & SMMU_ASID_ENABLE) | |
1012 | status = "yes"; | |
1013 | else | |
1014 | status = "no"; | |
1015 | ||
1016 | asid = value & SMMU_ASID_MASK; | |
1017 | ||
1018 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
1019 | asid); | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
062e52a5 | 1025 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups); |
d1313e78 TR |
1026 | |
1027 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
1028 | { | |
1029 | struct tegra_smmu *smmu = s->private; | |
1030 | unsigned int i; | |
1031 | u32 value; | |
1032 | ||
1033 | seq_printf(s, "client enabled\n"); | |
1034 | seq_printf(s, "--------------------\n"); | |
1035 | ||
1036 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
1037 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
1038 | const char *status; | |
1039 | ||
4f1ac76e | 1040 | value = smmu_readl(smmu, client->regs.smmu.reg); |
d1313e78 | 1041 | |
4f1ac76e | 1042 | if (value & BIT(client->regs.smmu.bit)) |
d1313e78 TR |
1043 | status = "yes"; |
1044 | else | |
1045 | status = "no"; | |
1046 | ||
1047 | seq_printf(s, "%-12s %s\n", client->name, status); | |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
062e52a5 | 1053 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients); |
d1313e78 TR |
1054 | |
1055 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
1056 | { | |
1057 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
1058 | if (!smmu->debugfs) | |
1059 | return; | |
1060 | ||
1061 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
1062 | &tegra_smmu_swgroups_fops); | |
1063 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
1064 | &tegra_smmu_clients_fops); | |
1065 | } | |
1066 | ||
1067 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
1068 | { | |
1069 | debugfs_remove_recursive(smmu->debugfs); | |
1070 | } | |
1071 | ||
89184651 TR |
1072 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
1073 | const struct tegra_smmu_soc *soc, | |
1074 | struct tegra_mc *mc) | |
1075 | { | |
1076 | struct tegra_smmu *smmu; | |
89184651 TR |
1077 | u32 value; |
1078 | int err; | |
7a31f6f4 | 1079 | |
89184651 TR |
1080 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
1081 | if (!smmu) | |
1082 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 1083 | |
765a9d1d NC |
1084 | /* |
1085 | * This is a bit of a hack. Ideally we'd want to simply return this | |
48a7c508 RM |
1086 | * value. However iommu_device_register() will attempt to add |
1087 | * all devices to the IOMMU before we get that far. In order | |
765a9d1d NC |
1088 | * not to rely on global variables to track the IOMMU instance, we |
1089 | * set it here so that it can be looked up from the .probe_device() | |
1090 | * callback via the IOMMU device's .drvdata field. | |
1091 | */ | |
1092 | mc->smmu = smmu; | |
1093 | ||
89374244 | 1094 | smmu->asids = devm_bitmap_zalloc(dev, soc->num_asids, GFP_KERNEL); |
89184651 TR |
1095 | if (!smmu->asids) |
1096 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 1097 | |
7f4c9176 | 1098 | INIT_LIST_HEAD(&smmu->groups); |
89184651 | 1099 | mutex_init(&smmu->lock); |
7a31f6f4 | 1100 | |
89184651 TR |
1101 | smmu->regs = mc->regs; |
1102 | smmu->soc = soc; | |
1103 | smmu->dev = dev; | |
1104 | smmu->mc = mc; | |
7a31f6f4 | 1105 | |
82fa58e8 NC |
1106 | smmu->pfn_mask = |
1107 | BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; | |
804cb54c TR |
1108 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", |
1109 | mc->soc->num_address_bits, smmu->pfn_mask); | |
d5c152c3 | 1110 | smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; |
11cec15b TR |
1111 | dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, |
1112 | smmu->tlb_mask); | |
804cb54c | 1113 | |
89184651 | 1114 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 1115 | |
89184651 TR |
1116 | if (soc->supports_request_limit) |
1117 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 1118 | |
89184651 | 1119 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 1120 | |
89184651 | 1121 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
11cec15b | 1122 | SMMU_TLB_CONFIG_ACTIVE_LINES(smmu); |
7a31f6f4 | 1123 | |
89184651 TR |
1124 | if (soc->supports_round_robin_arbitration) |
1125 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 1126 | |
89184651 | 1127 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 1128 | |
b8fe0382 | 1129 | smmu_flush_ptc_all(smmu); |
89184651 TR |
1130 | smmu_flush_tlb(smmu); |
1131 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
1132 | smmu_flush(smmu); | |
1133 | ||
1134 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 1135 | |
0b480e44 JR |
1136 | err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev)); |
1137 | if (err) | |
1138 | return ERR_PTR(err); | |
1139 | ||
2d471b20 | 1140 | err = iommu_device_register(&smmu->iommu, &tegra_smmu_ops, dev); |
48a7c508 RM |
1141 | if (err) { |
1142 | iommu_device_sysfs_remove(&smmu->iommu); | |
1143 | return ERR_PTR(err); | |
1144 | } | |
96302d89 | 1145 | |
d1313e78 TR |
1146 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1147 | tegra_smmu_debugfs_init(smmu); | |
1148 | ||
89184651 TR |
1149 | return smmu; |
1150 | } | |
d1313e78 TR |
1151 | |
1152 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
1153 | { | |
0b480e44 JR |
1154 | iommu_device_unregister(&smmu->iommu); |
1155 | iommu_device_sysfs_remove(&smmu->iommu); | |
1156 | ||
d1313e78 TR |
1157 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1158 | tegra_smmu_debugfs_exit(smmu); | |
1159 | } |