[linux-2.6-block.git] / drivers / iommu / sprd-iommu.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Unisoc IOMMU driver
 *
 * Copyright (C) 2020 Unisoc, Inc.
 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/iommu.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define SPRD_IOMMU_PAGE_SHIFT	12
#define SPRD_IOMMU_PAGE_SIZE	SZ_4K

#define SPRD_EX_CFG		0x0
#define SPRD_IOMMU_VAOR_BYPASS	BIT(4)
#define SPRD_IOMMU_GATE_EN	BIT(1)
#define SPRD_IOMMU_EN		BIT(0)
#define SPRD_EX_UPDATE		0x4
#define SPRD_EX_FIRST_VPN	0x8
#define SPRD_EX_VPN_RANGE	0xc
#define SPRD_EX_FIRST_PPN	0x10
#define SPRD_EX_DEFAULT_PPN	0x14

#define SPRD_IOMMU_VERSION	0x0
#define SPRD_VERSION_MASK	GENMASK(15, 8)
#define SPRD_VERSION_SHIFT	0x8
#define SPRD_VAU_CFG		0x4
#define SPRD_VAU_UPDATE		0x8
#define SPRD_VAU_AUTH_CFG	0xc
#define SPRD_VAU_FIRST_PPN	0x10
#define SPRD_VAU_DEFAULT_PPN_RD	0x14
#define SPRD_VAU_DEFAULT_PPN_WR	0x18
#define SPRD_VAU_FIRST_VPN	0x1c
#define SPRD_VAU_VPN_RANGE	0x20

enum sprd_iommu_version {
	SPRD_IOMMU_EX,
	SPRD_IOMMU_VAU,
};

/*
 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
 * including hardware information and configuration, also driver data, etc
 *
 * @ver: sprd IOMMU IP version
 * @prot_page_va: protect page base virtual address
 * @prot_page_pa: protect page base physical address, data would be
 *		  written to here while translation fault
 * @base: mapped base address for accessing registers
 * @dev: pointer to basic device structure
 * @iommu: IOMMU core representation
 * @group: IOMMU group
 * @eb: gate clock which controls IOMMU access
 */
struct sprd_iommu_device {
	struct sprd_iommu_domain	*dom;
	enum sprd_iommu_version	ver;
	u32			*prot_page_va;
	dma_addr_t		prot_page_pa;
	void __iomem		*base;
	struct device		*dev;
	struct iommu_device	iommu;
	struct clk		*eb;
};

struct sprd_iommu_domain {
	spinlock_t		pgtlock; /* lock for page table */
	struct iommu_domain	domain;
	u32			*pgt_va; /* page table virtual address base */
	dma_addr_t		pgt_pa; /* page table physical address base */
	struct sprd_iommu_device	*sdev;
};

static const struct iommu_ops sprd_iommu_ops;

static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct sprd_iommu_domain, domain);
}

static inline void
sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
{
	writel_relaxed(val, sdev->base + reg);
}

static inline u32
sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
{
	return readl_relaxed(sdev->base + reg);
}

static inline void
sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
		  u32 mask, u32 shift, u32 val)
{
	u32 t = sprd_iommu_read(sdev, reg);

	t = (t & (~(mask << shift))) | ((val & mask) << shift);
	sprd_iommu_write(sdev, reg, t);
}

static inline int
sprd_iommu_get_version(struct sprd_iommu_device *sdev)
{
	int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
		   SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;

	switch (ver) {
	case SPRD_IOMMU_EX:
	case SPRD_IOMMU_VAU:
		return ver;
	default:
		return -EINVAL;
	}
}

static size_t
sprd_iommu_pgt_size(struct iommu_domain *domain)
{
	return ((domain->geometry.aperture_end -
		 domain->geometry.aperture_start + 1) >>
		SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
}

static struct iommu_domain *sprd_iommu_domain_alloc_paging(struct device *dev)
{
	struct sprd_iommu_domain *dom;

	dom = kzalloc(sizeof(*dom), GFP_KERNEL);
	if (!dom)
		return NULL;

	spin_lock_init(&dom->pgtlock);

	dom->domain.geometry.aperture_start = 0;
	dom->domain.geometry.aperture_end = SZ_256M - 1;
	dom->domain.geometry.force_aperture = true;

	return &dom->domain;
}

static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
{
	struct sprd_iommu_device *sdev = dom->sdev;
	u32 val;
	unsigned int reg;

	if (sdev->ver == SPRD_IOMMU_EX)
		reg = SPRD_EX_FIRST_VPN;
	else
		reg = SPRD_VAU_FIRST_VPN;

	val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
	sprd_iommu_write(sdev, reg, val);
}

static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
{
	struct sprd_iommu_device *sdev = dom->sdev;
	u32 val;
	unsigned int reg;

	if (sdev->ver == SPRD_IOMMU_EX)
		reg = SPRD_EX_VPN_RANGE;
	else
		reg = SPRD_VAU_VPN_RANGE;

	val = (dom->domain.geometry.aperture_end -
	       dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
	sprd_iommu_write(sdev, reg, val);
}

static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
{
	u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
	struct sprd_iommu_device *sdev = dom->sdev;
	unsigned int reg;

	if (sdev->ver == SPRD_IOMMU_EX)
		reg = SPRD_EX_FIRST_PPN;
	else
		reg = SPRD_VAU_FIRST_PPN;

	sprd_iommu_write(sdev, reg, val);
}

static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
{
	u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;

	if (sdev->ver == SPRD_IOMMU_EX) {
		sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
	} else if (sdev->ver == SPRD_IOMMU_VAU) {
		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
		sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
	}
}

static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
{
	unsigned int reg_cfg;
	u32 mask, val;

	if (sdev->ver == SPRD_IOMMU_EX)
		reg_cfg = SPRD_EX_CFG;
	else
		reg_cfg = SPRD_VAU_CFG;

	mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN;
	val = en ? mask : 0;
	sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
}

static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
{
	size_t pgt_size;

	/* Nothing need to do if the domain hasn't been attached */
	if (!dom->sdev)
		return;

	pgt_size = sprd_iommu_pgt_size(&dom->domain);
	dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
	dom->sdev = NULL;
	sprd_iommu_hw_en(dom->sdev, false);
}

static void sprd_iommu_domain_free(struct iommu_domain *domain)
{
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);

	sprd_iommu_cleanup(dom);
	kfree(dom);
}

static int sprd_iommu_attach_device(struct iommu_domain *domain,
				    struct device *dev)
{
	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	size_t pgt_size = sprd_iommu_pgt_size(domain);

	/* The device is attached to this domain */
	if (sdev->dom == dom)
		return 0;

	/* The first time that domain is attaching to a device */
	if (!dom->pgt_va) {
		dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
		if (!dom->pgt_va)
			return -ENOMEM;

		dom->sdev = sdev;
	}

	sdev->dom = dom;

	/*
	 * One sprd IOMMU serves one client device only, disabled it before
	 * configure mapping table to avoid access conflict in case other
	 * mapping table is stored in.
	 */
	sprd_iommu_hw_en(sdev, false);
	sprd_iommu_first_ppn(dom);
	sprd_iommu_first_vpn(dom);
	sprd_iommu_vpn_range(dom);
	sprd_iommu_default_ppn(sdev);
	sprd_iommu_hw_en(sdev, true);

	return 0;
}

static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
			  phys_addr_t paddr, size_t pgsize, size_t pgcount,
			  int prot, gfp_t gfp, size_t *mapped)
{
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
	unsigned long flags;
	unsigned int i;
	u32 *pgt_base_iova;
	u32 pabase = (u32)paddr;
	unsigned long start = domain->geometry.aperture_start;
	unsigned long end = domain->geometry.aperture_end;

	if (!dom->sdev) {
		pr_err("No sprd_iommu_device attached to the domain\n");
		return -EINVAL;
	}

	if (iova < start || (iova + size) > (end + 1)) {
		dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
			iova, size);
		return -EINVAL;
	}

	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);

	spin_lock_irqsave(&dom->pgtlock, flags);
	for (i = 0; i < pgcount; i++) {
		pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
		pabase += SPRD_IOMMU_PAGE_SIZE;
	}
	spin_unlock_irqrestore(&dom->pgtlock, flags);

	*mapped = size;
	return 0;
}

static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
			       size_t pgsize, size_t pgcount,
			       struct iommu_iotlb_gather *iotlb_gather)
{
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	unsigned long flags;
	u32 *pgt_base_iova;
	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
	unsigned long start = domain->geometry.aperture_start;
	unsigned long end = domain->geometry.aperture_end;

	if (iova < start || (iova + size) > (end + 1))
		return 0;

	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);

	spin_lock_irqsave(&dom->pgtlock, flags);
	memset(pgt_base_iova, 0, pgcount * sizeof(u32));
	spin_unlock_irqrestore(&dom->pgtlock, flags);

	return size;
}

static int sprd_iommu_sync_map(struct iommu_domain *domain,
			       unsigned long iova, size_t size)
{
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	unsigned int reg;

	if (dom->sdev->ver == SPRD_IOMMU_EX)
		reg = SPRD_EX_UPDATE;
	else
		reg = SPRD_VAU_UPDATE;

	/* clear IOMMU TLB buffer after page table updated */
	sprd_iommu_write(dom->sdev, reg, 0xffffffff);
	return 0;
}

static void sprd_iommu_sync(struct iommu_domain *domain,
			    struct iommu_iotlb_gather *iotlb_gather)
{
	sprd_iommu_sync_map(domain, 0, 0);
}

static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
					   dma_addr_t iova)
{
	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	unsigned long flags;
	phys_addr_t pa;
	unsigned long start = domain->geometry.aperture_start;
	unsigned long end = domain->geometry.aperture_end;

	if (WARN_ON(iova < start || iova > end))
		return 0;

	spin_lock_irqsave(&dom->pgtlock, flags);
	pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
	pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
	spin_unlock_irqrestore(&dom->pgtlock, flags);

	return pa;
}

static struct iommu_device *sprd_iommu_probe_device(struct device *dev)
{
	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);

	return &sdev->iommu;
}

static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
{
	struct platform_device *pdev;

	if (!dev_iommu_priv_get(dev)) {
		pdev = of_find_device_by_node(args->np);
		dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
		platform_device_put(pdev);
	}

	return 0;
}


static const struct iommu_ops sprd_iommu_ops = {
	.domain_alloc_paging = sprd_iommu_domain_alloc_paging,
	.probe_device	= sprd_iommu_probe_device,
	.device_group	= generic_single_device_group,
	.of_xlate	= sprd_iommu_of_xlate,
	.pgsize_bitmap	= SPRD_IOMMU_PAGE_SIZE,
	.owner		= THIS_MODULE,
	.default_domain_ops = &(const struct iommu_domain_ops) {
		.attach_dev	= sprd_iommu_attach_device,
		.map_pages	= sprd_iommu_map,
		.unmap_pages	= sprd_iommu_unmap,
		.iotlb_sync_map	= sprd_iommu_sync_map,
		.iotlb_sync	= sprd_iommu_sync,
		.iova_to_phys	= sprd_iommu_iova_to_phys,
		.free		= sprd_iommu_domain_free,
	}
};

static const struct of_device_id sprd_iommu_of_match[] = {
	{ .compatible = "sprd,iommu-v1" },
	{ },
};
MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);

/*
 * Clock is not required, access to some of IOMMUs is controlled by gate
 * clk, enabled clocks for that kind of IOMMUs before accessing.
 * Return 0 for success or no clocks found.
 */
static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
{
	struct clk *eb;

	eb = devm_clk_get_optional(sdev->dev, NULL);
	if (!eb)
		return 0;

	if (IS_ERR(eb))
		return PTR_ERR(eb);

	sdev->eb = eb;
	return clk_prepare_enable(eb);
}

static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
{
	if (sdev->eb)
		clk_disable_unprepare(sdev->eb);
}

static int sprd_iommu_probe(struct platform_device *pdev)
{
	struct sprd_iommu_device *sdev;
	struct device *dev = &pdev->dev;
	void __iomem *base;
	int ret;

	sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
	if (!sdev)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base)) {
		dev_err(dev, "Failed to get ioremap resource.\n");
		return PTR_ERR(base);
	}
	sdev->base = base;

	sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
						&sdev->prot_page_pa, GFP_KERNEL);
	if (!sdev->prot_page_va)
		return -ENOMEM;

	platform_set_drvdata(pdev, sdev);
	sdev->dev = dev;

	ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
	if (ret)
		goto free_page;

	ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
	if (ret)
		goto remove_sysfs;

	ret = sprd_iommu_clk_enable(sdev);
	if (ret)
		goto unregister_iommu;

	ret = sprd_iommu_get_version(sdev);
	if (ret < 0) {
		dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
		goto disable_clk;
	}
	sdev->ver = ret;

	return 0;

disable_clk:
	sprd_iommu_clk_disable(sdev);
unregister_iommu:
	iommu_device_unregister(&sdev->iommu);
remove_sysfs:
	iommu_device_sysfs_remove(&sdev->iommu);
free_page:
	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
	return ret;
}

static void sprd_iommu_remove(struct platform_device *pdev)
{
	struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);

	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);

	platform_set_drvdata(pdev, NULL);
	iommu_device_sysfs_remove(&sdev->iommu);
	iommu_device_unregister(&sdev->iommu);
}

static struct platform_driver sprd_iommu_driver = {
	.driver	= {
		.name		= "sprd-iommu",
		.of_match_table	= sprd_iommu_of_match,
		.suppress_bind_attrs = true,
	},
	.probe	= sprd_iommu_probe,
	.remove_new = sprd_iommu_remove,
};
module_platform_driver(sprd_iommu_driver);

MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
MODULE_ALIAS("platform:sprd-iommu");
MODULE_LICENSE("GPL");
Commit	Line	Data
b23e4fc4 CZ	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Unisoc IOMMU driver
	4	*
	5	* Copyright (C) 2020 Unisoc, Inc.
	6	* Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/device.h>
b23e4fc4 CZ	11	#include <linux/dma-mapping.h>
	12	#include <linux/errno.h>
	13	#include <linux/iommu.h>
	14	#include <linux/mfd/syscon.h>
	15	#include <linux/module.h>
	16	#include <linux/of_platform.h>
d477f603	17	#include <linux/platform_device.h>
b23e4fc4 CZ	18	#include <linux/regmap.h>
	19	#include <linux/slab.h>
	20
	21	#define SPRD_IOMMU_PAGE_SHIFT 12
	22	#define SPRD_IOMMU_PAGE_SIZE SZ_4K
	23
	24	#define SPRD_EX_CFG 0x0
	25	#define SPRD_IOMMU_VAOR_BYPASS BIT(4)
	26	#define SPRD_IOMMU_GATE_EN BIT(1)
	27	#define SPRD_IOMMU_EN BIT(0)
	28	#define SPRD_EX_UPDATE 0x4
	29	#define SPRD_EX_FIRST_VPN 0x8
	30	#define SPRD_EX_VPN_RANGE 0xc
	31	#define SPRD_EX_FIRST_PPN 0x10
	32	#define SPRD_EX_DEFAULT_PPN 0x14
	33
	34	#define SPRD_IOMMU_VERSION 0x0
	35	#define SPRD_VERSION_MASK GENMASK(15, 8)
	36	#define SPRD_VERSION_SHIFT 0x8
	37	#define SPRD_VAU_CFG 0x4
	38	#define SPRD_VAU_UPDATE 0x8
	39	#define SPRD_VAU_AUTH_CFG 0xc
	40	#define SPRD_VAU_FIRST_PPN 0x10
	41	#define SPRD_VAU_DEFAULT_PPN_RD 0x14
	42	#define SPRD_VAU_DEFAULT_PPN_WR 0x18
	43	#define SPRD_VAU_FIRST_VPN 0x1c
	44	#define SPRD_VAU_VPN_RANGE 0x20
	45
	46	enum sprd_iommu_version {
	47	SPRD_IOMMU_EX,
	48	SPRD_IOMMU_VAU,
	49	};
	50
	51	/*
	52	* struct sprd_iommu_device - high-level sprd IOMMU device representation,
	53	* including hardware information and configuration, also driver data, etc
	54	*
	55	* @ver: sprd IOMMU IP version
	56	* @prot_page_va: protect page base virtual address
	57	* @prot_page_pa: protect page base physical address, data would be
	58	* written to here while translation fault
	59	* @base: mapped base address for accessing registers
	60	* @dev: pointer to basic device structure
	61	* @iommu: IOMMU core representation
	62	* @group: IOMMU group
	63	* @eb: gate clock which controls IOMMU access
	64	*/
	65	struct sprd_iommu_device {
816c698c	66	struct sprd_iommu_domain *dom;
b23e4fc4 CZ	67	enum sprd_iommu_version ver;
	68	u32 *prot_page_va;
	69	dma_addr_t prot_page_pa;
	70	void __iomem *base;
	71	struct device *dev;
	72	struct iommu_device iommu;
b23e4fc4 CZ	73	struct clk *eb;
	74	};
	75
	76	struct sprd_iommu_domain {
	77	spinlock_t pgtlock; /* lock for page table */
	78	struct iommu_domain domain;
	79	u32 pgt_va; / page table virtual address base */
	80	dma_addr_t pgt_pa; /* page table physical address base */
	81	struct sprd_iommu_device *sdev;
	82	};
	83
	84	static const struct iommu_ops sprd_iommu_ops;
	85
	86	static struct sprd_iommu_domain to_sprd_domain(struct iommu_domain dom)
	87	{
	88	return container_of(dom, struct sprd_iommu_domain, domain);
	89	}
	90
	91	static inline void
	92	sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
	93	{
	94	writel_relaxed(val, sdev->base + reg);
	95	}
	96
	97	static inline u32
	98	sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
	99	{
	100	return readl_relaxed(sdev->base + reg);
	101	}
	102
	103	static inline void
	104	sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
	105	u32 mask, u32 shift, u32 val)
	106	{
	107	u32 t = sprd_iommu_read(sdev, reg);
	108
	109	t = (t & (~(mask << shift))) \| ((val & mask) << shift);
	110	sprd_iommu_write(sdev, reg, t);
	111	}
	112
	113	static inline int
	114	sprd_iommu_get_version(struct sprd_iommu_device *sdev)
	115	{
	116	int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
	117	SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;
	118
	119	switch (ver) {
	120	case SPRD_IOMMU_EX:
	121	case SPRD_IOMMU_VAU:
	122	return ver;
	123	default:
	124	return -EINVAL;
	125	}
	126	}
	127
	128	static size_t
	129	sprd_iommu_pgt_size(struct iommu_domain *domain)
	130	{
	131	return ((domain->geometry.aperture_end -
	132	domain->geometry.aperture_start + 1) >>
	133	SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
	134	}
	135
3529375e	136	static struct iommu_domain sprd_iommu_domain_alloc_paging(struct device dev)
b23e4fc4 CZ	137	{
	138	struct sprd_iommu_domain *dom;
	139
b23e4fc4 CZ	140	dom = kzalloc(sizeof(*dom), GFP_KERNEL);
	141	if (!dom)
	142	return NULL;
	143
b23e4fc4 CZ	144	spin_lock_init(&dom->pgtlock);
	145
	146	dom->domain.geometry.aperture_start = 0;
	147	dom->domain.geometry.aperture_end = SZ_256M - 1;
d48a5128	148	dom->domain.geometry.force_aperture = true;
b23e4fc4 CZ	149
	150	return &dom->domain;
	151	}
	152
b23e4fc4 CZ	153	static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
	154	{
	155	struct sprd_iommu_device *sdev = dom->sdev;
	156	u32 val;
	157	unsigned int reg;
	158
	159	if (sdev->ver == SPRD_IOMMU_EX)
	160	reg = SPRD_EX_FIRST_VPN;
	161	else
	162	reg = SPRD_VAU_FIRST_VPN;
	163
	164	val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
	165	sprd_iommu_write(sdev, reg, val);
	166	}
	167
	168	static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
	169	{
	170	struct sprd_iommu_device *sdev = dom->sdev;
	171	u32 val;
	172	unsigned int reg;
	173
	174	if (sdev->ver == SPRD_IOMMU_EX)
	175	reg = SPRD_EX_VPN_RANGE;
	176	else
	177	reg = SPRD_VAU_VPN_RANGE;
	178
	179	val = (dom->domain.geometry.aperture_end -
	180	dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
	181	sprd_iommu_write(sdev, reg, val);
	182	}
	183
	184	static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
	185	{
	186	u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
	187	struct sprd_iommu_device *sdev = dom->sdev;
	188	unsigned int reg;
	189
	190	if (sdev->ver == SPRD_IOMMU_EX)
	191	reg = SPRD_EX_FIRST_PPN;
	192	else
	193	reg = SPRD_VAU_FIRST_PPN;
	194
	195	sprd_iommu_write(sdev, reg, val);
	196	}
	197
	198	static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
	199	{
	200	u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;
	201
	202	if (sdev->ver == SPRD_IOMMU_EX) {
	203	sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
	204	} else if (sdev->ver == SPRD_IOMMU_VAU) {
	205	sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
	206	sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
	207	}
	208	}
	209
	210	static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
	211	{
	212	unsigned int reg_cfg;
	213	u32 mask, val;
	214
	215	if (sdev->ver == SPRD_IOMMU_EX)
	216	reg_cfg = SPRD_EX_CFG;
217	else
218	reg_cfg = SPRD_VAU_CFG;
219
220	mask = SPRD_IOMMU_EN \| SPRD_IOMMU_GATE_EN;
221	val = en ? mask : 0;
222	sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
223	}
224
9afea573 CZ	225	static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
	226	{
	227	size_t pgt_size;
	228
	229	/* Nothing need to do if the domain hasn't been attached */
	230	if (!dom->sdev)
	231	return;
	232
	233	pgt_size = sprd_iommu_pgt_size(&dom->domain);
	234	dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
	235	dom->sdev = NULL;
	236	sprd_iommu_hw_en(dom->sdev, false);
	237	}
	238
	239	static void sprd_iommu_domain_free(struct iommu_domain *domain)
	240	{
	241	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	242
	243	sprd_iommu_cleanup(dom);
	244	kfree(dom);
	245	}
	246
b23e4fc4 CZ	247	static int sprd_iommu_attach_device(struct iommu_domain *domain,
	248	struct device *dev)
	249	{
	250	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
	251	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	252	size_t pgt_size = sprd_iommu_pgt_size(domain);
	253
816c698c CZ	254	/* The device is attached to this domain */
	255	if (sdev->dom == dom)
	256	return 0;
b23e4fc4	257
816c698c CZ	258	/* The first time that domain is attaching to a device */
	259	if (!dom->pgt_va) {
	260	dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
	261	if (!dom->pgt_va)
	262	return -ENOMEM;
b23e4fc4	263
816c698c CZ	264	dom->sdev = sdev;
816c698c CZ	265	}
b23e4fc4	266
816c698c	267	sdev->dom = dom;
b23e4fc4	268
816c698c CZ	269	/*
	270	* One sprd IOMMU serves one client device only, disabled it before
	271	* configure mapping table to avoid access conflict in case other
	272	* mapping table is stored in.
	273	*/
	274	sprd_iommu_hw_en(sdev, false);
b23e4fc4 CZ	275	sprd_iommu_first_ppn(dom);
	276	sprd_iommu_first_vpn(dom);
	277	sprd_iommu_vpn_range(dom);
	278	sprd_iommu_default_ppn(sdev);
	279	sprd_iommu_hw_en(sdev, true);
	280
	281	return 0;
	282	}
	283
b23e4fc4	284	static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
a05d5857 RM	285	phys_addr_t paddr, size_t pgsize, size_t pgcount,
a05d5857 RM	286	int prot, gfp_t gfp, size_t *mapped)
b23e4fc4 CZ	287	{
b23e4fc4 CZ	288	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
a05d5857	289	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
b23e4fc4 CZ	290	unsigned long flags;
	291	unsigned int i;
	292	u32 *pgt_base_iova;
	293	u32 pabase = (u32)paddr;
	294	unsigned long start = domain->geometry.aperture_start;
	295	unsigned long end = domain->geometry.aperture_end;
	296
	297	if (!dom->sdev) {
	298	pr_err("No sprd_iommu_device attached to the domain\n");
	299	return -EINVAL;
	300	}
	301
	302	if (iova < start \|\| (iova + size) > (end + 1)) {
0bb868e1	303	dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
b23e4fc4 CZ	304	iova, size);
	305	return -EINVAL;
	306	}
	307
	308	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
	309
	310	spin_lock_irqsave(&dom->pgtlock, flags);
a05d5857	311	for (i = 0; i < pgcount; i++) {
b23e4fc4 CZ	312	pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
	313	pabase += SPRD_IOMMU_PAGE_SIZE;
	314	}
	315	spin_unlock_irqrestore(&dom->pgtlock, flags);
	316
a05d5857	317	*mapped = size;
b23e4fc4 CZ	318	return 0;
	319	}
	320
	321	static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
a05d5857 RM	322	size_t pgsize, size_t pgcount,
a05d5857 RM	323	struct iommu_iotlb_gather *iotlb_gather)
b23e4fc4 CZ	324	{
	325	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	326	unsigned long flags;
	327	u32 *pgt_base_iova;
a05d5857	328	size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
b23e4fc4 CZ	329	unsigned long start = domain->geometry.aperture_start;
	330	unsigned long end = domain->geometry.aperture_end;
	331
	332	if (iova < start \|\| (iova + size) > (end + 1))
a05d5857	333	return 0;
b23e4fc4 CZ	334
	335	pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
	336
	337	spin_lock_irqsave(&dom->pgtlock, flags);
a05d5857	338	memset(pgt_base_iova, 0, pgcount * sizeof(u32));
b23e4fc4 CZ	339	spin_unlock_irqrestore(&dom->pgtlock, flags);
b23e4fc4 CZ	340
a05d5857	341	return size;
b23e4fc4 CZ	342	}
b23e4fc4 CZ	343
fa4c4507 NS	344	static int sprd_iommu_sync_map(struct iommu_domain *domain,
fa4c4507 NS	345	unsigned long iova, size_t size)
b23e4fc4 CZ	346	{
	347	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	348	unsigned int reg;
	349
	350	if (dom->sdev->ver == SPRD_IOMMU_EX)
	351	reg = SPRD_EX_UPDATE;
	352	else
	353	reg = SPRD_VAU_UPDATE;
	354
	355	/* clear IOMMU TLB buffer after page table updated */
	356	sprd_iommu_write(dom->sdev, reg, 0xffffffff);
fa4c4507	357	return 0;
b23e4fc4 CZ	358	}
	359
	360	static void sprd_iommu_sync(struct iommu_domain *domain,
	361	struct iommu_iotlb_gather *iotlb_gather)
	362	{
	363	sprd_iommu_sync_map(domain, 0, 0);
	364	}
	365
	366	static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
	367	dma_addr_t iova)
	368	{
	369	struct sprd_iommu_domain *dom = to_sprd_domain(domain);
	370	unsigned long flags;
	371	phys_addr_t pa;
	372	unsigned long start = domain->geometry.aperture_start;
	373	unsigned long end = domain->geometry.aperture_end;
	374
	375	if (WARN_ON(iova < start \|\| iova > end))
	376	return 0;
	377
	378	spin_lock_irqsave(&dom->pgtlock, flags);
	379	pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
	380	pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
	381	spin_unlock_irqrestore(&dom->pgtlock, flags);
	382
	383	return pa;
	384	}
	385
	386	static struct iommu_device sprd_iommu_probe_device(struct device dev)
	387	{
e7080665	388	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
b23e4fc4 CZ	389
	390	return &sdev->iommu;
	391	}
	392
b23e4fc4 CZ	393	static int sprd_iommu_of_xlate(struct device dev, struct of_phandle_args args)
	394	{
	395	struct platform_device *pdev;
	396
	397	if (!dev_iommu_priv_get(dev)) {
	398	pdev = of_find_device_by_node(args->np);
	399	dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
	400	platform_device_put(pdev);
	401	}
	402
	403	return 0;
	404	}
	405
	406
	407	static const struct iommu_ops sprd_iommu_ops = {
3529375e	408	.domain_alloc_paging = sprd_iommu_domain_alloc_paging,
b23e4fc4	409	.probe_device = sprd_iommu_probe_device,
a62cafe1	410	.device_group = generic_single_device_group,
b23e4fc4	411	.of_xlate = sprd_iommu_of_xlate,
a05d5857	412	.pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE,
c0aec668	413	.owner = THIS_MODULE,
9a630a4b LB	414	.default_domain_ops = &(const struct iommu_domain_ops) {
9a630a4b LB	415	.attach_dev = sprd_iommu_attach_device,
a05d5857 RM	416	.map_pages = sprd_iommu_map,
a05d5857 RM	417	.unmap_pages = sprd_iommu_unmap,
9a630a4b LB	418	.iotlb_sync_map = sprd_iommu_sync_map,
	419	.iotlb_sync = sprd_iommu_sync,
	420	.iova_to_phys = sprd_iommu_iova_to_phys,
	421	.free = sprd_iommu_domain_free,
	422	}
b23e4fc4 CZ	423	};
	424
	425	static const struct of_device_id sprd_iommu_of_match[] = {
	426	{ .compatible = "sprd,iommu-v1" },
	427	{ },
	428	};
	429	MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);
	430
	431	/*
	432	* Clock is not required, access to some of IOMMUs is controlled by gate
	433	* clk, enabled clocks for that kind of IOMMUs before accessing.
	434	* Return 0 for success or no clocks found.
	435	*/
	436	static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
	437	{
	438	struct clk *eb;
	439
a56af062	440	eb = devm_clk_get_optional(sdev->dev, NULL);
b23e4fc4 CZ	441	if (!eb)
	442	return 0;
	443
	444	if (IS_ERR(eb))
	445	return PTR_ERR(eb);
	446
	447	sdev->eb = eb;
	448	return clk_prepare_enable(eb);
	449	}
	450
	451	static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
	452	{
	453	if (sdev->eb)
	454	clk_disable_unprepare(sdev->eb);
	455	}
	456
	457	static int sprd_iommu_probe(struct platform_device *pdev)
	458	{
	459	struct sprd_iommu_device *sdev;
	460	struct device *dev = &pdev->dev;
	461	void __iomem *base;
	462	int ret;
	463
	464	sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
	465	if (!sdev)
	466	return -ENOMEM;
	467
	468	base = devm_platform_ioremap_resource(pdev, 0);
	469	if (IS_ERR(base)) {
	470	dev_err(dev, "Failed to get ioremap resource.\n");
	471	return PTR_ERR(base);
	472	}
	473	sdev->base = base;
	474
	475	sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
	476	&sdev->prot_page_pa, GFP_KERNEL);
	477	if (!sdev->prot_page_va)
	478	return -ENOMEM;
	479
	480	platform_set_drvdata(pdev, sdev);
	481	sdev->dev = dev;
	482
b23e4fc4 CZ	483	ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
b23e4fc4 CZ	484	if (ret)
a62cafe1	485	goto free_page;
b23e4fc4	486
2d471b20	487	ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
b23e4fc4 CZ	488	if (ret)
	489	goto remove_sysfs;
	490
b23e4fc4 CZ	491	ret = sprd_iommu_clk_enable(sdev);
	492	if (ret)
	493	goto unregister_iommu;
	494
	495	ret = sprd_iommu_get_version(sdev);
	496	if (ret < 0) {
	497	dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
	498	goto disable_clk;
	499	}
	500	sdev->ver = ret;
	501
	502	return 0;
	503
	504	disable_clk:
	505	sprd_iommu_clk_disable(sdev);
	506	unregister_iommu:
	507	iommu_device_unregister(&sdev->iommu);
	508	remove_sysfs:
	509	iommu_device_sysfs_remove(&sdev->iommu);
b23e4fc4 CZ	510	free_page:
	511	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
	512	return ret;
	513	}
	514
421b6093	515	static void sprd_iommu_remove(struct platform_device *pdev)
b23e4fc4 CZ	516	{
	517	struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);
	518
	519	dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
	520
b23e4fc4 CZ	521	platform_set_drvdata(pdev, NULL);
	522	iommu_device_sysfs_remove(&sdev->iommu);
	523	iommu_device_unregister(&sdev->iommu);
b23e4fc4 CZ	524	}
	525
	526	static struct platform_driver sprd_iommu_driver = {
	527	.driver = {
	528	.name = "sprd-iommu",
	529	.of_match_table = sprd_iommu_of_match,
	530	.suppress_bind_attrs = true,
	531	},
	532	.probe = sprd_iommu_probe,
421b6093	533	.remove_new = sprd_iommu_remove,
b23e4fc4 CZ	534	};
	535	module_platform_driver(sprd_iommu_driver);
	536
	537	MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
	538	MODULE_ALIAS("platform:sprd-iommu");
	539	MODULE_LICENSE("GPL");