Commit | Line | Data |
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c68a2921 DK |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | */ | |
6 | ||
f2e3a5f5 | 7 | #include <linux/clk.h> |
c68a2921 DK |
8 | #include <linux/compiler.h> |
9 | #include <linux/delay.h> | |
10 | #include <linux/device.h> | |
4f0aba67 | 11 | #include <linux/dma-iommu.h> |
461a6946 | 12 | #include <linux/dma-mapping.h> |
c68a2921 DK |
13 | #include <linux/errno.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/iommu.h> | |
0416bf64 | 17 | #include <linux/iopoll.h> |
c68a2921 DK |
18 | #include <linux/list.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
5fd577c3 | 22 | #include <linux/of_iommu.h> |
c68a2921 DK |
23 | #include <linux/of_platform.h> |
24 | #include <linux/platform_device.h> | |
0f181d3c | 25 | #include <linux/pm_runtime.h> |
c68a2921 DK |
26 | #include <linux/slab.h> |
27 | #include <linux/spinlock.h> | |
28 | ||
29 | /** MMU register offsets */ | |
30 | #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ | |
31 | #define RK_MMU_STATUS 0x04 | |
32 | #define RK_MMU_COMMAND 0x08 | |
33 | #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ | |
34 | #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ | |
35 | #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ | |
36 | #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ | |
37 | #define RK_MMU_INT_MASK 0x1C /* IRQ enable */ | |
38 | #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ | |
39 | #define RK_MMU_AUTO_GATING 0x24 | |
40 | ||
41 | #define DTE_ADDR_DUMMY 0xCAFEBABE | |
0416bf64 TF |
42 | |
43 | #define RK_MMU_POLL_PERIOD_US 100 | |
44 | #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 | |
45 | #define RK_MMU_POLL_TIMEOUT_US 1000 | |
c68a2921 DK |
46 | |
47 | /* RK_MMU_STATUS fields */ | |
48 | #define RK_MMU_STATUS_PAGING_ENABLED BIT(0) | |
49 | #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) | |
50 | #define RK_MMU_STATUS_STALL_ACTIVE BIT(2) | |
51 | #define RK_MMU_STATUS_IDLE BIT(3) | |
52 | #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) | |
53 | #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) | |
54 | #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) | |
55 | ||
56 | /* RK_MMU_COMMAND command values */ | |
57 | #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ | |
58 | #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ | |
59 | #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ | |
60 | #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ | |
61 | #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ | |
62 | #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ | |
63 | #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ | |
64 | ||
65 | /* RK_MMU_INT_* register fields */ | |
66 | #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ | |
67 | #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ | |
68 | #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) | |
69 | ||
70 | #define NUM_DT_ENTRIES 1024 | |
71 | #define NUM_PT_ENTRIES 1024 | |
72 | ||
73 | #define SPAGE_ORDER 12 | |
74 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
75 | ||
76 | /* | |
77 | * Support mapping any size that fits in one page table: | |
78 | * 4 KiB to 4 MiB | |
79 | */ | |
80 | #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 | |
81 | ||
c68a2921 DK |
82 | struct rk_iommu_domain { |
83 | struct list_head iommus; | |
84 | u32 *dt; /* page directory table */ | |
4f0aba67 | 85 | dma_addr_t dt_dma; |
c68a2921 DK |
86 | spinlock_t iommus_lock; /* lock for iommus list */ |
87 | spinlock_t dt_lock; /* lock for modifying page directory table */ | |
bcd516a3 JR |
88 | |
89 | struct iommu_domain domain; | |
c68a2921 DK |
90 | }; |
91 | ||
f2e3a5f5 TF |
92 | /* list of clocks required by IOMMU */ |
93 | static const char * const rk_iommu_clocks[] = { | |
94 | "aclk", "iface", | |
95 | }; | |
96 | ||
c68a2921 DK |
97 | struct rk_iommu { |
98 | struct device *dev; | |
cd6438c5 Z |
99 | void __iomem **bases; |
100 | int num_mmu; | |
f2e3a5f5 TF |
101 | struct clk_bulk_data *clocks; |
102 | int num_clocks; | |
c3aa4742 | 103 | bool reset_disabled; |
c9d9f239 | 104 | struct iommu_device iommu; |
c68a2921 DK |
105 | struct list_head node; /* entry in rk_iommu_domain.iommus */ |
106 | struct iommu_domain *domain; /* domain to which iommu is attached */ | |
57c26957 | 107 | struct iommu_group *group; |
c68a2921 DK |
108 | }; |
109 | ||
5fd577c3 | 110 | struct rk_iommudata { |
0f181d3c | 111 | struct device_link *link; /* runtime PM link from IOMMU to master */ |
5fd577c3 JC |
112 | struct rk_iommu *iommu; |
113 | }; | |
114 | ||
9176a303 JC |
115 | static struct device *dma_dev; |
116 | ||
4f0aba67 SZ |
117 | static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, |
118 | unsigned int count) | |
c68a2921 | 119 | { |
4f0aba67 | 120 | size_t size = count * sizeof(u32); /* count of u32 entry */ |
c68a2921 | 121 | |
9176a303 | 122 | dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE); |
c68a2921 DK |
123 | } |
124 | ||
bcd516a3 JR |
125 | static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) |
126 | { | |
127 | return container_of(dom, struct rk_iommu_domain, domain); | |
128 | } | |
129 | ||
c68a2921 DK |
130 | /* |
131 | * The Rockchip rk3288 iommu uses a 2-level page table. | |
132 | * The first level is the "Directory Table" (DT). | |
133 | * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing | |
134 | * to a "Page Table". | |
135 | * The second level is the 1024 Page Tables (PT). | |
136 | * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to | |
137 | * a 4 KB page of physical memory. | |
138 | * | |
139 | * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). | |
140 | * Each iommu device has a MMU_DTE_ADDR register that contains the physical | |
141 | * address of the start of the DT page. | |
142 | * | |
143 | * The structure of the page table is as follows: | |
144 | * | |
145 | * DT | |
146 | * MMU_DTE_ADDR -> +-----+ | |
147 | * | | | |
148 | * +-----+ PT | |
149 | * | DTE | -> +-----+ | |
150 | * +-----+ | | Memory | |
151 | * | | +-----+ Page | |
152 | * | | | PTE | -> +-----+ | |
153 | * +-----+ +-----+ | | | |
154 | * | | | | | |
155 | * | | | | | |
156 | * +-----+ | | | |
157 | * | | | |
158 | * | | | |
159 | * +-----+ | |
160 | */ | |
161 | ||
162 | /* | |
163 | * Each DTE has a PT address and a valid bit: | |
164 | * +---------------------+-----------+-+ | |
165 | * | PT address | Reserved |V| | |
166 | * +---------------------+-----------+-+ | |
167 | * 31:12 - PT address (PTs always starts on a 4 KB boundary) | |
168 | * 11: 1 - Reserved | |
169 | * 0 - 1 if PT @ PT address is valid | |
170 | */ | |
171 | #define RK_DTE_PT_ADDRESS_MASK 0xfffff000 | |
172 | #define RK_DTE_PT_VALID BIT(0) | |
173 | ||
174 | static inline phys_addr_t rk_dte_pt_address(u32 dte) | |
175 | { | |
176 | return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; | |
177 | } | |
178 | ||
179 | static inline bool rk_dte_is_pt_valid(u32 dte) | |
180 | { | |
181 | return dte & RK_DTE_PT_VALID; | |
182 | } | |
183 | ||
4f0aba67 | 184 | static inline u32 rk_mk_dte(dma_addr_t pt_dma) |
c68a2921 | 185 | { |
4f0aba67 | 186 | return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; |
c68a2921 DK |
187 | } |
188 | ||
189 | /* | |
190 | * Each PTE has a Page address, some flags and a valid bit: | |
191 | * +---------------------+---+-------+-+ | |
192 | * | Page address |Rsv| Flags |V| | |
193 | * +---------------------+---+-------+-+ | |
194 | * 31:12 - Page address (Pages always start on a 4 KB boundary) | |
195 | * 11: 9 - Reserved | |
196 | * 8: 1 - Flags | |
197 | * 8 - Read allocate - allocate cache space on read misses | |
198 | * 7 - Read cache - enable cache & prefetch of data | |
199 | * 6 - Write buffer - enable delaying writes on their way to memory | |
200 | * 5 - Write allocate - allocate cache space on write misses | |
201 | * 4 - Write cache - different writes can be merged together | |
202 | * 3 - Override cache attributes | |
203 | * if 1, bits 4-8 control cache attributes | |
204 | * if 0, the system bus defaults are used | |
205 | * 2 - Writable | |
206 | * 1 - Readable | |
207 | * 0 - 1 if Page @ Page address is valid | |
208 | */ | |
209 | #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 | |
210 | #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe | |
211 | #define RK_PTE_PAGE_WRITABLE BIT(2) | |
212 | #define RK_PTE_PAGE_READABLE BIT(1) | |
213 | #define RK_PTE_PAGE_VALID BIT(0) | |
214 | ||
215 | static inline phys_addr_t rk_pte_page_address(u32 pte) | |
216 | { | |
217 | return (phys_addr_t)pte & RK_PTE_PAGE_ADDRESS_MASK; | |
218 | } | |
219 | ||
220 | static inline bool rk_pte_is_page_valid(u32 pte) | |
221 | { | |
222 | return pte & RK_PTE_PAGE_VALID; | |
223 | } | |
224 | ||
225 | /* TODO: set cache flags per prot IOMMU_CACHE */ | |
226 | static u32 rk_mk_pte(phys_addr_t page, int prot) | |
227 | { | |
228 | u32 flags = 0; | |
229 | flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; | |
230 | flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; | |
231 | page &= RK_PTE_PAGE_ADDRESS_MASK; | |
232 | return page | flags | RK_PTE_PAGE_VALID; | |
233 | } | |
234 | ||
235 | static u32 rk_mk_pte_invalid(u32 pte) | |
236 | { | |
237 | return pte & ~RK_PTE_PAGE_VALID; | |
238 | } | |
239 | ||
240 | /* | |
241 | * rk3288 iova (IOMMU Virtual Address) format | |
242 | * 31 22.21 12.11 0 | |
243 | * +-----------+-----------+-------------+ | |
244 | * | DTE index | PTE index | Page offset | | |
245 | * +-----------+-----------+-------------+ | |
246 | * 31:22 - DTE index - index of DTE in DT | |
247 | * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address | |
248 | * 11: 0 - Page offset - offset into page @ PTE.page_address | |
249 | */ | |
250 | #define RK_IOVA_DTE_MASK 0xffc00000 | |
251 | #define RK_IOVA_DTE_SHIFT 22 | |
252 | #define RK_IOVA_PTE_MASK 0x003ff000 | |
253 | #define RK_IOVA_PTE_SHIFT 12 | |
254 | #define RK_IOVA_PAGE_MASK 0x00000fff | |
255 | #define RK_IOVA_PAGE_SHIFT 0 | |
256 | ||
257 | static u32 rk_iova_dte_index(dma_addr_t iova) | |
258 | { | |
259 | return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; | |
260 | } | |
261 | ||
262 | static u32 rk_iova_pte_index(dma_addr_t iova) | |
263 | { | |
264 | return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; | |
265 | } | |
266 | ||
267 | static u32 rk_iova_page_offset(dma_addr_t iova) | |
268 | { | |
269 | return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; | |
270 | } | |
271 | ||
cd6438c5 | 272 | static u32 rk_iommu_read(void __iomem *base, u32 offset) |
c68a2921 | 273 | { |
cd6438c5 | 274 | return readl(base + offset); |
c68a2921 DK |
275 | } |
276 | ||
cd6438c5 | 277 | static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) |
c68a2921 | 278 | { |
cd6438c5 | 279 | writel(value, base + offset); |
c68a2921 DK |
280 | } |
281 | ||
282 | static void rk_iommu_command(struct rk_iommu *iommu, u32 command) | |
283 | { | |
cd6438c5 Z |
284 | int i; |
285 | ||
286 | for (i = 0; i < iommu->num_mmu; i++) | |
287 | writel(command, iommu->bases[i] + RK_MMU_COMMAND); | |
c68a2921 DK |
288 | } |
289 | ||
cd6438c5 Z |
290 | static void rk_iommu_base_command(void __iomem *base, u32 command) |
291 | { | |
292 | writel(command, base + RK_MMU_COMMAND); | |
293 | } | |
bf2a5e71 | 294 | static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, |
c68a2921 DK |
295 | size_t size) |
296 | { | |
cd6438c5 | 297 | int i; |
bf2a5e71 | 298 | dma_addr_t iova_end = iova_start + size; |
c68a2921 DK |
299 | /* |
300 | * TODO(djkurtz): Figure out when it is more efficient to shootdown the | |
301 | * entire iotlb rather than iterate over individual iovas. | |
302 | */ | |
bf2a5e71 TF |
303 | for (i = 0; i < iommu->num_mmu; i++) { |
304 | dma_addr_t iova; | |
305 | ||
306 | for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) | |
cd6438c5 | 307 | rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); |
bf2a5e71 | 308 | } |
c68a2921 DK |
309 | } |
310 | ||
311 | static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) | |
312 | { | |
cd6438c5 Z |
313 | bool active = true; |
314 | int i; | |
315 | ||
316 | for (i = 0; i < iommu->num_mmu; i++) | |
fbedd9b9 JK |
317 | active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & |
318 | RK_MMU_STATUS_STALL_ACTIVE); | |
cd6438c5 Z |
319 | |
320 | return active; | |
c68a2921 DK |
321 | } |
322 | ||
323 | static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) | |
324 | { | |
cd6438c5 Z |
325 | bool enable = true; |
326 | int i; | |
327 | ||
328 | for (i = 0; i < iommu->num_mmu; i++) | |
fbedd9b9 JK |
329 | enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & |
330 | RK_MMU_STATUS_PAGING_ENABLED); | |
cd6438c5 Z |
331 | |
332 | return enable; | |
c68a2921 DK |
333 | } |
334 | ||
0416bf64 TF |
335 | static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) |
336 | { | |
337 | bool done = true; | |
338 | int i; | |
339 | ||
340 | for (i = 0; i < iommu->num_mmu; i++) | |
341 | done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; | |
342 | ||
343 | return done; | |
344 | } | |
345 | ||
c68a2921 DK |
346 | static int rk_iommu_enable_stall(struct rk_iommu *iommu) |
347 | { | |
cd6438c5 | 348 | int ret, i; |
0416bf64 | 349 | bool val; |
c68a2921 DK |
350 | |
351 | if (rk_iommu_is_stall_active(iommu)) | |
352 | return 0; | |
353 | ||
354 | /* Stall can only be enabled if paging is enabled */ | |
355 | if (!rk_iommu_is_paging_enabled(iommu)) | |
356 | return 0; | |
357 | ||
358 | rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); | |
359 | ||
0416bf64 TF |
360 | ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, |
361 | val, RK_MMU_POLL_PERIOD_US, | |
362 | RK_MMU_POLL_TIMEOUT_US); | |
c68a2921 | 363 | if (ret) |
cd6438c5 Z |
364 | for (i = 0; i < iommu->num_mmu; i++) |
365 | dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", | |
366 | rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); | |
c68a2921 DK |
367 | |
368 | return ret; | |
369 | } | |
370 | ||
371 | static int rk_iommu_disable_stall(struct rk_iommu *iommu) | |
372 | { | |
cd6438c5 | 373 | int ret, i; |
0416bf64 | 374 | bool val; |
c68a2921 DK |
375 | |
376 | if (!rk_iommu_is_stall_active(iommu)) | |
377 | return 0; | |
378 | ||
379 | rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); | |
380 | ||
0416bf64 TF |
381 | ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, |
382 | !val, RK_MMU_POLL_PERIOD_US, | |
383 | RK_MMU_POLL_TIMEOUT_US); | |
c68a2921 | 384 | if (ret) |
cd6438c5 Z |
385 | for (i = 0; i < iommu->num_mmu; i++) |
386 | dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", | |
387 | rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); | |
c68a2921 DK |
388 | |
389 | return ret; | |
390 | } | |
391 | ||
392 | static int rk_iommu_enable_paging(struct rk_iommu *iommu) | |
393 | { | |
cd6438c5 | 394 | int ret, i; |
0416bf64 | 395 | bool val; |
c68a2921 DK |
396 | |
397 | if (rk_iommu_is_paging_enabled(iommu)) | |
398 | return 0; | |
399 | ||
400 | rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); | |
401 | ||
0416bf64 TF |
402 | ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, |
403 | val, RK_MMU_POLL_PERIOD_US, | |
404 | RK_MMU_POLL_TIMEOUT_US); | |
c68a2921 | 405 | if (ret) |
cd6438c5 Z |
406 | for (i = 0; i < iommu->num_mmu; i++) |
407 | dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", | |
408 | rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); | |
c68a2921 DK |
409 | |
410 | return ret; | |
411 | } | |
412 | ||
413 | static int rk_iommu_disable_paging(struct rk_iommu *iommu) | |
414 | { | |
cd6438c5 | 415 | int ret, i; |
0416bf64 | 416 | bool val; |
c68a2921 DK |
417 | |
418 | if (!rk_iommu_is_paging_enabled(iommu)) | |
419 | return 0; | |
420 | ||
421 | rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); | |
422 | ||
0416bf64 TF |
423 | ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, |
424 | !val, RK_MMU_POLL_PERIOD_US, | |
425 | RK_MMU_POLL_TIMEOUT_US); | |
c68a2921 | 426 | if (ret) |
cd6438c5 Z |
427 | for (i = 0; i < iommu->num_mmu; i++) |
428 | dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", | |
429 | rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); | |
c68a2921 DK |
430 | |
431 | return ret; | |
432 | } | |
433 | ||
434 | static int rk_iommu_force_reset(struct rk_iommu *iommu) | |
435 | { | |
cd6438c5 | 436 | int ret, i; |
c68a2921 | 437 | u32 dte_addr; |
0416bf64 | 438 | bool val; |
c68a2921 | 439 | |
c3aa4742 SX |
440 | if (iommu->reset_disabled) |
441 | return 0; | |
442 | ||
c68a2921 DK |
443 | /* |
444 | * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY | |
445 | * and verifying that upper 5 nybbles are read back. | |
446 | */ | |
cd6438c5 Z |
447 | for (i = 0; i < iommu->num_mmu; i++) { |
448 | rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, DTE_ADDR_DUMMY); | |
c68a2921 | 449 | |
cd6438c5 Z |
450 | dte_addr = rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR); |
451 | if (dte_addr != (DTE_ADDR_DUMMY & RK_DTE_PT_ADDRESS_MASK)) { | |
452 | dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); | |
453 | return -EFAULT; | |
454 | } | |
c68a2921 DK |
455 | } |
456 | ||
457 | rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); | |
458 | ||
0416bf64 TF |
459 | ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, |
460 | val, RK_MMU_FORCE_RESET_TIMEOUT_US, | |
461 | RK_MMU_POLL_TIMEOUT_US); | |
462 | if (ret) { | |
463 | dev_err(iommu->dev, "FORCE_RESET command timed out\n"); | |
464 | return ret; | |
cd6438c5 | 465 | } |
c68a2921 | 466 | |
cd6438c5 | 467 | return 0; |
c68a2921 DK |
468 | } |
469 | ||
cd6438c5 | 470 | static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) |
c68a2921 | 471 | { |
cd6438c5 | 472 | void __iomem *base = iommu->bases[index]; |
c68a2921 DK |
473 | u32 dte_index, pte_index, page_offset; |
474 | u32 mmu_dte_addr; | |
475 | phys_addr_t mmu_dte_addr_phys, dte_addr_phys; | |
476 | u32 *dte_addr; | |
477 | u32 dte; | |
478 | phys_addr_t pte_addr_phys = 0; | |
479 | u32 *pte_addr = NULL; | |
480 | u32 pte = 0; | |
481 | phys_addr_t page_addr_phys = 0; | |
482 | u32 page_flags = 0; | |
483 | ||
484 | dte_index = rk_iova_dte_index(iova); | |
485 | pte_index = rk_iova_pte_index(iova); | |
486 | page_offset = rk_iova_page_offset(iova); | |
487 | ||
cd6438c5 | 488 | mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); |
c68a2921 DK |
489 | mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr; |
490 | ||
491 | dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); | |
492 | dte_addr = phys_to_virt(dte_addr_phys); | |
493 | dte = *dte_addr; | |
494 | ||
495 | if (!rk_dte_is_pt_valid(dte)) | |
496 | goto print_it; | |
497 | ||
498 | pte_addr_phys = rk_dte_pt_address(dte) + (pte_index * 4); | |
499 | pte_addr = phys_to_virt(pte_addr_phys); | |
500 | pte = *pte_addr; | |
501 | ||
502 | if (!rk_pte_is_page_valid(pte)) | |
503 | goto print_it; | |
504 | ||
505 | page_addr_phys = rk_pte_page_address(pte) + page_offset; | |
506 | page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; | |
507 | ||
508 | print_it: | |
509 | dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", | |
510 | &iova, dte_index, pte_index, page_offset); | |
511 | dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", | |
512 | &mmu_dte_addr_phys, &dte_addr_phys, dte, | |
513 | rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, | |
514 | rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); | |
515 | } | |
516 | ||
517 | static irqreturn_t rk_iommu_irq(int irq, void *dev_id) | |
518 | { | |
519 | struct rk_iommu *iommu = dev_id; | |
520 | u32 status; | |
521 | u32 int_status; | |
522 | dma_addr_t iova; | |
cd6438c5 | 523 | irqreturn_t ret = IRQ_NONE; |
3fc7c5c0 | 524 | int i, err; |
c68a2921 | 525 | |
3fc7c5c0 MZ |
526 | err = pm_runtime_get_if_in_use(iommu->dev); |
527 | if (WARN_ON_ONCE(err <= 0)) | |
528 | return ret; | |
0f181d3c JC |
529 | |
530 | if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) | |
531 | goto out; | |
f2e3a5f5 | 532 | |
cd6438c5 Z |
533 | for (i = 0; i < iommu->num_mmu; i++) { |
534 | int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); | |
535 | if (int_status == 0) | |
536 | continue; | |
c68a2921 | 537 | |
cd6438c5 Z |
538 | ret = IRQ_HANDLED; |
539 | iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); | |
c68a2921 | 540 | |
cd6438c5 Z |
541 | if (int_status & RK_MMU_IRQ_PAGE_FAULT) { |
542 | int flags; | |
c68a2921 | 543 | |
cd6438c5 Z |
544 | status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); |
545 | flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? | |
546 | IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
c68a2921 | 547 | |
cd6438c5 Z |
548 | dev_err(iommu->dev, "Page fault at %pad of type %s\n", |
549 | &iova, | |
550 | (flags == IOMMU_FAULT_WRITE) ? "write" : "read"); | |
c68a2921 | 551 | |
cd6438c5 | 552 | log_iova(iommu, i, iova); |
c68a2921 | 553 | |
cd6438c5 Z |
554 | /* |
555 | * Report page fault to any installed handlers. | |
556 | * Ignore the return code, though, since we always zap cache | |
557 | * and clear the page fault anyway. | |
558 | */ | |
559 | if (iommu->domain) | |
560 | report_iommu_fault(iommu->domain, iommu->dev, iova, | |
561 | flags); | |
562 | else | |
563 | dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); | |
c68a2921 | 564 | |
cd6438c5 Z |
565 | rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); |
566 | rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); | |
567 | } | |
c68a2921 | 568 | |
cd6438c5 Z |
569 | if (int_status & RK_MMU_IRQ_BUS_ERROR) |
570 | dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); | |
c68a2921 | 571 | |
cd6438c5 Z |
572 | if (int_status & ~RK_MMU_IRQ_MASK) |
573 | dev_err(iommu->dev, "unexpected int_status: %#08x\n", | |
574 | int_status); | |
c68a2921 | 575 | |
cd6438c5 Z |
576 | rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); |
577 | } | |
c68a2921 | 578 | |
f2e3a5f5 TF |
579 | clk_bulk_disable(iommu->num_clocks, iommu->clocks); |
580 | ||
0f181d3c JC |
581 | out: |
582 | pm_runtime_put(iommu->dev); | |
cd6438c5 | 583 | return ret; |
c68a2921 DK |
584 | } |
585 | ||
586 | static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, | |
587 | dma_addr_t iova) | |
588 | { | |
bcd516a3 | 589 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
c68a2921 DK |
590 | unsigned long flags; |
591 | phys_addr_t pt_phys, phys = 0; | |
592 | u32 dte, pte; | |
593 | u32 *page_table; | |
594 | ||
595 | spin_lock_irqsave(&rk_domain->dt_lock, flags); | |
596 | ||
597 | dte = rk_domain->dt[rk_iova_dte_index(iova)]; | |
598 | if (!rk_dte_is_pt_valid(dte)) | |
599 | goto out; | |
600 | ||
601 | pt_phys = rk_dte_pt_address(dte); | |
602 | page_table = (u32 *)phys_to_virt(pt_phys); | |
603 | pte = page_table[rk_iova_pte_index(iova)]; | |
604 | if (!rk_pte_is_page_valid(pte)) | |
605 | goto out; | |
606 | ||
607 | phys = rk_pte_page_address(pte) + rk_iova_page_offset(iova); | |
608 | out: | |
609 | spin_unlock_irqrestore(&rk_domain->dt_lock, flags); | |
610 | ||
611 | return phys; | |
612 | } | |
613 | ||
614 | static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, | |
615 | dma_addr_t iova, size_t size) | |
616 | { | |
617 | struct list_head *pos; | |
618 | unsigned long flags; | |
619 | ||
620 | /* shootdown these iova from all iommus using this domain */ | |
621 | spin_lock_irqsave(&rk_domain->iommus_lock, flags); | |
622 | list_for_each(pos, &rk_domain->iommus) { | |
623 | struct rk_iommu *iommu; | |
3fc7c5c0 | 624 | int ret; |
0f181d3c | 625 | |
c68a2921 | 626 | iommu = list_entry(pos, struct rk_iommu, node); |
0f181d3c JC |
627 | |
628 | /* Only zap TLBs of IOMMUs that are powered on. */ | |
3fc7c5c0 MZ |
629 | ret = pm_runtime_get_if_in_use(iommu->dev); |
630 | if (WARN_ON_ONCE(ret < 0)) | |
631 | continue; | |
632 | if (ret) { | |
0f181d3c JC |
633 | WARN_ON(clk_bulk_enable(iommu->num_clocks, |
634 | iommu->clocks)); | |
635 | rk_iommu_zap_lines(iommu, iova, size); | |
636 | clk_bulk_disable(iommu->num_clocks, iommu->clocks); | |
637 | pm_runtime_put(iommu->dev); | |
638 | } | |
c68a2921 DK |
639 | } |
640 | spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); | |
641 | } | |
642 | ||
d4dd920c TF |
643 | static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, |
644 | dma_addr_t iova, size_t size) | |
645 | { | |
646 | rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); | |
647 | if (size > SPAGE_SIZE) | |
648 | rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, | |
649 | SPAGE_SIZE); | |
650 | } | |
651 | ||
c68a2921 DK |
652 | static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, |
653 | dma_addr_t iova) | |
654 | { | |
655 | u32 *page_table, *dte_addr; | |
4f0aba67 | 656 | u32 dte_index, dte; |
c68a2921 | 657 | phys_addr_t pt_phys; |
4f0aba67 | 658 | dma_addr_t pt_dma; |
c68a2921 DK |
659 | |
660 | assert_spin_locked(&rk_domain->dt_lock); | |
661 | ||
4f0aba67 SZ |
662 | dte_index = rk_iova_dte_index(iova); |
663 | dte_addr = &rk_domain->dt[dte_index]; | |
c68a2921 DK |
664 | dte = *dte_addr; |
665 | if (rk_dte_is_pt_valid(dte)) | |
666 | goto done; | |
667 | ||
668 | page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32); | |
669 | if (!page_table) | |
670 | return ERR_PTR(-ENOMEM); | |
671 | ||
9176a303 JC |
672 | pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); |
673 | if (dma_mapping_error(dma_dev, pt_dma)) { | |
674 | dev_err(dma_dev, "DMA mapping error while allocating page table\n"); | |
4f0aba67 SZ |
675 | free_page((unsigned long)page_table); |
676 | return ERR_PTR(-ENOMEM); | |
677 | } | |
c68a2921 | 678 | |
4f0aba67 SZ |
679 | dte = rk_mk_dte(pt_dma); |
680 | *dte_addr = dte; | |
c68a2921 | 681 | |
4f0aba67 SZ |
682 | rk_table_flush(rk_domain, pt_dma, NUM_PT_ENTRIES); |
683 | rk_table_flush(rk_domain, | |
684 | rk_domain->dt_dma + dte_index * sizeof(u32), 1); | |
c68a2921 DK |
685 | done: |
686 | pt_phys = rk_dte_pt_address(dte); | |
687 | return (u32 *)phys_to_virt(pt_phys); | |
688 | } | |
689 | ||
690 | static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, | |
4f0aba67 SZ |
691 | u32 *pte_addr, dma_addr_t pte_dma, |
692 | size_t size) | |
c68a2921 DK |
693 | { |
694 | unsigned int pte_count; | |
695 | unsigned int pte_total = size / SPAGE_SIZE; | |
696 | ||
697 | assert_spin_locked(&rk_domain->dt_lock); | |
698 | ||
699 | for (pte_count = 0; pte_count < pte_total; pte_count++) { | |
700 | u32 pte = pte_addr[pte_count]; | |
701 | if (!rk_pte_is_page_valid(pte)) | |
702 | break; | |
703 | ||
704 | pte_addr[pte_count] = rk_mk_pte_invalid(pte); | |
705 | } | |
706 | ||
4f0aba67 | 707 | rk_table_flush(rk_domain, pte_dma, pte_count); |
c68a2921 DK |
708 | |
709 | return pte_count * SPAGE_SIZE; | |
710 | } | |
711 | ||
712 | static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, | |
4f0aba67 SZ |
713 | dma_addr_t pte_dma, dma_addr_t iova, |
714 | phys_addr_t paddr, size_t size, int prot) | |
c68a2921 DK |
715 | { |
716 | unsigned int pte_count; | |
717 | unsigned int pte_total = size / SPAGE_SIZE; | |
718 | phys_addr_t page_phys; | |
719 | ||
720 | assert_spin_locked(&rk_domain->dt_lock); | |
721 | ||
722 | for (pte_count = 0; pte_count < pte_total; pte_count++) { | |
723 | u32 pte = pte_addr[pte_count]; | |
724 | ||
725 | if (rk_pte_is_page_valid(pte)) | |
726 | goto unwind; | |
727 | ||
728 | pte_addr[pte_count] = rk_mk_pte(paddr, prot); | |
729 | ||
730 | paddr += SPAGE_SIZE; | |
731 | } | |
732 | ||
4f0aba67 | 733 | rk_table_flush(rk_domain, pte_dma, pte_total); |
c68a2921 | 734 | |
d4dd920c TF |
735 | /* |
736 | * Zap the first and last iova to evict from iotlb any previously | |
737 | * mapped cachelines holding stale values for its dte and pte. | |
738 | * We only zap the first and last iova, since only they could have | |
739 | * dte or pte shared with an existing mapping. | |
740 | */ | |
741 | rk_iommu_zap_iova_first_last(rk_domain, iova, size); | |
742 | ||
c68a2921 DK |
743 | return 0; |
744 | unwind: | |
745 | /* Unmap the range of iovas that we just mapped */ | |
4f0aba67 SZ |
746 | rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, |
747 | pte_count * SPAGE_SIZE); | |
c68a2921 DK |
748 | |
749 | iova += pte_count * SPAGE_SIZE; | |
750 | page_phys = rk_pte_page_address(pte_addr[pte_count]); | |
751 | pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", | |
752 | &iova, &page_phys, &paddr, prot); | |
753 | ||
754 | return -EADDRINUSE; | |
755 | } | |
756 | ||
757 | static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, | |
758 | phys_addr_t paddr, size_t size, int prot) | |
759 | { | |
bcd516a3 | 760 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
c68a2921 | 761 | unsigned long flags; |
4f0aba67 | 762 | dma_addr_t pte_dma, iova = (dma_addr_t)_iova; |
c68a2921 | 763 | u32 *page_table, *pte_addr; |
4f0aba67 | 764 | u32 dte_index, pte_index; |
c68a2921 DK |
765 | int ret; |
766 | ||
767 | spin_lock_irqsave(&rk_domain->dt_lock, flags); | |
768 | ||
769 | /* | |
770 | * pgsize_bitmap specifies iova sizes that fit in one page table | |
771 | * (1024 4-KiB pages = 4 MiB). | |
772 | * So, size will always be 4096 <= size <= 4194304. | |
773 | * Since iommu_map() guarantees that both iova and size will be | |
774 | * aligned, we will always only be mapping from a single dte here. | |
775 | */ | |
776 | page_table = rk_dte_get_page_table(rk_domain, iova); | |
777 | if (IS_ERR(page_table)) { | |
778 | spin_unlock_irqrestore(&rk_domain->dt_lock, flags); | |
779 | return PTR_ERR(page_table); | |
780 | } | |
781 | ||
4f0aba67 SZ |
782 | dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; |
783 | pte_index = rk_iova_pte_index(iova); | |
784 | pte_addr = &page_table[pte_index]; | |
785 | pte_dma = rk_dte_pt_address(dte_index) + pte_index * sizeof(u32); | |
786 | ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, | |
787 | paddr, size, prot); | |
788 | ||
c68a2921 DK |
789 | spin_unlock_irqrestore(&rk_domain->dt_lock, flags); |
790 | ||
791 | return ret; | |
792 | } | |
793 | ||
794 | static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, | |
795 | size_t size) | |
796 | { | |
bcd516a3 | 797 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
c68a2921 | 798 | unsigned long flags; |
4f0aba67 | 799 | dma_addr_t pte_dma, iova = (dma_addr_t)_iova; |
c68a2921 DK |
800 | phys_addr_t pt_phys; |
801 | u32 dte; | |
802 | u32 *pte_addr; | |
803 | size_t unmap_size; | |
804 | ||
805 | spin_lock_irqsave(&rk_domain->dt_lock, flags); | |
806 | ||
807 | /* | |
808 | * pgsize_bitmap specifies iova sizes that fit in one page table | |
809 | * (1024 4-KiB pages = 4 MiB). | |
810 | * So, size will always be 4096 <= size <= 4194304. | |
811 | * Since iommu_unmap() guarantees that both iova and size will be | |
812 | * aligned, we will always only be unmapping from a single dte here. | |
813 | */ | |
814 | dte = rk_domain->dt[rk_iova_dte_index(iova)]; | |
815 | /* Just return 0 if iova is unmapped */ | |
816 | if (!rk_dte_is_pt_valid(dte)) { | |
817 | spin_unlock_irqrestore(&rk_domain->dt_lock, flags); | |
818 | return 0; | |
819 | } | |
820 | ||
821 | pt_phys = rk_dte_pt_address(dte); | |
822 | pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); | |
4f0aba67 SZ |
823 | pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); |
824 | unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); | |
c68a2921 DK |
825 | |
826 | spin_unlock_irqrestore(&rk_domain->dt_lock, flags); | |
827 | ||
828 | /* Shootdown iotlb entries for iova range that was just unmapped */ | |
829 | rk_iommu_zap_iova(rk_domain, iova, unmap_size); | |
830 | ||
831 | return unmap_size; | |
832 | } | |
833 | ||
834 | static struct rk_iommu *rk_iommu_from_dev(struct device *dev) | |
835 | { | |
5fd577c3 | 836 | struct rk_iommudata *data = dev->archdata.iommu; |
c68a2921 | 837 | |
5fd577c3 | 838 | return data ? data->iommu : NULL; |
c68a2921 DK |
839 | } |
840 | ||
0f181d3c JC |
841 | /* Must be called with iommu powered on and attached */ |
842 | static void rk_iommu_disable(struct rk_iommu *iommu) | |
c68a2921 | 843 | { |
0f181d3c JC |
844 | int i; |
845 | ||
846 | /* Ignore error while disabling, just keep going */ | |
847 | WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); | |
848 | rk_iommu_enable_stall(iommu); | |
849 | rk_iommu_disable_paging(iommu); | |
850 | for (i = 0; i < iommu->num_mmu; i++) { | |
851 | rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); | |
852 | rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); | |
853 | } | |
854 | rk_iommu_disable_stall(iommu); | |
855 | clk_bulk_disable(iommu->num_clocks, iommu->clocks); | |
856 | } | |
857 | ||
858 | /* Must be called with iommu powered on and attached */ | |
859 | static int rk_iommu_enable(struct rk_iommu *iommu) | |
860 | { | |
861 | struct iommu_domain *domain = iommu->domain; | |
bcd516a3 | 862 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
cd6438c5 | 863 | int ret, i; |
c68a2921 | 864 | |
f2e3a5f5 | 865 | ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); |
c68a2921 DK |
866 | if (ret) |
867 | return ret; | |
868 | ||
f2e3a5f5 TF |
869 | ret = rk_iommu_enable_stall(iommu); |
870 | if (ret) | |
871 | goto out_disable_clocks; | |
872 | ||
c68a2921 DK |
873 | ret = rk_iommu_force_reset(iommu); |
874 | if (ret) | |
f6717d72 | 875 | goto out_disable_stall; |
c68a2921 | 876 | |
cd6438c5 | 877 | for (i = 0; i < iommu->num_mmu; i++) { |
4f0aba67 SZ |
878 | rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, |
879 | rk_domain->dt_dma); | |
ae8a7910 | 880 | rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); |
cd6438c5 Z |
881 | rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); |
882 | } | |
c68a2921 DK |
883 | |
884 | ret = rk_iommu_enable_paging(iommu); | |
c68a2921 | 885 | |
f6717d72 | 886 | out_disable_stall: |
c68a2921 | 887 | rk_iommu_disable_stall(iommu); |
f2e3a5f5 TF |
888 | out_disable_clocks: |
889 | clk_bulk_disable(iommu->num_clocks, iommu->clocks); | |
f6717d72 | 890 | return ret; |
c68a2921 DK |
891 | } |
892 | ||
893 | static void rk_iommu_detach_device(struct iommu_domain *domain, | |
894 | struct device *dev) | |
895 | { | |
896 | struct rk_iommu *iommu; | |
bcd516a3 | 897 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
c68a2921 | 898 | unsigned long flags; |
3fc7c5c0 | 899 | int ret; |
c68a2921 DK |
900 | |
901 | /* Allow 'virtual devices' (eg drm) to detach from domain */ | |
902 | iommu = rk_iommu_from_dev(dev); | |
903 | if (!iommu) | |
904 | return; | |
905 | ||
0f181d3c JC |
906 | dev_dbg(dev, "Detaching from iommu domain\n"); |
907 | ||
908 | /* iommu already detached */ | |
909 | if (iommu->domain != domain) | |
910 | return; | |
911 | ||
912 | iommu->domain = NULL; | |
913 | ||
c68a2921 DK |
914 | spin_lock_irqsave(&rk_domain->iommus_lock, flags); |
915 | list_del_init(&iommu->node); | |
916 | spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); | |
917 | ||
3fc7c5c0 MZ |
918 | ret = pm_runtime_get_if_in_use(iommu->dev); |
919 | WARN_ON_ONCE(ret < 0); | |
920 | if (ret > 0) { | |
0f181d3c JC |
921 | rk_iommu_disable(iommu); |
922 | pm_runtime_put(iommu->dev); | |
cd6438c5 | 923 | } |
0f181d3c | 924 | } |
c68a2921 | 925 | |
0f181d3c JC |
926 | static int rk_iommu_attach_device(struct iommu_domain *domain, |
927 | struct device *dev) | |
928 | { | |
929 | struct rk_iommu *iommu; | |
930 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); | |
931 | unsigned long flags; | |
932 | int ret; | |
c68a2921 | 933 | |
0f181d3c JC |
934 | /* |
935 | * Allow 'virtual devices' (e.g., drm) to attach to domain. | |
936 | * Such a device does not belong to an iommu group. | |
937 | */ | |
938 | iommu = rk_iommu_from_dev(dev); | |
939 | if (!iommu) | |
940 | return 0; | |
941 | ||
942 | dev_dbg(dev, "Attaching to iommu domain\n"); | |
943 | ||
944 | /* iommu already attached */ | |
945 | if (iommu->domain == domain) | |
946 | return 0; | |
947 | ||
948 | if (iommu->domain) | |
949 | rk_iommu_detach_device(iommu->domain, dev); | |
950 | ||
951 | iommu->domain = domain; | |
952 | ||
953 | spin_lock_irqsave(&rk_domain->iommus_lock, flags); | |
954 | list_add_tail(&iommu->node, &rk_domain->iommus); | |
955 | spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); | |
956 | ||
3fc7c5c0 MZ |
957 | ret = pm_runtime_get_if_in_use(iommu->dev); |
958 | if (!ret || WARN_ON_ONCE(ret < 0)) | |
0f181d3c JC |
959 | return 0; |
960 | ||
961 | ret = rk_iommu_enable(iommu); | |
962 | if (ret) | |
963 | rk_iommu_detach_device(iommu->domain, dev); | |
964 | ||
965 | pm_runtime_put(iommu->dev); | |
966 | ||
967 | return ret; | |
c68a2921 DK |
968 | } |
969 | ||
bcd516a3 | 970 | static struct iommu_domain *rk_iommu_domain_alloc(unsigned type) |
c68a2921 DK |
971 | { |
972 | struct rk_iommu_domain *rk_domain; | |
973 | ||
a93db2f2 | 974 | if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) |
bcd516a3 JR |
975 | return NULL; |
976 | ||
9176a303 | 977 | if (!dma_dev) |
bcd516a3 | 978 | return NULL; |
c68a2921 | 979 | |
9176a303 | 980 | rk_domain = devm_kzalloc(dma_dev, sizeof(*rk_domain), GFP_KERNEL); |
4f0aba67 | 981 | if (!rk_domain) |
9176a303 | 982 | return NULL; |
4f0aba67 | 983 | |
a93db2f2 SZ |
984 | if (type == IOMMU_DOMAIN_DMA && |
985 | iommu_get_dma_cookie(&rk_domain->domain)) | |
9176a303 | 986 | return NULL; |
4f0aba67 | 987 | |
c68a2921 DK |
988 | /* |
989 | * rk32xx iommus use a 2 level pagetable. | |
990 | * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. | |
991 | * Allocate one 4 KiB page for each table. | |
992 | */ | |
993 | rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32); | |
994 | if (!rk_domain->dt) | |
4f0aba67 SZ |
995 | goto err_put_cookie; |
996 | ||
9176a303 | 997 | rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt, |
4f0aba67 | 998 | SPAGE_SIZE, DMA_TO_DEVICE); |
9176a303 JC |
999 | if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) { |
1000 | dev_err(dma_dev, "DMA map error for DT\n"); | |
4f0aba67 SZ |
1001 | goto err_free_dt; |
1002 | } | |
c68a2921 | 1003 | |
4f0aba67 | 1004 | rk_table_flush(rk_domain, rk_domain->dt_dma, NUM_DT_ENTRIES); |
c68a2921 DK |
1005 | |
1006 | spin_lock_init(&rk_domain->iommus_lock); | |
1007 | spin_lock_init(&rk_domain->dt_lock); | |
1008 | INIT_LIST_HEAD(&rk_domain->iommus); | |
1009 | ||
a93db2f2 SZ |
1010 | rk_domain->domain.geometry.aperture_start = 0; |
1011 | rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
1012 | rk_domain->domain.geometry.force_aperture = true; | |
1013 | ||
bcd516a3 | 1014 | return &rk_domain->domain; |
c68a2921 | 1015 | |
4f0aba67 SZ |
1016 | err_free_dt: |
1017 | free_page((unsigned long)rk_domain->dt); | |
1018 | err_put_cookie: | |
a93db2f2 SZ |
1019 | if (type == IOMMU_DOMAIN_DMA) |
1020 | iommu_put_dma_cookie(&rk_domain->domain); | |
4f0aba67 | 1021 | |
bcd516a3 | 1022 | return NULL; |
c68a2921 DK |
1023 | } |
1024 | ||
bcd516a3 | 1025 | static void rk_iommu_domain_free(struct iommu_domain *domain) |
c68a2921 | 1026 | { |
bcd516a3 | 1027 | struct rk_iommu_domain *rk_domain = to_rk_domain(domain); |
c68a2921 DK |
1028 | int i; |
1029 | ||
1030 | WARN_ON(!list_empty(&rk_domain->iommus)); | |
1031 | ||
1032 | for (i = 0; i < NUM_DT_ENTRIES; i++) { | |
1033 | u32 dte = rk_domain->dt[i]; | |
1034 | if (rk_dte_is_pt_valid(dte)) { | |
1035 | phys_addr_t pt_phys = rk_dte_pt_address(dte); | |
1036 | u32 *page_table = phys_to_virt(pt_phys); | |
9176a303 | 1037 | dma_unmap_single(dma_dev, pt_phys, |
4f0aba67 | 1038 | SPAGE_SIZE, DMA_TO_DEVICE); |
c68a2921 DK |
1039 | free_page((unsigned long)page_table); |
1040 | } | |
1041 | } | |
1042 | ||
9176a303 | 1043 | dma_unmap_single(dma_dev, rk_domain->dt_dma, |
4f0aba67 | 1044 | SPAGE_SIZE, DMA_TO_DEVICE); |
c68a2921 | 1045 | free_page((unsigned long)rk_domain->dt); |
4f0aba67 | 1046 | |
a93db2f2 SZ |
1047 | if (domain->type == IOMMU_DOMAIN_DMA) |
1048 | iommu_put_dma_cookie(&rk_domain->domain); | |
c68a2921 DK |
1049 | } |
1050 | ||
5fd577c3 | 1051 | static int rk_iommu_add_device(struct device *dev) |
c68a2921 | 1052 | { |
5fd577c3 JC |
1053 | struct iommu_group *group; |
1054 | struct rk_iommu *iommu; | |
0f181d3c | 1055 | struct rk_iommudata *data; |
c68a2921 | 1056 | |
0f181d3c JC |
1057 | data = dev->archdata.iommu; |
1058 | if (!data) | |
5fd577c3 | 1059 | return -ENODEV; |
c68a2921 | 1060 | |
0f181d3c JC |
1061 | iommu = rk_iommu_from_dev(dev); |
1062 | ||
5fd577c3 JC |
1063 | group = iommu_group_get_for_dev(dev); |
1064 | if (IS_ERR(group)) | |
1065 | return PTR_ERR(group); | |
1066 | iommu_group_put(group); | |
c68a2921 | 1067 | |
5fd577c3 | 1068 | iommu_device_link(&iommu->iommu, dev); |
0f181d3c | 1069 | data->link = device_link_add(dev, iommu->dev, DL_FLAG_PM_RUNTIME); |
c68a2921 DK |
1070 | |
1071 | return 0; | |
1072 | } | |
1073 | ||
5fd577c3 | 1074 | static void rk_iommu_remove_device(struct device *dev) |
c68a2921 | 1075 | { |
c9d9f239 | 1076 | struct rk_iommu *iommu; |
0f181d3c | 1077 | struct rk_iommudata *data = dev->archdata.iommu; |
c68a2921 | 1078 | |
c9d9f239 | 1079 | iommu = rk_iommu_from_dev(dev); |
c9d9f239 | 1080 | |
0f181d3c | 1081 | device_link_del(data->link); |
5fd577c3 | 1082 | iommu_device_unlink(&iommu->iommu, dev); |
c68a2921 | 1083 | iommu_group_remove_device(dev); |
c68a2921 DK |
1084 | } |
1085 | ||
57c26957 JC |
1086 | static struct iommu_group *rk_iommu_device_group(struct device *dev) |
1087 | { | |
1088 | struct rk_iommu *iommu; | |
1089 | ||
1090 | iommu = rk_iommu_from_dev(dev); | |
1091 | ||
1092 | return iommu_group_ref_get(iommu->group); | |
1093 | } | |
1094 | ||
5fd577c3 JC |
1095 | static int rk_iommu_of_xlate(struct device *dev, |
1096 | struct of_phandle_args *args) | |
c68a2921 | 1097 | { |
5fd577c3 JC |
1098 | struct platform_device *iommu_dev; |
1099 | struct rk_iommudata *data; | |
c9d9f239 | 1100 | |
5fd577c3 JC |
1101 | data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); |
1102 | if (!data) | |
1103 | return -ENOMEM; | |
c68a2921 | 1104 | |
5fd577c3 | 1105 | iommu_dev = of_find_device_by_node(args->np); |
c9d9f239 | 1106 | |
5fd577c3 JC |
1107 | data->iommu = platform_get_drvdata(iommu_dev); |
1108 | dev->archdata.iommu = data; | |
1109 | ||
40fa84e1 | 1110 | platform_device_put(iommu_dev); |
5fd577c3 JC |
1111 | |
1112 | return 0; | |
c68a2921 DK |
1113 | } |
1114 | ||
1115 | static const struct iommu_ops rk_iommu_ops = { | |
bcd516a3 JR |
1116 | .domain_alloc = rk_iommu_domain_alloc, |
1117 | .domain_free = rk_iommu_domain_free, | |
c68a2921 DK |
1118 | .attach_dev = rk_iommu_attach_device, |
1119 | .detach_dev = rk_iommu_detach_device, | |
1120 | .map = rk_iommu_map, | |
1121 | .unmap = rk_iommu_unmap, | |
1122 | .add_device = rk_iommu_add_device, | |
1123 | .remove_device = rk_iommu_remove_device, | |
1124 | .iova_to_phys = rk_iommu_iova_to_phys, | |
57c26957 | 1125 | .device_group = rk_iommu_device_group, |
c68a2921 | 1126 | .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, |
5fd577c3 | 1127 | .of_xlate = rk_iommu_of_xlate, |
c68a2921 DK |
1128 | }; |
1129 | ||
1130 | static int rk_iommu_probe(struct platform_device *pdev) | |
1131 | { | |
1132 | struct device *dev = &pdev->dev; | |
1133 | struct rk_iommu *iommu; | |
1134 | struct resource *res; | |
3d08f434 | 1135 | int num_res = pdev->num_resources; |
d0b912bd | 1136 | int err, i, irq; |
c68a2921 DK |
1137 | |
1138 | iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); | |
1139 | if (!iommu) | |
1140 | return -ENOMEM; | |
1141 | ||
1142 | platform_set_drvdata(pdev, iommu); | |
1143 | iommu->dev = dev; | |
cd6438c5 | 1144 | iommu->num_mmu = 0; |
3d08f434 | 1145 | |
a86854d0 | 1146 | iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), |
cd6438c5 Z |
1147 | GFP_KERNEL); |
1148 | if (!iommu->bases) | |
1149 | return -ENOMEM; | |
c68a2921 | 1150 | |
3d08f434 | 1151 | for (i = 0; i < num_res; i++) { |
cd6438c5 | 1152 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
8d7f2d84 TV |
1153 | if (!res) |
1154 | continue; | |
cd6438c5 Z |
1155 | iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); |
1156 | if (IS_ERR(iommu->bases[i])) | |
1157 | continue; | |
1158 | iommu->num_mmu++; | |
1159 | } | |
1160 | if (iommu->num_mmu == 0) | |
1161 | return PTR_ERR(iommu->bases[0]); | |
c68a2921 | 1162 | |
c3aa4742 SX |
1163 | iommu->reset_disabled = device_property_read_bool(dev, |
1164 | "rockchip,disable-mmu-reset"); | |
1165 | ||
f2e3a5f5 TF |
1166 | iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); |
1167 | iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, | |
1168 | sizeof(*iommu->clocks), GFP_KERNEL); | |
1169 | if (!iommu->clocks) | |
1170 | return -ENOMEM; | |
1171 | ||
1172 | for (i = 0; i < iommu->num_clocks; ++i) | |
1173 | iommu->clocks[i].id = rk_iommu_clocks[i]; | |
1174 | ||
2f8c7f2e HS |
1175 | /* |
1176 | * iommu clocks should be present for all new devices and devicetrees | |
1177 | * but there are older devicetrees without clocks out in the wild. | |
1178 | * So clocks as optional for the time being. | |
1179 | */ | |
f2e3a5f5 | 1180 | err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); |
2f8c7f2e HS |
1181 | if (err == -ENOENT) |
1182 | iommu->num_clocks = 0; | |
1183 | else if (err) | |
f2e3a5f5 TF |
1184 | return err; |
1185 | ||
1186 | err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); | |
c9d9f239 JR |
1187 | if (err) |
1188 | return err; | |
1189 | ||
57c26957 JC |
1190 | iommu->group = iommu_group_alloc(); |
1191 | if (IS_ERR(iommu->group)) { | |
1192 | err = PTR_ERR(iommu->group); | |
1193 | goto err_unprepare_clocks; | |
1194 | } | |
1195 | ||
f2e3a5f5 TF |
1196 | err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); |
1197 | if (err) | |
57c26957 | 1198 | goto err_put_group; |
f2e3a5f5 | 1199 | |
c9d9f239 | 1200 | iommu_device_set_ops(&iommu->iommu, &rk_iommu_ops); |
5fd577c3 JC |
1201 | iommu_device_set_fwnode(&iommu->iommu, &dev->of_node->fwnode); |
1202 | ||
c9d9f239 | 1203 | err = iommu_device_register(&iommu->iommu); |
6d9ffaad | 1204 | if (err) |
f2e3a5f5 | 1205 | goto err_remove_sysfs; |
c9d9f239 | 1206 | |
9176a303 JC |
1207 | /* |
1208 | * Use the first registered IOMMU device for domain to use with DMA | |
1209 | * API, since a domain might not physically correspond to a single | |
1210 | * IOMMU device.. | |
1211 | */ | |
1212 | if (!dma_dev) | |
1213 | dma_dev = &pdev->dev; | |
1214 | ||
4d88a8a4 JC |
1215 | bus_set_iommu(&platform_bus_type, &rk_iommu_ops); |
1216 | ||
0f181d3c JC |
1217 | pm_runtime_enable(dev); |
1218 | ||
1aa55ca9 MZ |
1219 | i = 0; |
1220 | while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) { | |
1221 | if (irq < 0) | |
1222 | return irq; | |
1223 | ||
1224 | err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, | |
1225 | IRQF_SHARED, dev_name(dev), iommu); | |
1226 | if (err) { | |
1227 | pm_runtime_disable(dev); | |
1228 | goto err_remove_sysfs; | |
1229 | } | |
1230 | } | |
1231 | ||
f2e3a5f5 TF |
1232 | return 0; |
1233 | err_remove_sysfs: | |
1234 | iommu_device_sysfs_remove(&iommu->iommu); | |
57c26957 JC |
1235 | err_put_group: |
1236 | iommu_group_put(iommu->group); | |
f2e3a5f5 TF |
1237 | err_unprepare_clocks: |
1238 | clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); | |
c9d9f239 | 1239 | return err; |
c68a2921 DK |
1240 | } |
1241 | ||
1a4e90f2 MZ |
1242 | static void rk_iommu_shutdown(struct platform_device *pdev) |
1243 | { | |
74bc2abc HS |
1244 | struct rk_iommu *iommu = platform_get_drvdata(pdev); |
1245 | int i = 0, irq; | |
1246 | ||
1247 | while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) | |
1248 | devm_free_irq(iommu->dev, irq, iommu); | |
1249 | ||
0f181d3c JC |
1250 | pm_runtime_force_suspend(&pdev->dev); |
1251 | } | |
1a4e90f2 | 1252 | |
0f181d3c JC |
1253 | static int __maybe_unused rk_iommu_suspend(struct device *dev) |
1254 | { | |
1255 | struct rk_iommu *iommu = dev_get_drvdata(dev); | |
1256 | ||
1257 | if (!iommu->domain) | |
1258 | return 0; | |
1259 | ||
1260 | rk_iommu_disable(iommu); | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static int __maybe_unused rk_iommu_resume(struct device *dev) | |
1265 | { | |
1266 | struct rk_iommu *iommu = dev_get_drvdata(dev); | |
1267 | ||
1268 | if (!iommu->domain) | |
1269 | return 0; | |
1270 | ||
1271 | return rk_iommu_enable(iommu); | |
1a4e90f2 MZ |
1272 | } |
1273 | ||
0f181d3c JC |
1274 | static const struct dev_pm_ops rk_iommu_pm_ops = { |
1275 | SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) | |
1276 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1277 | pm_runtime_force_resume) | |
1278 | }; | |
1279 | ||
c68a2921 DK |
1280 | static const struct of_device_id rk_iommu_dt_ids[] = { |
1281 | { .compatible = "rockchip,iommu" }, | |
1282 | { /* sentinel */ } | |
1283 | }; | |
1284 | MODULE_DEVICE_TABLE(of, rk_iommu_dt_ids); | |
c68a2921 DK |
1285 | |
1286 | static struct platform_driver rk_iommu_driver = { | |
1287 | .probe = rk_iommu_probe, | |
1a4e90f2 | 1288 | .shutdown = rk_iommu_shutdown, |
c68a2921 DK |
1289 | .driver = { |
1290 | .name = "rk_iommu", | |
d9e7eb15 | 1291 | .of_match_table = rk_iommu_dt_ids, |
0f181d3c | 1292 | .pm = &rk_iommu_pm_ops, |
98b72b94 | 1293 | .suppress_bind_attrs = true, |
c68a2921 DK |
1294 | }, |
1295 | }; | |
1296 | ||
1297 | static int __init rk_iommu_init(void) | |
1298 | { | |
9176a303 | 1299 | return platform_driver_register(&rk_iommu_driver); |
c68a2921 | 1300 | } |
c68a2921 | 1301 | subsys_initcall(rk_iommu_init); |
c68a2921 DK |
1302 | |
1303 | MODULE_DESCRIPTION("IOMMU API for Rockchip"); | |
1304 | MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com> and Daniel Kurtz <djkurtz@chromium.org>"); | |
1305 | MODULE_ALIAS("platform:rockchip-iommu"); | |
1306 | MODULE_LICENSE("GPL v2"); |