Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
a9dcad5e HD |
16 | #include <linux/interrupt.h> |
17 | #include <linux/ioport.h> | |
a9dcad5e | 18 | #include <linux/platform_device.h> |
f626b52d | 19 | #include <linux/iommu.h> |
c8d35c84 | 20 | #include <linux/omap-iommu.h> |
f626b52d OBC |
21 | #include <linux/mutex.h> |
22 | #include <linux/spinlock.h> | |
ed1c7de2 | 23 | #include <linux/io.h> |
ebf7cda0 | 24 | #include <linux/pm_runtime.h> |
3c92748d FV |
25 | #include <linux/of.h> |
26 | #include <linux/of_iommu.h> | |
27 | #include <linux/of_irq.h> | |
7d682774 | 28 | #include <linux/of_platform.h> |
3ca9299e SA |
29 | #include <linux/regmap.h> |
30 | #include <linux/mfd/syscon.h> | |
a9dcad5e HD |
31 | |
32 | #include <asm/cacheflush.h> | |
33 | ||
2ab7c848 | 34 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 35 | |
2f7702af | 36 | #include "omap-iopgtable.h" |
ed1c7de2 | 37 | #include "omap-iommu.h" |
a9dcad5e | 38 | |
5acc97db SA |
39 | #define to_iommu(dev) \ |
40 | ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))) | |
41 | ||
66bc8cf3 OBC |
42 | /* bitmap of the page sizes currently supported */ |
43 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
44 | ||
7bd9e25f IY |
45 | #define MMU_LOCK_BASE_SHIFT 10 |
46 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
47 | #define MMU_LOCK_BASE(x) \ | |
48 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
49 | ||
50 | #define MMU_LOCK_VICT_SHIFT 4 | |
51 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
52 | #define MMU_LOCK_VICT(x) \ | |
53 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
54 | ||
a9dcad5e HD |
55 | static struct platform_driver omap_iommu_driver; |
56 | static struct kmem_cache *iopte_cachep; | |
57 | ||
8cf851e0 JR |
58 | /** |
59 | * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain | |
60 | * @dom: generic iommu domain handle | |
61 | **/ | |
62 | static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) | |
63 | { | |
64 | return container_of(dom, struct omap_iommu_domain, domain); | |
65 | } | |
66 | ||
a9dcad5e | 67 | /** |
6c32df43 | 68 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 69 | * @dev: client device |
a9dcad5e | 70 | **/ |
fabdbca8 | 71 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 72 | { |
fabdbca8 | 73 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
bd4396f0 SA |
74 | u32 *p = obj->ctx; |
75 | int i; | |
fabdbca8 | 76 | |
bd4396f0 SA |
77 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { |
78 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
79 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
80 | } | |
a9dcad5e | 81 | } |
6c32df43 | 82 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
83 | |
84 | /** | |
6c32df43 | 85 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 86 | * @dev: client device |
a9dcad5e | 87 | **/ |
fabdbca8 | 88 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 89 | { |
fabdbca8 | 90 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
bd4396f0 SA |
91 | u32 *p = obj->ctx; |
92 | int i; | |
fabdbca8 | 93 | |
bd4396f0 SA |
94 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { |
95 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
96 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
97 | } | |
a9dcad5e | 98 | } |
6c32df43 | 99 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e | 100 | |
3ca9299e SA |
101 | static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable) |
102 | { | |
103 | u32 val, mask; | |
104 | ||
105 | if (!obj->syscfg) | |
106 | return; | |
107 | ||
108 | mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT)); | |
109 | val = enable ? mask : 0; | |
110 | regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); | |
111 | } | |
112 | ||
bd4396f0 SA |
113 | static void __iommu_set_twl(struct omap_iommu *obj, bool on) |
114 | { | |
115 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
116 | ||
117 | if (on) | |
118 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | |
119 | else | |
120 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | |
121 | ||
122 | l &= ~MMU_CNTL_MASK; | |
123 | if (on) | |
124 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
125 | else | |
126 | l |= (MMU_CNTL_MMU_EN); | |
127 | ||
128 | iommu_write_reg(obj, l, MMU_CNTL); | |
129 | } | |
130 | ||
131 | static int omap2_iommu_enable(struct omap_iommu *obj) | |
132 | { | |
133 | u32 l, pa; | |
134 | ||
135 | if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | |
136 | return -EINVAL; | |
137 | ||
138 | pa = virt_to_phys(obj->iopgd); | |
139 | if (!IS_ALIGNED(pa, SZ_16K)) | |
140 | return -EINVAL; | |
141 | ||
142 | l = iommu_read_reg(obj, MMU_REVISION); | |
143 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
144 | (l >> 4) & 0xf, l & 0xf); | |
145 | ||
146 | iommu_write_reg(obj, pa, MMU_TTB); | |
147 | ||
3ca9299e SA |
148 | dra7_cfg_dspsys_mmu(obj, true); |
149 | ||
bd4396f0 SA |
150 | if (obj->has_bus_err_back) |
151 | iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); | |
152 | ||
153 | __iommu_set_twl(obj, true); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static void omap2_iommu_disable(struct omap_iommu *obj) | |
159 | { | |
160 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
161 | ||
162 | l &= ~MMU_CNTL_MASK; | |
163 | iommu_write_reg(obj, l, MMU_CNTL); | |
3ca9299e | 164 | dra7_cfg_dspsys_mmu(obj, false); |
bd4396f0 SA |
165 | |
166 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
167 | } | |
168 | ||
6c32df43 | 169 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
170 | { |
171 | int err; | |
72b15b6a | 172 | struct platform_device *pdev = to_platform_device(obj->dev); |
99cb9aee | 173 | struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); |
a9dcad5e | 174 | |
90e569c4 | 175 | if (pdata && pdata->deassert_reset) { |
72b15b6a ORL |
176 | err = pdata->deassert_reset(pdev, pdata->reset_name); |
177 | if (err) { | |
178 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
179 | return err; | |
180 | } | |
181 | } | |
182 | ||
ebf7cda0 | 183 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 184 | |
bd4396f0 | 185 | err = omap2_iommu_enable(obj); |
a9dcad5e | 186 | |
a9dcad5e HD |
187 | return err; |
188 | } | |
189 | ||
6c32df43 | 190 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 191 | { |
72b15b6a | 192 | struct platform_device *pdev = to_platform_device(obj->dev); |
99cb9aee | 193 | struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); |
72b15b6a | 194 | |
bd4396f0 | 195 | omap2_iommu_disable(obj); |
a9dcad5e | 196 | |
ebf7cda0 | 197 | pm_runtime_put_sync(obj->dev); |
72b15b6a | 198 | |
90e569c4 | 199 | if (pdata && pdata->assert_reset) |
72b15b6a | 200 | pdata->assert_reset(pdev, pdata->reset_name); |
a9dcad5e HD |
201 | } |
202 | ||
203 | /* | |
204 | * TLB operations | |
205 | */ | |
e1f23813 | 206 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e | 207 | { |
bd4396f0 SA |
208 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; |
209 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
210 | ||
211 | return cr->cam & mask; | |
a9dcad5e | 212 | } |
a9dcad5e HD |
213 | |
214 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
215 | { | |
bd4396f0 SA |
216 | u32 attr; |
217 | ||
218 | attr = e->mixed << 5; | |
219 | attr |= e->endian; | |
220 | attr |= e->elsz >> 3; | |
221 | attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || | |
222 | (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); | |
223 | return attr; | |
a9dcad5e HD |
224 | } |
225 | ||
6c32df43 | 226 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e | 227 | { |
bd4396f0 SA |
228 | u32 status, fault_addr; |
229 | ||
230 | status = iommu_read_reg(obj, MMU_IRQSTATUS); | |
231 | status &= MMU_IRQ_MASK; | |
232 | if (!status) { | |
233 | *da = 0; | |
234 | return 0; | |
235 | } | |
236 | ||
237 | fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); | |
238 | *da = fault_addr; | |
239 | ||
240 | iommu_write_reg(obj, status, MMU_IRQSTATUS); | |
241 | ||
242 | return status; | |
a9dcad5e HD |
243 | } |
244 | ||
69c2c196 | 245 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
246 | { |
247 | u32 val; | |
248 | ||
249 | val = iommu_read_reg(obj, MMU_LOCK); | |
250 | ||
251 | l->base = MMU_LOCK_BASE(val); | |
252 | l->vict = MMU_LOCK_VICT(val); | |
a9dcad5e HD |
253 | } |
254 | ||
69c2c196 | 255 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
256 | { |
257 | u32 val; | |
258 | ||
a9dcad5e HD |
259 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
260 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
261 | ||
262 | iommu_write_reg(obj, val, MMU_LOCK); | |
263 | } | |
264 | ||
6c32df43 | 265 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 266 | { |
bd4396f0 SA |
267 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); |
268 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
a9dcad5e HD |
269 | } |
270 | ||
6c32df43 | 271 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 272 | { |
bd4396f0 SA |
273 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); |
274 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
a9dcad5e HD |
275 | |
276 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
277 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
278 | } | |
279 | ||
37c2836c | 280 | /* only used in iotlb iteration for-loop */ |
69c2c196 | 281 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
282 | { |
283 | struct cr_regs cr; | |
284 | struct iotlb_lock l; | |
285 | ||
286 | iotlb_lock_get(obj, &l); | |
287 | l.vict = n; | |
288 | iotlb_lock_set(obj, &l); | |
289 | iotlb_read_cr(obj, &cr); | |
290 | ||
291 | return cr; | |
292 | } | |
293 | ||
bd4396f0 SA |
294 | #ifdef PREFETCH_IOTLB |
295 | static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, | |
296 | struct iotlb_entry *e) | |
297 | { | |
298 | struct cr_regs *cr; | |
299 | ||
300 | if (!e) | |
301 | return NULL; | |
302 | ||
303 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
304 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
305 | e->da); | |
306 | return ERR_PTR(-EINVAL); | |
307 | } | |
308 | ||
309 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
310 | if (!cr) | |
311 | return ERR_PTR(-ENOMEM); | |
312 | ||
313 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; | |
314 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; | |
315 | ||
316 | return cr; | |
317 | } | |
318 | ||
a9dcad5e HD |
319 | /** |
320 | * load_iotlb_entry - Set an iommu tlb entry | |
321 | * @obj: target iommu | |
322 | * @e: an iommu tlb entry info | |
323 | **/ | |
6c32df43 | 324 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 325 | { |
a9dcad5e HD |
326 | int err = 0; |
327 | struct iotlb_lock l; | |
328 | struct cr_regs *cr; | |
329 | ||
330 | if (!obj || !obj->nr_tlb_entries || !e) | |
331 | return -EINVAL; | |
332 | ||
ebf7cda0 | 333 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 334 | |
be6d8026 KH |
335 | iotlb_lock_get(obj, &l); |
336 | if (l.base == obj->nr_tlb_entries) { | |
337 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
338 | err = -EBUSY; |
339 | goto out; | |
340 | } | |
be6d8026 | 341 | if (!e->prsvd) { |
37c2836c HD |
342 | int i; |
343 | struct cr_regs tmp; | |
be6d8026 | 344 | |
37c2836c | 345 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
346 | if (!iotlb_cr_valid(&tmp)) |
347 | break; | |
37c2836c | 348 | |
be6d8026 KH |
349 | if (i == obj->nr_tlb_entries) { |
350 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
351 | err = -EBUSY; | |
352 | goto out; | |
353 | } | |
37c2836c HD |
354 | |
355 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
356 | } else { |
357 | l.vict = l.base; | |
358 | iotlb_lock_set(obj, &l); | |
359 | } | |
a9dcad5e HD |
360 | |
361 | cr = iotlb_alloc_cr(obj, e); | |
362 | if (IS_ERR(cr)) { | |
ebf7cda0 | 363 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
364 | return PTR_ERR(cr); |
365 | } | |
366 | ||
367 | iotlb_load_cr(obj, cr); | |
368 | kfree(cr); | |
369 | ||
be6d8026 KH |
370 | if (e->prsvd) |
371 | l.base++; | |
a9dcad5e HD |
372 | /* increment victim for next tlb load */ |
373 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 374 | l.vict = l.base; |
a9dcad5e HD |
375 | iotlb_lock_set(obj, &l); |
376 | out: | |
ebf7cda0 | 377 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
378 | return err; |
379 | } | |
a9dcad5e | 380 | |
5da14a47 OBC |
381 | #else /* !PREFETCH_IOTLB */ |
382 | ||
6c32df43 | 383 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
384 | { |
385 | return 0; | |
386 | } | |
387 | ||
388 | #endif /* !PREFETCH_IOTLB */ | |
389 | ||
6c32df43 | 390 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
391 | { |
392 | return load_iotlb_entry(obj, e); | |
393 | } | |
a9dcad5e HD |
394 | |
395 | /** | |
396 | * flush_iotlb_page - Clear an iommu tlb entry | |
397 | * @obj: target iommu | |
398 | * @da: iommu device virtual address | |
399 | * | |
400 | * Clear an iommu tlb entry which includes 'da' address. | |
401 | **/ | |
6c32df43 | 402 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 403 | { |
a9dcad5e | 404 | int i; |
37c2836c | 405 | struct cr_regs cr; |
a9dcad5e | 406 | |
ebf7cda0 | 407 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 408 | |
37c2836c | 409 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
410 | u32 start; |
411 | size_t bytes; | |
412 | ||
a9dcad5e HD |
413 | if (!iotlb_cr_valid(&cr)) |
414 | continue; | |
415 | ||
416 | start = iotlb_cr_to_virt(&cr); | |
417 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
418 | ||
419 | if ((start <= da) && (da < start + bytes)) { | |
420 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
421 | __func__, start, da, bytes); | |
0fa035e5 | 422 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 423 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 424 | break; |
a9dcad5e HD |
425 | } |
426 | } | |
ebf7cda0 | 427 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
428 | |
429 | if (i == obj->nr_tlb_entries) | |
430 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
431 | } | |
a9dcad5e HD |
432 | |
433 | /** | |
434 | * flush_iotlb_all - Clear all iommu tlb entries | |
435 | * @obj: target iommu | |
436 | **/ | |
6c32df43 | 437 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
438 | { |
439 | struct iotlb_lock l; | |
440 | ||
ebf7cda0 | 441 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
442 | |
443 | l.base = 0; | |
444 | l.vict = 0; | |
445 | iotlb_lock_set(obj, &l); | |
446 | ||
447 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
448 | ||
ebf7cda0 | 449 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 450 | } |
ddfa975a | 451 | |
a9dcad5e HD |
452 | /* |
453 | * H/W pagetable operations | |
454 | */ | |
455 | static void flush_iopgd_range(u32 *first, u32 *last) | |
456 | { | |
457 | /* FIXME: L2 cache should be taken care of if it exists */ | |
458 | do { | |
459 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
460 | : : "r" (first)); | |
461 | first += L1_CACHE_BYTES / sizeof(*first); | |
462 | } while (first <= last); | |
463 | } | |
464 | ||
465 | static void flush_iopte_range(u32 *first, u32 *last) | |
466 | { | |
467 | /* FIXME: L2 cache should be taken care of if it exists */ | |
468 | do { | |
469 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
470 | : : "r" (first)); | |
471 | first += L1_CACHE_BYTES / sizeof(*first); | |
472 | } while (first <= last); | |
473 | } | |
474 | ||
475 | static void iopte_free(u32 *iopte) | |
476 | { | |
477 | /* Note: freed iopte's must be clean ready for re-use */ | |
e28045ab ZZ |
478 | if (iopte) |
479 | kmem_cache_free(iopte_cachep, iopte); | |
a9dcad5e HD |
480 | } |
481 | ||
6c32df43 | 482 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
483 | { |
484 | u32 *iopte; | |
485 | ||
486 | /* a table has already existed */ | |
487 | if (*iopgd) | |
488 | goto pte_ready; | |
489 | ||
490 | /* | |
491 | * do the allocation outside the page table lock | |
492 | */ | |
493 | spin_unlock(&obj->page_table_lock); | |
494 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
495 | spin_lock(&obj->page_table_lock); | |
496 | ||
497 | if (!*iopgd) { | |
498 | if (!iopte) | |
499 | return ERR_PTR(-ENOMEM); | |
500 | ||
501 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
502 | flush_iopgd_range(iopgd, iopgd); | |
503 | ||
504 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
505 | } else { | |
506 | /* We raced, free the reduniovant table */ | |
507 | iopte_free(iopte); | |
508 | } | |
509 | ||
510 | pte_ready: | |
511 | iopte = iopte_offset(iopgd, da); | |
512 | ||
513 | dev_vdbg(obj->dev, | |
514 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
515 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
516 | ||
517 | return iopte; | |
518 | } | |
519 | ||
6c32df43 | 520 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
521 | { |
522 | u32 *iopgd = iopgd_offset(obj, da); | |
523 | ||
4abb7617 HD |
524 | if ((da | pa) & ~IOSECTION_MASK) { |
525 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
526 | __func__, da, pa, IOSECTION_SIZE); | |
527 | return -EINVAL; | |
528 | } | |
529 | ||
a9dcad5e HD |
530 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
531 | flush_iopgd_range(iopgd, iopgd); | |
532 | return 0; | |
533 | } | |
534 | ||
6c32df43 | 535 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
536 | { |
537 | u32 *iopgd = iopgd_offset(obj, da); | |
538 | int i; | |
539 | ||
4abb7617 HD |
540 | if ((da | pa) & ~IOSUPER_MASK) { |
541 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
542 | __func__, da, pa, IOSUPER_SIZE); | |
543 | return -EINVAL; | |
544 | } | |
545 | ||
a9dcad5e HD |
546 | for (i = 0; i < 16; i++) |
547 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
548 | flush_iopgd_range(iopgd, iopgd + 15); | |
549 | return 0; | |
550 | } | |
551 | ||
6c32df43 | 552 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
553 | { |
554 | u32 *iopgd = iopgd_offset(obj, da); | |
555 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
556 | ||
557 | if (IS_ERR(iopte)) | |
558 | return PTR_ERR(iopte); | |
559 | ||
560 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
561 | flush_iopte_range(iopte, iopte); | |
562 | ||
563 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
564 | __func__, da, pa, iopte, *iopte); | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
6c32df43 | 569 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
570 | { |
571 | u32 *iopgd = iopgd_offset(obj, da); | |
572 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
573 | int i; | |
574 | ||
4abb7617 HD |
575 | if ((da | pa) & ~IOLARGE_MASK) { |
576 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
577 | __func__, da, pa, IOLARGE_SIZE); | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
a9dcad5e HD |
581 | if (IS_ERR(iopte)) |
582 | return PTR_ERR(iopte); | |
583 | ||
584 | for (i = 0; i < 16; i++) | |
585 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
586 | flush_iopte_range(iopte, iopte + 15); | |
587 | return 0; | |
588 | } | |
589 | ||
6c32df43 OBC |
590 | static int |
591 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 592 | { |
6c32df43 | 593 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
594 | u32 prot; |
595 | int err; | |
596 | ||
597 | if (!obj || !e) | |
598 | return -EINVAL; | |
599 | ||
600 | switch (e->pgsz) { | |
601 | case MMU_CAM_PGSZ_16M: | |
602 | fn = iopgd_alloc_super; | |
603 | break; | |
604 | case MMU_CAM_PGSZ_1M: | |
605 | fn = iopgd_alloc_section; | |
606 | break; | |
607 | case MMU_CAM_PGSZ_64K: | |
608 | fn = iopte_alloc_large; | |
609 | break; | |
610 | case MMU_CAM_PGSZ_4K: | |
611 | fn = iopte_alloc_page; | |
612 | break; | |
613 | default: | |
614 | fn = NULL; | |
a9dcad5e HD |
615 | break; |
616 | } | |
617 | ||
7c1ab600 SA |
618 | if (WARN_ON(!fn)) |
619 | return -EINVAL; | |
620 | ||
a9dcad5e HD |
621 | prot = get_iopte_attr(e); |
622 | ||
623 | spin_lock(&obj->page_table_lock); | |
624 | err = fn(obj, e->da, e->pa, prot); | |
625 | spin_unlock(&obj->page_table_lock); | |
626 | ||
627 | return err; | |
628 | } | |
629 | ||
630 | /** | |
6c32df43 | 631 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
632 | * @obj: target iommu |
633 | * @e: an iommu tlb entry info | |
634 | **/ | |
4899a563 SA |
635 | static int |
636 | omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e HD |
637 | { |
638 | int err; | |
639 | ||
640 | flush_iotlb_page(obj, e->da); | |
641 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 642 | if (!err) |
5da14a47 | 643 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
644 | return err; |
645 | } | |
a9dcad5e HD |
646 | |
647 | /** | |
648 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
649 | * @obj: target iommu | |
650 | * @da: iommu device virtual address | |
651 | * @ppgd: iommu pgd entry pointer to be returned | |
652 | * @ppte: iommu pte entry pointer to be returned | |
653 | **/ | |
e1f23813 OBC |
654 | static void |
655 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
656 | { |
657 | u32 *iopgd, *iopte = NULL; | |
658 | ||
659 | iopgd = iopgd_offset(obj, da); | |
660 | if (!*iopgd) | |
661 | goto out; | |
662 | ||
a1a54456 | 663 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
664 | iopte = iopte_offset(iopgd, da); |
665 | out: | |
666 | *ppgd = iopgd; | |
667 | *ppte = iopte; | |
668 | } | |
a9dcad5e | 669 | |
6c32df43 | 670 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
671 | { |
672 | size_t bytes; | |
673 | u32 *iopgd = iopgd_offset(obj, da); | |
674 | int nent = 1; | |
675 | ||
676 | if (!*iopgd) | |
677 | return 0; | |
678 | ||
a1a54456 | 679 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
680 | int i; |
681 | u32 *iopte = iopte_offset(iopgd, da); | |
682 | ||
683 | bytes = IOPTE_SIZE; | |
684 | if (*iopte & IOPTE_LARGE) { | |
685 | nent *= 16; | |
686 | /* rewind to the 1st entry */ | |
c127c7dc | 687 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
688 | } |
689 | bytes *= nent; | |
690 | memset(iopte, 0, nent * sizeof(*iopte)); | |
691 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
692 | ||
693 | /* | |
694 | * do table walk to check if this table is necessary or not | |
695 | */ | |
696 | iopte = iopte_offset(iopgd, 0); | |
697 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
698 | if (iopte[i]) | |
699 | goto out; | |
700 | ||
701 | iopte_free(iopte); | |
702 | nent = 1; /* for the next L1 entry */ | |
703 | } else { | |
704 | bytes = IOPGD_SIZE; | |
dcc730dc | 705 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
706 | nent *= 16; |
707 | /* rewind to the 1st entry */ | |
8d33ea58 | 708 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
709 | } |
710 | bytes *= nent; | |
711 | } | |
712 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
713 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
714 | out: | |
715 | return bytes; | |
716 | } | |
717 | ||
718 | /** | |
719 | * iopgtable_clear_entry - Remove an iommu pte entry | |
720 | * @obj: target iommu | |
721 | * @da: iommu device virtual address | |
722 | **/ | |
6c32df43 | 723 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
724 | { |
725 | size_t bytes; | |
726 | ||
727 | spin_lock(&obj->page_table_lock); | |
728 | ||
729 | bytes = iopgtable_clear_entry_core(obj, da); | |
730 | flush_iotlb_page(obj, da); | |
731 | ||
732 | spin_unlock(&obj->page_table_lock); | |
733 | ||
734 | return bytes; | |
735 | } | |
a9dcad5e | 736 | |
6c32df43 | 737 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
738 | { |
739 | int i; | |
740 | ||
741 | spin_lock(&obj->page_table_lock); | |
742 | ||
743 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
744 | u32 da; | |
745 | u32 *iopgd; | |
746 | ||
747 | da = i << IOPGD_SHIFT; | |
748 | iopgd = iopgd_offset(obj, da); | |
749 | ||
750 | if (!*iopgd) | |
751 | continue; | |
752 | ||
a1a54456 | 753 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
754 | iopte_free(iopte_offset(iopgd, 0)); |
755 | ||
756 | *iopgd = 0; | |
757 | flush_iopgd_range(iopgd, iopgd); | |
758 | } | |
759 | ||
760 | flush_iotlb_all(obj); | |
761 | ||
762 | spin_unlock(&obj->page_table_lock); | |
763 | } | |
764 | ||
765 | /* | |
766 | * Device IOMMU generic operations | |
767 | */ | |
768 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
769 | { | |
d594f1f3 | 770 | u32 da, errs; |
a9dcad5e | 771 | u32 *iopgd, *iopte; |
6c32df43 | 772 | struct omap_iommu *obj = data; |
e7f10f02 | 773 | struct iommu_domain *domain = obj->domain; |
8cf851e0 | 774 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
a9dcad5e | 775 | |
2088ecba | 776 | if (!omap_domain->iommu_dev) |
a9dcad5e HD |
777 | return IRQ_NONE; |
778 | ||
d594f1f3 | 779 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
780 | if (errs == 0) |
781 | return IRQ_HANDLED; | |
d594f1f3 DC |
782 | |
783 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 784 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
785 | return IRQ_HANDLED; |
786 | ||
37b29810 HD |
787 | iommu_disable(obj); |
788 | ||
a9dcad5e HD |
789 | iopgd = iopgd_offset(obj, da); |
790 | ||
a1a54456 | 791 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f | 792 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
5835b6a6 | 793 | obj->name, errs, da, iopgd, *iopgd); |
a9dcad5e HD |
794 | return IRQ_NONE; |
795 | } | |
796 | ||
797 | iopte = iopte_offset(iopgd, da); | |
798 | ||
b6c2e09f | 799 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
5835b6a6 | 800 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); |
a9dcad5e HD |
801 | |
802 | return IRQ_NONE; | |
803 | } | |
804 | ||
805 | static int device_match_by_alias(struct device *dev, void *data) | |
806 | { | |
6c32df43 | 807 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
808 | const char *name = data; |
809 | ||
810 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
811 | ||
812 | return strcmp(obj->name, name) == 0; | |
813 | } | |
814 | ||
815 | /** | |
f626b52d | 816 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 817 | * @name: name of target omap iommu device |
f626b52d | 818 | * @iopgd: page table |
a9dcad5e | 819 | **/ |
fabdbca8 | 820 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e | 821 | { |
7ee08b9e | 822 | int err; |
fabdbca8 OBC |
823 | struct device *dev; |
824 | struct omap_iommu *obj; | |
825 | ||
5835b6a6 SA |
826 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, |
827 | device_match_by_alias); | |
fabdbca8 | 828 | if (!dev) |
7ee08b9e | 829 | return ERR_PTR(-ENODEV); |
fabdbca8 OBC |
830 | |
831 | obj = to_iommu(dev); | |
a9dcad5e | 832 | |
f626b52d | 833 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 834 | |
f626b52d OBC |
835 | obj->iopgd = iopgd; |
836 | err = iommu_enable(obj); | |
837 | if (err) | |
838 | goto err_enable; | |
839 | flush_iotlb_all(obj); | |
840 | ||
f626b52d | 841 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
842 | |
843 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
844 | return obj; | |
845 | ||
a9dcad5e | 846 | err_enable: |
f626b52d | 847 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
848 | return ERR_PTR(err); |
849 | } | |
a9dcad5e HD |
850 | |
851 | /** | |
f626b52d | 852 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
853 | * @obj: target iommu |
854 | **/ | |
6c32df43 | 855 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 856 | { |
acf9d467 | 857 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
858 | return; |
859 | ||
f626b52d | 860 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 861 | |
2088ecba | 862 | iommu_disable(obj); |
f626b52d | 863 | obj->iopgd = NULL; |
d594f1f3 | 864 | |
f626b52d | 865 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 866 | |
a9dcad5e | 867 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 868 | } |
d594f1f3 | 869 | |
3ca9299e SA |
870 | static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev, |
871 | struct omap_iommu *obj) | |
872 | { | |
873 | struct device_node *np = pdev->dev.of_node; | |
874 | int ret; | |
875 | ||
876 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
877 | return 0; | |
878 | ||
879 | if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) { | |
880 | dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n"); | |
881 | return -EINVAL; | |
882 | } | |
883 | ||
884 | obj->syscfg = | |
885 | syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig"); | |
886 | if (IS_ERR(obj->syscfg)) { | |
887 | /* can fail with -EPROBE_DEFER */ | |
888 | ret = PTR_ERR(obj->syscfg); | |
889 | return ret; | |
890 | } | |
891 | ||
892 | if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1, | |
893 | &obj->id)) { | |
894 | dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n"); | |
895 | return -EINVAL; | |
896 | } | |
897 | ||
898 | if (obj->id != 0 && obj->id != 1) { | |
899 | dev_err(&pdev->dev, "invalid IOMMU instance id\n"); | |
900 | return -EINVAL; | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
a9dcad5e HD |
906 | /* |
907 | * OMAP Device MMU(IOMMU) detection | |
908 | */ | |
d34d6517 | 909 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
910 | { |
911 | int err = -ENODEV; | |
a9dcad5e | 912 | int irq; |
6c32df43 | 913 | struct omap_iommu *obj; |
a9dcad5e | 914 | struct resource *res; |
3c92748d | 915 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 916 | |
49a57ef7 SA |
917 | if (!of) { |
918 | pr_err("%s: only DT-based devices are supported\n", __func__); | |
919 | return -ENODEV; | |
920 | } | |
921 | ||
f129b3df | 922 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
923 | if (!obj) |
924 | return -ENOMEM; | |
925 | ||
49a57ef7 SA |
926 | obj->name = dev_name(&pdev->dev); |
927 | obj->nr_tlb_entries = 32; | |
928 | err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries); | |
929 | if (err && err != -EINVAL) | |
930 | return err; | |
931 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
932 | return -EINVAL; | |
933 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) | |
934 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d | 935 | |
a9dcad5e HD |
936 | obj->dev = &pdev->dev; |
937 | obj->ctx = (void *)obj + sizeof(*obj); | |
938 | ||
f626b52d | 939 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 940 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
941 | |
942 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
943 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
944 | if (IS_ERR(obj->regbase)) | |
945 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 946 | |
3ca9299e SA |
947 | err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj); |
948 | if (err) | |
949 | return err; | |
950 | ||
a9dcad5e | 951 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
952 | if (irq < 0) |
953 | return -ENODEV; | |
954 | ||
955 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
956 | dev_name(obj->dev), obj); | |
a9dcad5e | 957 | if (err < 0) |
f129b3df | 958 | return err; |
a9dcad5e HD |
959 | platform_set_drvdata(pdev, obj); |
960 | ||
ebf7cda0 ORL |
961 | pm_runtime_irq_safe(obj->dev); |
962 | pm_runtime_enable(obj->dev); | |
963 | ||
61c75352 SA |
964 | omap_iommu_debugfs_add(obj); |
965 | ||
a9dcad5e HD |
966 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
967 | return 0; | |
a9dcad5e HD |
968 | } |
969 | ||
d34d6517 | 970 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 971 | { |
6c32df43 | 972 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 973 | |
61c75352 | 974 | omap_iommu_debugfs_remove(obj); |
a9dcad5e | 975 | |
ebf7cda0 ORL |
976 | pm_runtime_disable(obj->dev); |
977 | ||
a9dcad5e | 978 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
979 | return 0; |
980 | } | |
981 | ||
d943b0ff | 982 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
983 | { .compatible = "ti,omap2-iommu" }, |
984 | { .compatible = "ti,omap4-iommu" }, | |
985 | { .compatible = "ti,dra7-iommu" }, | |
3ca9299e | 986 | { .compatible = "ti,dra7-dsp-iommu" }, |
3c92748d FV |
987 | {}, |
988 | }; | |
3c92748d | 989 | |
a9dcad5e HD |
990 | static struct platform_driver omap_iommu_driver = { |
991 | .probe = omap_iommu_probe, | |
d34d6517 | 992 | .remove = omap_iommu_remove, |
a9dcad5e HD |
993 | .driver = { |
994 | .name = "omap-iommu", | |
3c92748d | 995 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
996 | }, |
997 | }; | |
998 | ||
999 | static void iopte_cachep_ctor(void *iopte) | |
1000 | { | |
1001 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1002 | } | |
1003 | ||
286f600b | 1004 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1005 | { |
1006 | memset(e, 0, sizeof(*e)); | |
1007 | ||
1008 | e->da = da; | |
1009 | e->pa = pa; | |
d760e3e0 | 1010 | e->valid = MMU_CAM_V; |
286f600b LP |
1011 | e->pgsz = pgsz; |
1012 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1013 | e->elsz = MMU_RAM_ELSZ_8; | |
1014 | e->mixed = 0; | |
ed1c7de2 TL |
1015 | |
1016 | return iopgsz_to_bytes(e->pgsz); | |
1017 | } | |
1018 | ||
f626b52d | 1019 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5835b6a6 | 1020 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d | 1021 | { |
8cf851e0 | 1022 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
6c32df43 | 1023 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1024 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1025 | struct iotlb_entry e; |
1026 | int omap_pgsz; | |
286f600b | 1027 | u32 ret; |
f626b52d | 1028 | |
f626b52d OBC |
1029 | omap_pgsz = bytes_to_iopgsz(bytes); |
1030 | if (omap_pgsz < 0) { | |
1031 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | ||
1d7f449c | 1035 | dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes); |
f626b52d | 1036 | |
286f600b | 1037 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1038 | |
6c32df43 | 1039 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1040 | if (ret) |
6c32df43 | 1041 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1042 | |
b4550d41 | 1043 | return ret; |
f626b52d OBC |
1044 | } |
1045 | ||
5009065d | 1046 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
5835b6a6 | 1047 | size_t size) |
f626b52d | 1048 | { |
8cf851e0 | 1049 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
6c32df43 | 1050 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1051 | struct device *dev = oiommu->dev; |
f626b52d | 1052 | |
5009065d | 1053 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1054 | |
5009065d | 1055 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1056 | } |
1057 | ||
1058 | static int | |
1059 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1060 | { | |
8cf851e0 | 1061 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
6c32df43 | 1062 | struct omap_iommu *oiommu; |
fabdbca8 | 1063 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1064 | int ret = 0; |
1065 | ||
e3f595b9 SA |
1066 | if (!arch_data || !arch_data->name) { |
1067 | dev_err(dev, "device doesn't have an associated iommu\n"); | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
f626b52d OBC |
1071 | spin_lock(&omap_domain->lock); |
1072 | ||
1073 | /* only a single device is supported per domain for now */ | |
1074 | if (omap_domain->iommu_dev) { | |
1075 | dev_err(dev, "iommu domain is already attached\n"); | |
1076 | ret = -EBUSY; | |
1077 | goto out; | |
1078 | } | |
1079 | ||
1080 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1081 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1082 | if (IS_ERR(oiommu)) { |
1083 | ret = PTR_ERR(oiommu); | |
1084 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1085 | goto out; | |
1086 | } | |
1087 | ||
fabdbca8 | 1088 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1089 | omap_domain->dev = dev; |
e7f10f02 | 1090 | oiommu->domain = domain; |
f626b52d OBC |
1091 | |
1092 | out: | |
1093 | spin_unlock(&omap_domain->lock); | |
1094 | return ret; | |
1095 | } | |
1096 | ||
803b5277 | 1097 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
5835b6a6 | 1098 | struct device *dev) |
f626b52d | 1099 | { |
fabdbca8 | 1100 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1101 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1102 | |
1103 | /* only a single device is supported per domain for now */ | |
1104 | if (omap_domain->iommu_dev != oiommu) { | |
1105 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1106 | return; |
f626b52d OBC |
1107 | } |
1108 | ||
1109 | iopgtable_clear_entry_all(oiommu); | |
1110 | ||
1111 | omap_iommu_detach(oiommu); | |
1112 | ||
fabdbca8 | 1113 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 | 1114 | omap_domain->dev = NULL; |
f24d9ad3 | 1115 | oiommu->domain = NULL; |
803b5277 | 1116 | } |
f626b52d | 1117 | |
803b5277 | 1118 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
5835b6a6 | 1119 | struct device *dev) |
803b5277 | 1120 | { |
8cf851e0 | 1121 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
803b5277 ORL |
1122 | |
1123 | spin_lock(&omap_domain->lock); | |
1124 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1125 | spin_unlock(&omap_domain->lock); |
1126 | } | |
1127 | ||
8cf851e0 | 1128 | static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) |
f626b52d OBC |
1129 | { |
1130 | struct omap_iommu_domain *omap_domain; | |
1131 | ||
8cf851e0 JR |
1132 | if (type != IOMMU_DOMAIN_UNMANAGED) |
1133 | return NULL; | |
1134 | ||
f626b52d | 1135 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); |
99ee98d6 | 1136 | if (!omap_domain) |
f626b52d | 1137 | goto out; |
f626b52d OBC |
1138 | |
1139 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
99ee98d6 | 1140 | if (!omap_domain->pgtable) |
f626b52d | 1141 | goto fail_nomem; |
f626b52d OBC |
1142 | |
1143 | /* | |
1144 | * should never fail, but please keep this around to ensure | |
1145 | * we keep the hardware happy | |
1146 | */ | |
433c434a SA |
1147 | if (WARN_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE))) |
1148 | goto fail_align; | |
f626b52d OBC |
1149 | |
1150 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1151 | spin_lock_init(&omap_domain->lock); | |
1152 | ||
8cf851e0 JR |
1153 | omap_domain->domain.geometry.aperture_start = 0; |
1154 | omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; | |
1155 | omap_domain->domain.geometry.force_aperture = true; | |
f626b52d | 1156 | |
8cf851e0 | 1157 | return &omap_domain->domain; |
f626b52d | 1158 | |
433c434a SA |
1159 | fail_align: |
1160 | kfree(omap_domain->pgtable); | |
f626b52d OBC |
1161 | fail_nomem: |
1162 | kfree(omap_domain); | |
1163 | out: | |
8cf851e0 | 1164 | return NULL; |
f626b52d OBC |
1165 | } |
1166 | ||
8cf851e0 | 1167 | static void omap_iommu_domain_free(struct iommu_domain *domain) |
f626b52d | 1168 | { |
8cf851e0 | 1169 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
f626b52d | 1170 | |
803b5277 ORL |
1171 | /* |
1172 | * An iommu device is still attached | |
1173 | * (currently, only one device can be attached) ? | |
1174 | */ | |
1175 | if (omap_domain->iommu_dev) | |
1176 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1177 | ||
f626b52d OBC |
1178 | kfree(omap_domain->pgtable); |
1179 | kfree(omap_domain); | |
1180 | } | |
1181 | ||
1182 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
5835b6a6 | 1183 | dma_addr_t da) |
f626b52d | 1184 | { |
8cf851e0 | 1185 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
6c32df43 | 1186 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1187 | struct device *dev = oiommu->dev; |
1188 | u32 *pgd, *pte; | |
1189 | phys_addr_t ret = 0; | |
1190 | ||
1191 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1192 | ||
1193 | if (pte) { | |
1194 | if (iopte_is_small(*pte)) | |
1195 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1196 | else if (iopte_is_large(*pte)) | |
1197 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1198 | else | |
2abfcfbc | 1199 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
5835b6a6 | 1200 | (unsigned long long)da); |
f626b52d OBC |
1201 | } else { |
1202 | if (iopgd_is_section(*pgd)) | |
1203 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1204 | else if (iopgd_is_super(*pgd)) | |
1205 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1206 | else | |
2abfcfbc | 1207 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
5835b6a6 | 1208 | (unsigned long long)da); |
f626b52d OBC |
1209 | } |
1210 | ||
1211 | return ret; | |
1212 | } | |
1213 | ||
07a02030 LP |
1214 | static int omap_iommu_add_device(struct device *dev) |
1215 | { | |
1216 | struct omap_iommu_arch_data *arch_data; | |
1217 | struct device_node *np; | |
7d682774 | 1218 | struct platform_device *pdev; |
07a02030 LP |
1219 | |
1220 | /* | |
1221 | * Allocate the archdata iommu structure for DT-based devices. | |
1222 | * | |
1223 | * TODO: Simplify this when removing non-DT support completely from the | |
1224 | * IOMMU users. | |
1225 | */ | |
1226 | if (!dev->of_node) | |
1227 | return 0; | |
1228 | ||
1229 | np = of_parse_phandle(dev->of_node, "iommus", 0); | |
1230 | if (!np) | |
1231 | return 0; | |
1232 | ||
7d682774 SA |
1233 | pdev = of_find_device_by_node(np); |
1234 | if (WARN_ON(!pdev)) { | |
1235 | of_node_put(np); | |
1236 | return -EINVAL; | |
1237 | } | |
1238 | ||
07a02030 LP |
1239 | arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); |
1240 | if (!arch_data) { | |
1241 | of_node_put(np); | |
1242 | return -ENOMEM; | |
1243 | } | |
1244 | ||
7d682774 | 1245 | arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL); |
07a02030 LP |
1246 | dev->archdata.iommu = arch_data; |
1247 | ||
1248 | of_node_put(np); | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static void omap_iommu_remove_device(struct device *dev) | |
1254 | { | |
1255 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1256 | ||
1257 | if (!dev->of_node || !arch_data) | |
1258 | return; | |
1259 | ||
1260 | kfree(arch_data->name); | |
1261 | kfree(arch_data); | |
1262 | } | |
1263 | ||
b22f6434 | 1264 | static const struct iommu_ops omap_iommu_ops = { |
8cf851e0 JR |
1265 | .domain_alloc = omap_iommu_domain_alloc, |
1266 | .domain_free = omap_iommu_domain_free, | |
f626b52d OBC |
1267 | .attach_dev = omap_iommu_attach_dev, |
1268 | .detach_dev = omap_iommu_detach_dev, | |
1269 | .map = omap_iommu_map, | |
1270 | .unmap = omap_iommu_unmap, | |
315786eb | 1271 | .map_sg = default_iommu_map_sg, |
f626b52d | 1272 | .iova_to_phys = omap_iommu_iova_to_phys, |
07a02030 LP |
1273 | .add_device = omap_iommu_add_device, |
1274 | .remove_device = omap_iommu_remove_device, | |
66bc8cf3 | 1275 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1276 | }; |
1277 | ||
a9dcad5e HD |
1278 | static int __init omap_iommu_init(void) |
1279 | { | |
1280 | struct kmem_cache *p; | |
1281 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1282 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
f938aab2 | 1283 | struct device_node *np; |
abaa7e5b | 1284 | int ret; |
f938aab2 TR |
1285 | |
1286 | np = of_find_matching_node(NULL, omap_iommu_of_match); | |
1287 | if (!np) | |
1288 | return 0; | |
1289 | ||
1290 | of_node_put(np); | |
a9dcad5e HD |
1291 | |
1292 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1293 | iopte_cachep_ctor); | |
1294 | if (!p) | |
1295 | return -ENOMEM; | |
1296 | iopte_cachep = p; | |
1297 | ||
61c75352 SA |
1298 | omap_iommu_debugfs_init(); |
1299 | ||
abaa7e5b SA |
1300 | ret = platform_driver_register(&omap_iommu_driver); |
1301 | if (ret) { | |
1302 | pr_err("%s: failed to register driver\n", __func__); | |
1303 | goto fail_driver; | |
1304 | } | |
1305 | ||
1306 | ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops); | |
1307 | if (ret) | |
1308 | goto fail_bus; | |
1309 | ||
1310 | return 0; | |
1311 | ||
1312 | fail_bus: | |
1313 | platform_driver_unregister(&omap_iommu_driver); | |
1314 | fail_driver: | |
1315 | kmem_cache_destroy(iopte_cachep); | |
1316 | return ret; | |
a9dcad5e | 1317 | } |
435792d9 | 1318 | subsys_initcall(omap_iommu_init); |
0cdbf727 | 1319 | /* must be ready before omap3isp is probed */ |