Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
f626b52d | 21 | #include <linux/iommu.h> |
c8d35c84 | 22 | #include <linux/omap-iommu.h> |
f626b52d OBC |
23 | #include <linux/mutex.h> |
24 | #include <linux/spinlock.h> | |
ed1c7de2 | 25 | #include <linux/io.h> |
a9dcad5e HD |
26 | |
27 | #include <asm/cacheflush.h> | |
28 | ||
ce491cf8 | 29 | #include <plat/iommu.h> |
a9dcad5e | 30 | |
2f7702af | 31 | #include "omap-iopgtable.h" |
ed1c7de2 | 32 | #include "omap-iommu.h" |
a9dcad5e | 33 | |
37c2836c HD |
34 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
35 | for (__i = 0; \ | |
36 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
37 | __i++) | |
38 | ||
66bc8cf3 OBC |
39 | /* bitmap of the page sizes currently supported */ |
40 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
41 | ||
f626b52d OBC |
42 | /** |
43 | * struct omap_iommu_domain - omap iommu domain | |
44 | * @pgtable: the page table | |
45 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
46 | * iommu device can be attached for now. | |
803b5277 | 47 | * @dev: Device using this domain. |
f626b52d OBC |
48 | * @lock: domain lock, should be taken when attaching/detaching |
49 | */ | |
50 | struct omap_iommu_domain { | |
51 | u32 *pgtable; | |
6c32df43 | 52 | struct omap_iommu *iommu_dev; |
803b5277 | 53 | struct device *dev; |
f626b52d OBC |
54 | spinlock_t lock; |
55 | }; | |
56 | ||
7bd9e25f IY |
57 | #define MMU_LOCK_BASE_SHIFT 10 |
58 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
59 | #define MMU_LOCK_BASE(x) \ | |
60 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
61 | ||
62 | #define MMU_LOCK_VICT_SHIFT 4 | |
63 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
64 | #define MMU_LOCK_VICT(x) \ | |
65 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
66 | ||
67 | struct iotlb_lock { | |
68 | short base; | |
69 | short vict; | |
70 | }; | |
71 | ||
a9dcad5e HD |
72 | /* accommodate the difference between omap1 and omap2/3 */ |
73 | static const struct iommu_functions *arch_iommu; | |
74 | ||
75 | static struct platform_driver omap_iommu_driver; | |
76 | static struct kmem_cache *iopte_cachep; | |
77 | ||
78 | /** | |
6c32df43 | 79 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
80 | * @ops: a pointer to architecture specific iommu functions |
81 | * | |
82 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
83 | * omap series. This interface installs such an iommu algorighm. | |
84 | **/ | |
6c32df43 | 85 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
86 | { |
87 | if (arch_iommu) | |
88 | return -EBUSY; | |
89 | ||
90 | arch_iommu = ops; | |
91 | return 0; | |
92 | } | |
6c32df43 | 93 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
94 | |
95 | /** | |
6c32df43 | 96 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
97 | * @ops: a pointer to architecture specific iommu functions |
98 | * | |
99 | * This interface uninstalls the iommu algorighm installed previously. | |
100 | **/ | |
6c32df43 | 101 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
102 | { |
103 | if (arch_iommu != ops) | |
104 | pr_err("%s: not your arch\n", __func__); | |
105 | ||
106 | arch_iommu = NULL; | |
107 | } | |
6c32df43 | 108 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
109 | |
110 | /** | |
6c32df43 | 111 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 112 | * @dev: client device |
a9dcad5e | 113 | **/ |
fabdbca8 | 114 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 115 | { |
fabdbca8 OBC |
116 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
117 | ||
a9dcad5e HD |
118 | arch_iommu->save_ctx(obj); |
119 | } | |
6c32df43 | 120 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
121 | |
122 | /** | |
6c32df43 | 123 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 124 | * @dev: client device |
a9dcad5e | 125 | **/ |
fabdbca8 | 126 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 127 | { |
fabdbca8 OBC |
128 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
129 | ||
a9dcad5e HD |
130 | arch_iommu->restore_ctx(obj); |
131 | } | |
6c32df43 | 132 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
133 | |
134 | /** | |
6c32df43 | 135 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 136 | **/ |
6c32df43 | 137 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
138 | { |
139 | return arch_iommu->version; | |
140 | } | |
6c32df43 | 141 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 142 | |
6c32df43 | 143 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
144 | { |
145 | int err; | |
146 | ||
147 | if (!obj) | |
148 | return -EINVAL; | |
149 | ||
ef4815ab MH |
150 | if (!arch_iommu) |
151 | return -ENODEV; | |
152 | ||
a9dcad5e HD |
153 | clk_enable(obj->clk); |
154 | ||
155 | err = arch_iommu->enable(obj); | |
156 | ||
157 | clk_disable(obj->clk); | |
158 | return err; | |
159 | } | |
160 | ||
6c32df43 | 161 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e HD |
162 | { |
163 | if (!obj) | |
164 | return; | |
165 | ||
166 | clk_enable(obj->clk); | |
167 | ||
168 | arch_iommu->disable(obj); | |
169 | ||
170 | clk_disable(obj->clk); | |
171 | } | |
172 | ||
173 | /* | |
174 | * TLB operations | |
175 | */ | |
6c32df43 | 176 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
177 | { |
178 | BUG_ON(!cr || !e); | |
179 | ||
180 | arch_iommu->cr_to_e(cr, e); | |
181 | } | |
6c32df43 | 182 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
183 | |
184 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
185 | { | |
186 | if (!cr) | |
187 | return -EINVAL; | |
188 | ||
189 | return arch_iommu->cr_valid(cr); | |
190 | } | |
191 | ||
6c32df43 | 192 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
193 | struct iotlb_entry *e) |
194 | { | |
195 | if (!e) | |
196 | return NULL; | |
197 | ||
198 | return arch_iommu->alloc_cr(obj, e); | |
199 | } | |
200 | ||
e1f23813 | 201 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
202 | { |
203 | return arch_iommu->cr_to_virt(cr); | |
204 | } | |
a9dcad5e HD |
205 | |
206 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
207 | { | |
208 | return arch_iommu->get_pte_attr(e); | |
209 | } | |
210 | ||
6c32df43 | 211 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
212 | { |
213 | return arch_iommu->fault_isr(obj, da); | |
214 | } | |
215 | ||
6c32df43 | 216 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
217 | { |
218 | u32 val; | |
219 | ||
220 | val = iommu_read_reg(obj, MMU_LOCK); | |
221 | ||
222 | l->base = MMU_LOCK_BASE(val); | |
223 | l->vict = MMU_LOCK_VICT(val); | |
224 | ||
a9dcad5e HD |
225 | } |
226 | ||
6c32df43 | 227 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
228 | { |
229 | u32 val; | |
230 | ||
a9dcad5e HD |
231 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
232 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
233 | ||
234 | iommu_write_reg(obj, val, MMU_LOCK); | |
235 | } | |
236 | ||
6c32df43 | 237 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
238 | { |
239 | arch_iommu->tlb_read_cr(obj, cr); | |
240 | } | |
241 | ||
6c32df43 | 242 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
243 | { |
244 | arch_iommu->tlb_load_cr(obj, cr); | |
245 | ||
246 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
247 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
248 | } | |
249 | ||
250 | /** | |
251 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
252 | * @obj: target iommu | |
253 | * @cr: contents of cam and ram register | |
254 | * @buf: output buffer | |
255 | **/ | |
6c32df43 | 256 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
257 | char *buf) |
258 | { | |
259 | BUG_ON(!cr || !buf); | |
260 | ||
261 | return arch_iommu->dump_cr(obj, cr, buf); | |
262 | } | |
263 | ||
37c2836c | 264 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 265 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
266 | { |
267 | struct cr_regs cr; | |
268 | struct iotlb_lock l; | |
269 | ||
270 | iotlb_lock_get(obj, &l); | |
271 | l.vict = n; | |
272 | iotlb_lock_set(obj, &l); | |
273 | iotlb_read_cr(obj, &cr); | |
274 | ||
275 | return cr; | |
276 | } | |
277 | ||
a9dcad5e HD |
278 | /** |
279 | * load_iotlb_entry - Set an iommu tlb entry | |
280 | * @obj: target iommu | |
281 | * @e: an iommu tlb entry info | |
282 | **/ | |
5da14a47 | 283 | #ifdef PREFETCH_IOTLB |
6c32df43 | 284 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 285 | { |
a9dcad5e HD |
286 | int err = 0; |
287 | struct iotlb_lock l; | |
288 | struct cr_regs *cr; | |
289 | ||
290 | if (!obj || !obj->nr_tlb_entries || !e) | |
291 | return -EINVAL; | |
292 | ||
293 | clk_enable(obj->clk); | |
294 | ||
be6d8026 KH |
295 | iotlb_lock_get(obj, &l); |
296 | if (l.base == obj->nr_tlb_entries) { | |
297 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
298 | err = -EBUSY; |
299 | goto out; | |
300 | } | |
be6d8026 | 301 | if (!e->prsvd) { |
37c2836c HD |
302 | int i; |
303 | struct cr_regs tmp; | |
be6d8026 | 304 | |
37c2836c | 305 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
306 | if (!iotlb_cr_valid(&tmp)) |
307 | break; | |
37c2836c | 308 | |
be6d8026 KH |
309 | if (i == obj->nr_tlb_entries) { |
310 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
311 | err = -EBUSY; | |
312 | goto out; | |
313 | } | |
37c2836c HD |
314 | |
315 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
316 | } else { |
317 | l.vict = l.base; | |
318 | iotlb_lock_set(obj, &l); | |
319 | } | |
a9dcad5e HD |
320 | |
321 | cr = iotlb_alloc_cr(obj, e); | |
322 | if (IS_ERR(cr)) { | |
323 | clk_disable(obj->clk); | |
324 | return PTR_ERR(cr); | |
325 | } | |
326 | ||
327 | iotlb_load_cr(obj, cr); | |
328 | kfree(cr); | |
329 | ||
be6d8026 KH |
330 | if (e->prsvd) |
331 | l.base++; | |
a9dcad5e HD |
332 | /* increment victim for next tlb load */ |
333 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 334 | l.vict = l.base; |
a9dcad5e HD |
335 | iotlb_lock_set(obj, &l); |
336 | out: | |
337 | clk_disable(obj->clk); | |
338 | return err; | |
339 | } | |
a9dcad5e | 340 | |
5da14a47 OBC |
341 | #else /* !PREFETCH_IOTLB */ |
342 | ||
6c32df43 | 343 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
344 | { |
345 | return 0; | |
346 | } | |
347 | ||
348 | #endif /* !PREFETCH_IOTLB */ | |
349 | ||
6c32df43 | 350 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
351 | { |
352 | return load_iotlb_entry(obj, e); | |
353 | } | |
a9dcad5e HD |
354 | |
355 | /** | |
356 | * flush_iotlb_page - Clear an iommu tlb entry | |
357 | * @obj: target iommu | |
358 | * @da: iommu device virtual address | |
359 | * | |
360 | * Clear an iommu tlb entry which includes 'da' address. | |
361 | **/ | |
6c32df43 | 362 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 363 | { |
a9dcad5e | 364 | int i; |
37c2836c | 365 | struct cr_regs cr; |
a9dcad5e HD |
366 | |
367 | clk_enable(obj->clk); | |
368 | ||
37c2836c | 369 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
370 | u32 start; |
371 | size_t bytes; | |
372 | ||
a9dcad5e HD |
373 | if (!iotlb_cr_valid(&cr)) |
374 | continue; | |
375 | ||
376 | start = iotlb_cr_to_virt(&cr); | |
377 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
378 | ||
379 | if ((start <= da) && (da < start + bytes)) { | |
380 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
381 | __func__, start, da, bytes); | |
0fa035e5 | 382 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
383 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
384 | } | |
385 | } | |
386 | clk_disable(obj->clk); | |
387 | ||
388 | if (i == obj->nr_tlb_entries) | |
389 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
390 | } | |
a9dcad5e HD |
391 | |
392 | /** | |
393 | * flush_iotlb_all - Clear all iommu tlb entries | |
394 | * @obj: target iommu | |
395 | **/ | |
6c32df43 | 396 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
397 | { |
398 | struct iotlb_lock l; | |
399 | ||
400 | clk_enable(obj->clk); | |
401 | ||
402 | l.base = 0; | |
403 | l.vict = 0; | |
404 | iotlb_lock_set(obj, &l); | |
405 | ||
406 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
407 | ||
408 | clk_disable(obj->clk); | |
409 | } | |
ddfa975a | 410 | |
e4efd94b | 411 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 412 | |
6c32df43 | 413 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 414 | { |
a9dcad5e HD |
415 | if (!obj || !buf) |
416 | return -EINVAL; | |
417 | ||
418 | clk_enable(obj->clk); | |
419 | ||
14e0e679 | 420 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
421 | |
422 | clk_disable(obj->clk); | |
423 | ||
424 | return bytes; | |
425 | } | |
6c32df43 | 426 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 427 | |
6c32df43 OBC |
428 | static int |
429 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
430 | { |
431 | int i; | |
37c2836c HD |
432 | struct iotlb_lock saved; |
433 | struct cr_regs tmp; | |
a9dcad5e HD |
434 | struct cr_regs *p = crs; |
435 | ||
436 | clk_enable(obj->clk); | |
a9dcad5e | 437 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 438 | |
37c2836c | 439 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
440 | if (!iotlb_cr_valid(&tmp)) |
441 | continue; | |
a9dcad5e HD |
442 | *p++ = tmp; |
443 | } | |
37c2836c | 444 | |
a9dcad5e HD |
445 | iotlb_lock_set(obj, &saved); |
446 | clk_disable(obj->clk); | |
447 | ||
448 | return p - crs; | |
449 | } | |
450 | ||
451 | /** | |
6c32df43 | 452 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
453 | * @obj: target iommu |
454 | * @buf: output buffer | |
455 | **/ | |
6c32df43 | 456 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 457 | { |
14e0e679 | 458 | int i, num; |
a9dcad5e HD |
459 | struct cr_regs *cr; |
460 | char *p = buf; | |
461 | ||
14e0e679 HD |
462 | num = bytes / sizeof(*cr); |
463 | num = min(obj->nr_tlb_entries, num); | |
464 | ||
465 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
466 | if (!cr) |
467 | return 0; | |
468 | ||
14e0e679 HD |
469 | num = __dump_tlb_entries(obj, cr, num); |
470 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
471 | p += iotlb_dump_cr(obj, cr + i, p); |
472 | kfree(cr); | |
473 | ||
474 | return p - buf; | |
475 | } | |
6c32df43 | 476 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 477 | |
6c32df43 | 478 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
479 | { |
480 | return driver_for_each_device(&omap_iommu_driver.driver, | |
481 | NULL, data, fn); | |
482 | } | |
6c32df43 | 483 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
484 | |
485 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
486 | ||
487 | /* | |
488 | * H/W pagetable operations | |
489 | */ | |
490 | static void flush_iopgd_range(u32 *first, u32 *last) | |
491 | { | |
492 | /* FIXME: L2 cache should be taken care of if it exists */ | |
493 | do { | |
494 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
495 | : : "r" (first)); | |
496 | first += L1_CACHE_BYTES / sizeof(*first); | |
497 | } while (first <= last); | |
498 | } | |
499 | ||
500 | static void flush_iopte_range(u32 *first, u32 *last) | |
501 | { | |
502 | /* FIXME: L2 cache should be taken care of if it exists */ | |
503 | do { | |
504 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
505 | : : "r" (first)); | |
506 | first += L1_CACHE_BYTES / sizeof(*first); | |
507 | } while (first <= last); | |
508 | } | |
509 | ||
510 | static void iopte_free(u32 *iopte) | |
511 | { | |
512 | /* Note: freed iopte's must be clean ready for re-use */ | |
513 | kmem_cache_free(iopte_cachep, iopte); | |
514 | } | |
515 | ||
6c32df43 | 516 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
517 | { |
518 | u32 *iopte; | |
519 | ||
520 | /* a table has already existed */ | |
521 | if (*iopgd) | |
522 | goto pte_ready; | |
523 | ||
524 | /* | |
525 | * do the allocation outside the page table lock | |
526 | */ | |
527 | spin_unlock(&obj->page_table_lock); | |
528 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
529 | spin_lock(&obj->page_table_lock); | |
530 | ||
531 | if (!*iopgd) { | |
532 | if (!iopte) | |
533 | return ERR_PTR(-ENOMEM); | |
534 | ||
535 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
536 | flush_iopgd_range(iopgd, iopgd); | |
537 | ||
538 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
539 | } else { | |
540 | /* We raced, free the reduniovant table */ | |
541 | iopte_free(iopte); | |
542 | } | |
543 | ||
544 | pte_ready: | |
545 | iopte = iopte_offset(iopgd, da); | |
546 | ||
547 | dev_vdbg(obj->dev, | |
548 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
549 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
550 | ||
551 | return iopte; | |
552 | } | |
553 | ||
6c32df43 | 554 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
555 | { |
556 | u32 *iopgd = iopgd_offset(obj, da); | |
557 | ||
4abb7617 HD |
558 | if ((da | pa) & ~IOSECTION_MASK) { |
559 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
560 | __func__, da, pa, IOSECTION_SIZE); | |
561 | return -EINVAL; | |
562 | } | |
563 | ||
a9dcad5e HD |
564 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
565 | flush_iopgd_range(iopgd, iopgd); | |
566 | return 0; | |
567 | } | |
568 | ||
6c32df43 | 569 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
570 | { |
571 | u32 *iopgd = iopgd_offset(obj, da); | |
572 | int i; | |
573 | ||
4abb7617 HD |
574 | if ((da | pa) & ~IOSUPER_MASK) { |
575 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
576 | __func__, da, pa, IOSUPER_SIZE); | |
577 | return -EINVAL; | |
578 | } | |
579 | ||
a9dcad5e HD |
580 | for (i = 0; i < 16; i++) |
581 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
582 | flush_iopgd_range(iopgd, iopgd + 15); | |
583 | return 0; | |
584 | } | |
585 | ||
6c32df43 | 586 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
587 | { |
588 | u32 *iopgd = iopgd_offset(obj, da); | |
589 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
590 | ||
591 | if (IS_ERR(iopte)) | |
592 | return PTR_ERR(iopte); | |
593 | ||
594 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
595 | flush_iopte_range(iopte, iopte); | |
596 | ||
597 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
598 | __func__, da, pa, iopte, *iopte); | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
6c32df43 | 603 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
604 | { |
605 | u32 *iopgd = iopgd_offset(obj, da); | |
606 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
607 | int i; | |
608 | ||
4abb7617 HD |
609 | if ((da | pa) & ~IOLARGE_MASK) { |
610 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
611 | __func__, da, pa, IOLARGE_SIZE); | |
612 | return -EINVAL; | |
613 | } | |
614 | ||
a9dcad5e HD |
615 | if (IS_ERR(iopte)) |
616 | return PTR_ERR(iopte); | |
617 | ||
618 | for (i = 0; i < 16; i++) | |
619 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
620 | flush_iopte_range(iopte, iopte + 15); | |
621 | return 0; | |
622 | } | |
623 | ||
6c32df43 OBC |
624 | static int |
625 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 626 | { |
6c32df43 | 627 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
628 | u32 prot; |
629 | int err; | |
630 | ||
631 | if (!obj || !e) | |
632 | return -EINVAL; | |
633 | ||
634 | switch (e->pgsz) { | |
635 | case MMU_CAM_PGSZ_16M: | |
636 | fn = iopgd_alloc_super; | |
637 | break; | |
638 | case MMU_CAM_PGSZ_1M: | |
639 | fn = iopgd_alloc_section; | |
640 | break; | |
641 | case MMU_CAM_PGSZ_64K: | |
642 | fn = iopte_alloc_large; | |
643 | break; | |
644 | case MMU_CAM_PGSZ_4K: | |
645 | fn = iopte_alloc_page; | |
646 | break; | |
647 | default: | |
648 | fn = NULL; | |
649 | BUG(); | |
650 | break; | |
651 | } | |
652 | ||
653 | prot = get_iopte_attr(e); | |
654 | ||
655 | spin_lock(&obj->page_table_lock); | |
656 | err = fn(obj, e->da, e->pa, prot); | |
657 | spin_unlock(&obj->page_table_lock); | |
658 | ||
659 | return err; | |
660 | } | |
661 | ||
662 | /** | |
6c32df43 | 663 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
664 | * @obj: target iommu |
665 | * @e: an iommu tlb entry info | |
666 | **/ | |
6c32df43 | 667 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
668 | { |
669 | int err; | |
670 | ||
671 | flush_iotlb_page(obj, e->da); | |
672 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 673 | if (!err) |
5da14a47 | 674 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
675 | return err; |
676 | } | |
6c32df43 | 677 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
678 | |
679 | /** | |
680 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
681 | * @obj: target iommu | |
682 | * @da: iommu device virtual address | |
683 | * @ppgd: iommu pgd entry pointer to be returned | |
684 | * @ppte: iommu pte entry pointer to be returned | |
685 | **/ | |
e1f23813 OBC |
686 | static void |
687 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
688 | { |
689 | u32 *iopgd, *iopte = NULL; | |
690 | ||
691 | iopgd = iopgd_offset(obj, da); | |
692 | if (!*iopgd) | |
693 | goto out; | |
694 | ||
a1a54456 | 695 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
696 | iopte = iopte_offset(iopgd, da); |
697 | out: | |
698 | *ppgd = iopgd; | |
699 | *ppte = iopte; | |
700 | } | |
a9dcad5e | 701 | |
6c32df43 | 702 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
703 | { |
704 | size_t bytes; | |
705 | u32 *iopgd = iopgd_offset(obj, da); | |
706 | int nent = 1; | |
707 | ||
708 | if (!*iopgd) | |
709 | return 0; | |
710 | ||
a1a54456 | 711 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
712 | int i; |
713 | u32 *iopte = iopte_offset(iopgd, da); | |
714 | ||
715 | bytes = IOPTE_SIZE; | |
716 | if (*iopte & IOPTE_LARGE) { | |
717 | nent *= 16; | |
718 | /* rewind to the 1st entry */ | |
c127c7dc | 719 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
720 | } |
721 | bytes *= nent; | |
722 | memset(iopte, 0, nent * sizeof(*iopte)); | |
723 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
724 | ||
725 | /* | |
726 | * do table walk to check if this table is necessary or not | |
727 | */ | |
728 | iopte = iopte_offset(iopgd, 0); | |
729 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
730 | if (iopte[i]) | |
731 | goto out; | |
732 | ||
733 | iopte_free(iopte); | |
734 | nent = 1; /* for the next L1 entry */ | |
735 | } else { | |
736 | bytes = IOPGD_SIZE; | |
dcc730dc | 737 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
738 | nent *= 16; |
739 | /* rewind to the 1st entry */ | |
8d33ea58 | 740 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
741 | } |
742 | bytes *= nent; | |
743 | } | |
744 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
745 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
746 | out: | |
747 | return bytes; | |
748 | } | |
749 | ||
750 | /** | |
751 | * iopgtable_clear_entry - Remove an iommu pte entry | |
752 | * @obj: target iommu | |
753 | * @da: iommu device virtual address | |
754 | **/ | |
6c32df43 | 755 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
756 | { |
757 | size_t bytes; | |
758 | ||
759 | spin_lock(&obj->page_table_lock); | |
760 | ||
761 | bytes = iopgtable_clear_entry_core(obj, da); | |
762 | flush_iotlb_page(obj, da); | |
763 | ||
764 | spin_unlock(&obj->page_table_lock); | |
765 | ||
766 | return bytes; | |
767 | } | |
a9dcad5e | 768 | |
6c32df43 | 769 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
770 | { |
771 | int i; | |
772 | ||
773 | spin_lock(&obj->page_table_lock); | |
774 | ||
775 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
776 | u32 da; | |
777 | u32 *iopgd; | |
778 | ||
779 | da = i << IOPGD_SHIFT; | |
780 | iopgd = iopgd_offset(obj, da); | |
781 | ||
782 | if (!*iopgd) | |
783 | continue; | |
784 | ||
a1a54456 | 785 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
786 | iopte_free(iopte_offset(iopgd, 0)); |
787 | ||
788 | *iopgd = 0; | |
789 | flush_iopgd_range(iopgd, iopgd); | |
790 | } | |
791 | ||
792 | flush_iotlb_all(obj); | |
793 | ||
794 | spin_unlock(&obj->page_table_lock); | |
795 | } | |
796 | ||
797 | /* | |
798 | * Device IOMMU generic operations | |
799 | */ | |
800 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
801 | { | |
d594f1f3 | 802 | u32 da, errs; |
a9dcad5e | 803 | u32 *iopgd, *iopte; |
6c32df43 | 804 | struct omap_iommu *obj = data; |
e7f10f02 | 805 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
806 | |
807 | if (!obj->refcount) | |
808 | return IRQ_NONE; | |
809 | ||
a9dcad5e | 810 | clk_enable(obj->clk); |
d594f1f3 | 811 | errs = iommu_report_fault(obj, &da); |
a9dcad5e | 812 | clk_disable(obj->clk); |
c56b2ddd LP |
813 | if (errs == 0) |
814 | return IRQ_HANDLED; | |
d594f1f3 DC |
815 | |
816 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 817 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
818 | return IRQ_HANDLED; |
819 | ||
37b29810 HD |
820 | iommu_disable(obj); |
821 | ||
a9dcad5e HD |
822 | iopgd = iopgd_offset(obj, da); |
823 | ||
a1a54456 | 824 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
825 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
826 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
827 | return IRQ_NONE; |
828 | } | |
829 | ||
830 | iopte = iopte_offset(iopgd, da); | |
831 | ||
d594f1f3 DC |
832 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
833 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
834 | iopte, *iopte); | |
a9dcad5e HD |
835 | |
836 | return IRQ_NONE; | |
837 | } | |
838 | ||
839 | static int device_match_by_alias(struct device *dev, void *data) | |
840 | { | |
6c32df43 | 841 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
842 | const char *name = data; |
843 | ||
844 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
845 | ||
846 | return strcmp(obj->name, name) == 0; | |
847 | } | |
848 | ||
849 | /** | |
f626b52d | 850 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 851 | * @name: name of target omap iommu device |
f626b52d | 852 | * @iopgd: page table |
a9dcad5e | 853 | **/ |
fabdbca8 | 854 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e HD |
855 | { |
856 | int err = -ENOMEM; | |
fabdbca8 OBC |
857 | struct device *dev; |
858 | struct omap_iommu *obj; | |
859 | ||
860 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
861 | (void *)name, | |
862 | device_match_by_alias); | |
863 | if (!dev) | |
864 | return NULL; | |
865 | ||
866 | obj = to_iommu(dev); | |
a9dcad5e | 867 | |
f626b52d | 868 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 869 | |
f626b52d OBC |
870 | /* an iommu device can only be attached once */ |
871 | if (++obj->refcount > 1) { | |
872 | dev_err(dev, "%s: already attached!\n", obj->name); | |
873 | err = -EBUSY; | |
874 | goto err_enable; | |
a9dcad5e HD |
875 | } |
876 | ||
f626b52d OBC |
877 | obj->iopgd = iopgd; |
878 | err = iommu_enable(obj); | |
879 | if (err) | |
880 | goto err_enable; | |
881 | flush_iotlb_all(obj); | |
882 | ||
a9dcad5e HD |
883 | if (!try_module_get(obj->owner)) |
884 | goto err_module; | |
885 | ||
f626b52d | 886 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
887 | |
888 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
889 | return obj; | |
890 | ||
891 | err_module: | |
892 | if (obj->refcount == 1) | |
893 | iommu_disable(obj); | |
894 | err_enable: | |
895 | obj->refcount--; | |
f626b52d | 896 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
897 | return ERR_PTR(err); |
898 | } | |
a9dcad5e HD |
899 | |
900 | /** | |
f626b52d | 901 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
902 | * @obj: target iommu |
903 | **/ | |
6c32df43 | 904 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 905 | { |
acf9d467 | 906 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
907 | return; |
908 | ||
f626b52d | 909 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
910 | |
911 | if (--obj->refcount == 0) | |
912 | iommu_disable(obj); | |
913 | ||
914 | module_put(obj->owner); | |
915 | ||
f626b52d | 916 | obj->iopgd = NULL; |
d594f1f3 | 917 | |
f626b52d | 918 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 919 | |
a9dcad5e | 920 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 921 | } |
d594f1f3 | 922 | |
a9dcad5e HD |
923 | /* |
924 | * OMAP Device MMU(IOMMU) detection | |
925 | */ | |
926 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
927 | { | |
928 | int err = -ENODEV; | |
a9dcad5e | 929 | int irq; |
6c32df43 | 930 | struct omap_iommu *obj; |
a9dcad5e HD |
931 | struct resource *res; |
932 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
933 | ||
934 | if (pdev->num_resources != 2) | |
935 | return -EINVAL; | |
936 | ||
937 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
938 | if (!obj) | |
939 | return -ENOMEM; | |
940 | ||
941 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
942 | if (IS_ERR(obj->clk)) | |
943 | goto err_clk; | |
944 | ||
945 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
946 | obj->name = pdata->name; | |
947 | obj->dev = &pdev->dev; | |
948 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
949 | obj->da_start = pdata->da_start; |
950 | obj->da_end = pdata->da_end; | |
a9dcad5e | 951 | |
f626b52d | 952 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
953 | mutex_init(&obj->mmap_lock); |
954 | spin_lock_init(&obj->page_table_lock); | |
955 | INIT_LIST_HEAD(&obj->mmap); | |
956 | ||
957 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
958 | if (!res) { | |
959 | err = -ENODEV; | |
960 | goto err_mem; | |
961 | } | |
a9dcad5e HD |
962 | |
963 | res = request_mem_region(res->start, resource_size(res), | |
964 | dev_name(&pdev->dev)); | |
965 | if (!res) { | |
966 | err = -EIO; | |
967 | goto err_mem; | |
968 | } | |
969 | ||
da4a0f76 AK |
970 | obj->regbase = ioremap(res->start, resource_size(res)); |
971 | if (!obj->regbase) { | |
972 | err = -ENOMEM; | |
973 | goto err_ioremap; | |
974 | } | |
975 | ||
a9dcad5e HD |
976 | irq = platform_get_irq(pdev, 0); |
977 | if (irq < 0) { | |
978 | err = -ENODEV; | |
979 | goto err_irq; | |
980 | } | |
981 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
982 | dev_name(&pdev->dev), obj); | |
983 | if (err < 0) | |
984 | goto err_irq; | |
985 | platform_set_drvdata(pdev, obj); | |
986 | ||
a9dcad5e HD |
987 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
988 | return 0; | |
989 | ||
a9dcad5e | 990 | err_irq: |
a9dcad5e | 991 | iounmap(obj->regbase); |
da4a0f76 AK |
992 | err_ioremap: |
993 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e HD |
994 | err_mem: |
995 | clk_put(obj->clk); | |
996 | err_clk: | |
997 | kfree(obj); | |
998 | return err; | |
999 | } | |
1000 | ||
1001 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
1002 | { | |
1003 | int irq; | |
1004 | struct resource *res; | |
6c32df43 | 1005 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
1006 | |
1007 | platform_set_drvdata(pdev, NULL); | |
1008 | ||
1009 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
1010 | |
1011 | irq = platform_get_irq(pdev, 0); | |
1012 | free_irq(irq, obj); | |
1013 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1014 | release_mem_region(res->start, resource_size(res)); | |
1015 | iounmap(obj->regbase); | |
1016 | ||
1017 | clk_put(obj->clk); | |
1018 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1019 | kfree(obj); | |
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static struct platform_driver omap_iommu_driver = { | |
1024 | .probe = omap_iommu_probe, | |
1025 | .remove = __devexit_p(omap_iommu_remove), | |
1026 | .driver = { | |
1027 | .name = "omap-iommu", | |
1028 | }, | |
1029 | }; | |
1030 | ||
1031 | static void iopte_cachep_ctor(void *iopte) | |
1032 | { | |
1033 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1034 | } | |
1035 | ||
ed1c7de2 TL |
1036 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
1037 | u32 flags) | |
1038 | { | |
1039 | memset(e, 0, sizeof(*e)); | |
1040 | ||
1041 | e->da = da; | |
1042 | e->pa = pa; | |
1043 | e->valid = 1; | |
1044 | /* FIXME: add OMAP1 support */ | |
1045 | e->pgsz = flags & MMU_CAM_PGSZ_MASK; | |
1046 | e->endian = flags & MMU_RAM_ENDIAN_MASK; | |
1047 | e->elsz = flags & MMU_RAM_ELSZ_MASK; | |
1048 | e->mixed = flags & MMU_RAM_MIXED_MASK; | |
1049 | ||
1050 | return iopgsz_to_bytes(e->pgsz); | |
1051 | } | |
1052 | ||
f626b52d | 1053 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1054 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1055 | { |
1056 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1057 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1058 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1059 | struct iotlb_entry e; |
1060 | int omap_pgsz; | |
1061 | u32 ret, flags; | |
1062 | ||
1063 | /* we only support mapping a single iommu page for now */ | |
1064 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1065 | if (omap_pgsz < 0) { | |
1066 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | ||
1070 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1071 | ||
1072 | flags = omap_pgsz | prot; | |
1073 | ||
1074 | iotlb_init_entry(&e, da, pa, flags); | |
1075 | ||
6c32df43 | 1076 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1077 | if (ret) |
6c32df43 | 1078 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1079 | |
b4550d41 | 1080 | return ret; |
f626b52d OBC |
1081 | } |
1082 | ||
5009065d OBC |
1083 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1084 | size_t size) | |
f626b52d OBC |
1085 | { |
1086 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1087 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1088 | struct device *dev = oiommu->dev; |
f626b52d | 1089 | |
5009065d | 1090 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1091 | |
5009065d | 1092 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1093 | } |
1094 | ||
1095 | static int | |
1096 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1097 | { | |
1098 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1099 | struct omap_iommu *oiommu; |
fabdbca8 | 1100 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1101 | int ret = 0; |
1102 | ||
1103 | spin_lock(&omap_domain->lock); | |
1104 | ||
1105 | /* only a single device is supported per domain for now */ | |
1106 | if (omap_domain->iommu_dev) { | |
1107 | dev_err(dev, "iommu domain is already attached\n"); | |
1108 | ret = -EBUSY; | |
1109 | goto out; | |
1110 | } | |
1111 | ||
1112 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1113 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1114 | if (IS_ERR(oiommu)) { |
1115 | ret = PTR_ERR(oiommu); | |
1116 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1117 | goto out; | |
1118 | } | |
1119 | ||
fabdbca8 | 1120 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1121 | omap_domain->dev = dev; |
e7f10f02 | 1122 | oiommu->domain = domain; |
f626b52d OBC |
1123 | |
1124 | out: | |
1125 | spin_unlock(&omap_domain->lock); | |
1126 | return ret; | |
1127 | } | |
1128 | ||
803b5277 ORL |
1129 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1130 | struct device *dev) | |
f626b52d | 1131 | { |
fabdbca8 | 1132 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1133 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1134 | |
1135 | /* only a single device is supported per domain for now */ | |
1136 | if (omap_domain->iommu_dev != oiommu) { | |
1137 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1138 | return; |
f626b52d OBC |
1139 | } |
1140 | ||
1141 | iopgtable_clear_entry_all(oiommu); | |
1142 | ||
1143 | omap_iommu_detach(oiommu); | |
1144 | ||
fabdbca8 | 1145 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1146 | omap_domain->dev = NULL; |
1147 | } | |
f626b52d | 1148 | |
803b5277 ORL |
1149 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1150 | struct device *dev) | |
1151 | { | |
1152 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1153 | ||
1154 | spin_lock(&omap_domain->lock); | |
1155 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1156 | spin_unlock(&omap_domain->lock); |
1157 | } | |
1158 | ||
1159 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1160 | { | |
1161 | struct omap_iommu_domain *omap_domain; | |
1162 | ||
1163 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1164 | if (!omap_domain) { | |
1165 | pr_err("kzalloc failed\n"); | |
1166 | goto out; | |
1167 | } | |
1168 | ||
1169 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1170 | if (!omap_domain->pgtable) { | |
1171 | pr_err("kzalloc failed\n"); | |
1172 | goto fail_nomem; | |
1173 | } | |
1174 | ||
1175 | /* | |
1176 | * should never fail, but please keep this around to ensure | |
1177 | * we keep the hardware happy | |
1178 | */ | |
1179 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1180 | ||
1181 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1182 | spin_lock_init(&omap_domain->lock); | |
1183 | ||
1184 | domain->priv = omap_domain; | |
1185 | ||
2c6edb0c JR |
1186 | domain->geometry.aperture_start = 0; |
1187 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1188 | domain->geometry.force_aperture = true; | |
1189 | ||
f626b52d OBC |
1190 | return 0; |
1191 | ||
1192 | fail_nomem: | |
1193 | kfree(omap_domain); | |
1194 | out: | |
1195 | return -ENOMEM; | |
1196 | } | |
1197 | ||
f626b52d OBC |
1198 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1199 | { | |
1200 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1201 | ||
1202 | domain->priv = NULL; | |
1203 | ||
803b5277 ORL |
1204 | /* |
1205 | * An iommu device is still attached | |
1206 | * (currently, only one device can be attached) ? | |
1207 | */ | |
1208 | if (omap_domain->iommu_dev) | |
1209 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1210 | ||
f626b52d OBC |
1211 | kfree(omap_domain->pgtable); |
1212 | kfree(omap_domain); | |
1213 | } | |
1214 | ||
1215 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
1216 | unsigned long da) | |
1217 | { | |
1218 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1219 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1220 | struct device *dev = oiommu->dev; |
1221 | u32 *pgd, *pte; | |
1222 | phys_addr_t ret = 0; | |
1223 | ||
1224 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1225 | ||
1226 | if (pte) { | |
1227 | if (iopte_is_small(*pte)) | |
1228 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1229 | else if (iopte_is_large(*pte)) | |
1230 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1231 | else | |
1a36ea81 | 1232 | dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da); |
f626b52d OBC |
1233 | } else { |
1234 | if (iopgd_is_section(*pgd)) | |
1235 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1236 | else if (iopgd_is_super(*pgd)) | |
1237 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1238 | else | |
1a36ea81 | 1239 | dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da); |
f626b52d OBC |
1240 | } |
1241 | ||
1242 | return ret; | |
1243 | } | |
1244 | ||
1245 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1246 | unsigned long cap) | |
1247 | { | |
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | static struct iommu_ops omap_iommu_ops = { | |
1252 | .domain_init = omap_iommu_domain_init, | |
1253 | .domain_destroy = omap_iommu_domain_destroy, | |
1254 | .attach_dev = omap_iommu_attach_dev, | |
1255 | .detach_dev = omap_iommu_detach_dev, | |
1256 | .map = omap_iommu_map, | |
1257 | .unmap = omap_iommu_unmap, | |
1258 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1259 | .domain_has_cap = omap_iommu_domain_has_cap, | |
66bc8cf3 | 1260 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1261 | }; |
1262 | ||
a9dcad5e HD |
1263 | static int __init omap_iommu_init(void) |
1264 | { | |
1265 | struct kmem_cache *p; | |
1266 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1267 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1268 | ||
1269 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1270 | iopte_cachep_ctor); | |
1271 | if (!p) | |
1272 | return -ENOMEM; | |
1273 | iopte_cachep = p; | |
1274 | ||
a65bc64f | 1275 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1276 | |
a9dcad5e HD |
1277 | return platform_driver_register(&omap_iommu_driver); |
1278 | } | |
435792d9 OBC |
1279 | /* must be ready before omap3isp is probed */ |
1280 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1281 | |
1282 | static void __exit omap_iommu_exit(void) | |
1283 | { | |
1284 | kmem_cache_destroy(iopte_cachep); | |
1285 | ||
1286 | platform_driver_unregister(&omap_iommu_driver); | |
1287 | } | |
1288 | module_exit(omap_iommu_exit); | |
1289 | ||
1290 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1291 | MODULE_ALIAS("platform:omap-iommu"); | |
1292 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1293 | MODULE_LICENSE("GPL v2"); |