Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a9dcad5e HD |
2 | /* |
3 | * omap iommu: tlb and pagetable primitives | |
4 | * | |
c127c7dc | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
9d5018de | 6 | * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ |
a9dcad5e HD |
7 | * |
8 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
9 | * Paul Mundt and Toshihiro Kobayashi | |
a9dcad5e HD |
10 | */ |
11 | ||
bfee0cf0 | 12 | #include <linux/dma-mapping.h> |
a9dcad5e | 13 | #include <linux/err.h> |
5a0e3ad6 | 14 | #include <linux/slab.h> |
a9dcad5e HD |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioport.h> | |
a9dcad5e | 17 | #include <linux/platform_device.h> |
f626b52d | 18 | #include <linux/iommu.h> |
c8d35c84 | 19 | #include <linux/omap-iommu.h> |
f626b52d OBC |
20 | #include <linux/mutex.h> |
21 | #include <linux/spinlock.h> | |
ed1c7de2 | 22 | #include <linux/io.h> |
ebf7cda0 | 23 | #include <linux/pm_runtime.h> |
3c92748d FV |
24 | #include <linux/of.h> |
25 | #include <linux/of_iommu.h> | |
26 | #include <linux/of_irq.h> | |
7d682774 | 27 | #include <linux/of_platform.h> |
3ca9299e SA |
28 | #include <linux/regmap.h> |
29 | #include <linux/mfd/syscon.h> | |
a9dcad5e | 30 | |
2ab7c848 | 31 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 32 | |
2f7702af | 33 | #include "omap-iopgtable.h" |
ed1c7de2 | 34 | #include "omap-iommu.h" |
a9dcad5e | 35 | |
01611fe8 JR |
36 | static const struct iommu_ops omap_iommu_ops; |
37 | ||
604629bc TK |
38 | struct orphan_dev { |
39 | struct device *dev; | |
40 | struct list_head node; | |
41 | }; | |
42 | ||
43 | static LIST_HEAD(orphan_dev_list); | |
44 | ||
45 | static DEFINE_SPINLOCK(orphan_lock); | |
46 | ||
6e8b5668 | 47 | #define to_iommu(dev) ((struct omap_iommu *)dev_get_drvdata(dev)) |
5acc97db | 48 | |
66bc8cf3 OBC |
49 | /* bitmap of the page sizes currently supported */ |
50 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
51 | ||
7bd9e25f IY |
52 | #define MMU_LOCK_BASE_SHIFT 10 |
53 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
54 | #define MMU_LOCK_BASE(x) \ | |
55 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
56 | ||
57 | #define MMU_LOCK_VICT_SHIFT 4 | |
58 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
59 | #define MMU_LOCK_VICT(x) \ | |
60 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
61 | ||
a9dcad5e HD |
62 | static struct platform_driver omap_iommu_driver; |
63 | static struct kmem_cache *iopte_cachep; | |
64 | ||
604629bc TK |
65 | static int _omap_iommu_add_device(struct device *dev); |
66 | ||
8cf851e0 JR |
67 | /** |
68 | * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain | |
69 | * @dom: generic iommu domain handle | |
70 | **/ | |
71 | static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) | |
72 | { | |
73 | return container_of(dom, struct omap_iommu_domain, domain); | |
74 | } | |
75 | ||
a9dcad5e | 76 | /** |
6c32df43 | 77 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 78 | * @dev: client device |
c4206c4e SA |
79 | * |
80 | * This should be treated as an deprecated API. It is preserved only | |
81 | * to maintain existing functionality for OMAP3 ISP driver. | |
a9dcad5e | 82 | **/ |
fabdbca8 | 83 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 84 | { |
9d5018de SA |
85 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
86 | struct omap_iommu *obj; | |
87 | u32 *p; | |
bd4396f0 | 88 | int i; |
fabdbca8 | 89 | |
9d5018de SA |
90 | if (!arch_data) |
91 | return; | |
92 | ||
93 | while (arch_data->iommu_dev) { | |
94 | obj = arch_data->iommu_dev; | |
95 | p = obj->ctx; | |
96 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
97 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
98 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
99 | p[i]); | |
100 | } | |
101 | arch_data++; | |
bd4396f0 | 102 | } |
a9dcad5e | 103 | } |
6c32df43 | 104 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
105 | |
106 | /** | |
6c32df43 | 107 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 108 | * @dev: client device |
c4206c4e SA |
109 | * |
110 | * This should be treated as an deprecated API. It is preserved only | |
111 | * to maintain existing functionality for OMAP3 ISP driver. | |
a9dcad5e | 112 | **/ |
fabdbca8 | 113 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 114 | { |
9d5018de SA |
115 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
116 | struct omap_iommu *obj; | |
117 | u32 *p; | |
bd4396f0 | 118 | int i; |
fabdbca8 | 119 | |
9d5018de SA |
120 | if (!arch_data) |
121 | return; | |
122 | ||
123 | while (arch_data->iommu_dev) { | |
124 | obj = arch_data->iommu_dev; | |
125 | p = obj->ctx; | |
126 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
127 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
128 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
129 | p[i]); | |
130 | } | |
131 | arch_data++; | |
bd4396f0 | 132 | } |
a9dcad5e | 133 | } |
6c32df43 | 134 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e | 135 | |
3ca9299e SA |
136 | static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable) |
137 | { | |
138 | u32 val, mask; | |
139 | ||
140 | if (!obj->syscfg) | |
141 | return; | |
142 | ||
143 | mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT)); | |
144 | val = enable ? mask : 0; | |
145 | regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); | |
146 | } | |
147 | ||
bd4396f0 SA |
148 | static void __iommu_set_twl(struct omap_iommu *obj, bool on) |
149 | { | |
150 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
151 | ||
152 | if (on) | |
153 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | |
154 | else | |
155 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | |
156 | ||
157 | l &= ~MMU_CNTL_MASK; | |
158 | if (on) | |
159 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
160 | else | |
161 | l |= (MMU_CNTL_MMU_EN); | |
162 | ||
163 | iommu_write_reg(obj, l, MMU_CNTL); | |
164 | } | |
165 | ||
166 | static int omap2_iommu_enable(struct omap_iommu *obj) | |
167 | { | |
168 | u32 l, pa; | |
169 | ||
170 | if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | |
171 | return -EINVAL; | |
172 | ||
173 | pa = virt_to_phys(obj->iopgd); | |
174 | if (!IS_ALIGNED(pa, SZ_16K)) | |
175 | return -EINVAL; | |
176 | ||
177 | l = iommu_read_reg(obj, MMU_REVISION); | |
178 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
179 | (l >> 4) & 0xf, l & 0xf); | |
180 | ||
181 | iommu_write_reg(obj, pa, MMU_TTB); | |
182 | ||
3ca9299e SA |
183 | dra7_cfg_dspsys_mmu(obj, true); |
184 | ||
bd4396f0 SA |
185 | if (obj->has_bus_err_back) |
186 | iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); | |
187 | ||
188 | __iommu_set_twl(obj, true); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | static void omap2_iommu_disable(struct omap_iommu *obj) | |
194 | { | |
195 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
196 | ||
197 | l &= ~MMU_CNTL_MASK; | |
198 | iommu_write_reg(obj, l, MMU_CNTL); | |
3ca9299e | 199 | dra7_cfg_dspsys_mmu(obj, false); |
bd4396f0 SA |
200 | |
201 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
202 | } | |
203 | ||
6c32df43 | 204 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e | 205 | { |
db8918f6 | 206 | int ret; |
a9dcad5e | 207 | |
db8918f6 SA |
208 | ret = pm_runtime_get_sync(obj->dev); |
209 | if (ret < 0) | |
210 | pm_runtime_put_noidle(obj->dev); | |
a9dcad5e | 211 | |
db8918f6 | 212 | return ret < 0 ? ret : 0; |
a9dcad5e HD |
213 | } |
214 | ||
6c32df43 | 215 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 216 | { |
ebf7cda0 | 217 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
218 | } |
219 | ||
220 | /* | |
221 | * TLB operations | |
222 | */ | |
e1f23813 | 223 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e | 224 | { |
bd4396f0 SA |
225 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; |
226 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
227 | ||
228 | return cr->cam & mask; | |
a9dcad5e | 229 | } |
a9dcad5e HD |
230 | |
231 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
232 | { | |
bd4396f0 SA |
233 | u32 attr; |
234 | ||
235 | attr = e->mixed << 5; | |
236 | attr |= e->endian; | |
237 | attr |= e->elsz >> 3; | |
238 | attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || | |
239 | (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); | |
240 | return attr; | |
a9dcad5e HD |
241 | } |
242 | ||
6c32df43 | 243 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e | 244 | { |
bd4396f0 SA |
245 | u32 status, fault_addr; |
246 | ||
247 | status = iommu_read_reg(obj, MMU_IRQSTATUS); | |
248 | status &= MMU_IRQ_MASK; | |
249 | if (!status) { | |
250 | *da = 0; | |
251 | return 0; | |
252 | } | |
253 | ||
254 | fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); | |
255 | *da = fault_addr; | |
256 | ||
257 | iommu_write_reg(obj, status, MMU_IRQSTATUS); | |
258 | ||
259 | return status; | |
a9dcad5e HD |
260 | } |
261 | ||
69c2c196 | 262 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
263 | { |
264 | u32 val; | |
265 | ||
266 | val = iommu_read_reg(obj, MMU_LOCK); | |
267 | ||
268 | l->base = MMU_LOCK_BASE(val); | |
269 | l->vict = MMU_LOCK_VICT(val); | |
a9dcad5e HD |
270 | } |
271 | ||
69c2c196 | 272 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
273 | { |
274 | u32 val; | |
275 | ||
a9dcad5e HD |
276 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
277 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
278 | ||
279 | iommu_write_reg(obj, val, MMU_LOCK); | |
280 | } | |
281 | ||
6c32df43 | 282 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 283 | { |
bd4396f0 SA |
284 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); |
285 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
a9dcad5e HD |
286 | } |
287 | ||
6c32df43 | 288 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 289 | { |
bd4396f0 SA |
290 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); |
291 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
a9dcad5e HD |
292 | |
293 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
294 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
295 | } | |
296 | ||
37c2836c | 297 | /* only used in iotlb iteration for-loop */ |
69c2c196 | 298 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
299 | { |
300 | struct cr_regs cr; | |
301 | struct iotlb_lock l; | |
302 | ||
303 | iotlb_lock_get(obj, &l); | |
304 | l.vict = n; | |
305 | iotlb_lock_set(obj, &l); | |
306 | iotlb_read_cr(obj, &cr); | |
307 | ||
308 | return cr; | |
309 | } | |
310 | ||
bd4396f0 SA |
311 | #ifdef PREFETCH_IOTLB |
312 | static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, | |
313 | struct iotlb_entry *e) | |
314 | { | |
315 | struct cr_regs *cr; | |
316 | ||
317 | if (!e) | |
318 | return NULL; | |
319 | ||
320 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
321 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
322 | e->da); | |
323 | return ERR_PTR(-EINVAL); | |
324 | } | |
325 | ||
326 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
327 | if (!cr) | |
328 | return ERR_PTR(-ENOMEM); | |
329 | ||
330 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; | |
331 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; | |
332 | ||
333 | return cr; | |
334 | } | |
335 | ||
a9dcad5e HD |
336 | /** |
337 | * load_iotlb_entry - Set an iommu tlb entry | |
338 | * @obj: target iommu | |
339 | * @e: an iommu tlb entry info | |
340 | **/ | |
6c32df43 | 341 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 342 | { |
a9dcad5e HD |
343 | int err = 0; |
344 | struct iotlb_lock l; | |
345 | struct cr_regs *cr; | |
346 | ||
347 | if (!obj || !obj->nr_tlb_entries || !e) | |
348 | return -EINVAL; | |
349 | ||
ebf7cda0 | 350 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 351 | |
be6d8026 KH |
352 | iotlb_lock_get(obj, &l); |
353 | if (l.base == obj->nr_tlb_entries) { | |
354 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
355 | err = -EBUSY; |
356 | goto out; | |
357 | } | |
be6d8026 | 358 | if (!e->prsvd) { |
37c2836c HD |
359 | int i; |
360 | struct cr_regs tmp; | |
be6d8026 | 361 | |
37c2836c | 362 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
363 | if (!iotlb_cr_valid(&tmp)) |
364 | break; | |
37c2836c | 365 | |
be6d8026 KH |
366 | if (i == obj->nr_tlb_entries) { |
367 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
368 | err = -EBUSY; | |
369 | goto out; | |
370 | } | |
37c2836c HD |
371 | |
372 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
373 | } else { |
374 | l.vict = l.base; | |
375 | iotlb_lock_set(obj, &l); | |
376 | } | |
a9dcad5e HD |
377 | |
378 | cr = iotlb_alloc_cr(obj, e); | |
379 | if (IS_ERR(cr)) { | |
ebf7cda0 | 380 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
381 | return PTR_ERR(cr); |
382 | } | |
383 | ||
384 | iotlb_load_cr(obj, cr); | |
385 | kfree(cr); | |
386 | ||
be6d8026 KH |
387 | if (e->prsvd) |
388 | l.base++; | |
a9dcad5e HD |
389 | /* increment victim for next tlb load */ |
390 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 391 | l.vict = l.base; |
a9dcad5e HD |
392 | iotlb_lock_set(obj, &l); |
393 | out: | |
ebf7cda0 | 394 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
395 | return err; |
396 | } | |
a9dcad5e | 397 | |
5da14a47 OBC |
398 | #else /* !PREFETCH_IOTLB */ |
399 | ||
6c32df43 | 400 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
401 | { |
402 | return 0; | |
403 | } | |
404 | ||
405 | #endif /* !PREFETCH_IOTLB */ | |
406 | ||
6c32df43 | 407 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
408 | { |
409 | return load_iotlb_entry(obj, e); | |
410 | } | |
a9dcad5e HD |
411 | |
412 | /** | |
413 | * flush_iotlb_page - Clear an iommu tlb entry | |
414 | * @obj: target iommu | |
415 | * @da: iommu device virtual address | |
416 | * | |
417 | * Clear an iommu tlb entry which includes 'da' address. | |
418 | **/ | |
6c32df43 | 419 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 420 | { |
a9dcad5e | 421 | int i; |
37c2836c | 422 | struct cr_regs cr; |
a9dcad5e | 423 | |
ebf7cda0 | 424 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 425 | |
37c2836c | 426 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
427 | u32 start; |
428 | size_t bytes; | |
429 | ||
a9dcad5e HD |
430 | if (!iotlb_cr_valid(&cr)) |
431 | continue; | |
432 | ||
433 | start = iotlb_cr_to_virt(&cr); | |
434 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
435 | ||
436 | if ((start <= da) && (da < start + bytes)) { | |
437 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
438 | __func__, start, da, bytes); | |
0fa035e5 | 439 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 440 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 441 | break; |
a9dcad5e HD |
442 | } |
443 | } | |
ebf7cda0 | 444 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
445 | |
446 | if (i == obj->nr_tlb_entries) | |
447 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
448 | } | |
a9dcad5e HD |
449 | |
450 | /** | |
451 | * flush_iotlb_all - Clear all iommu tlb entries | |
452 | * @obj: target iommu | |
453 | **/ | |
6c32df43 | 454 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
455 | { |
456 | struct iotlb_lock l; | |
457 | ||
ebf7cda0 | 458 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
459 | |
460 | l.base = 0; | |
461 | l.vict = 0; | |
462 | iotlb_lock_set(obj, &l); | |
463 | ||
464 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
465 | ||
ebf7cda0 | 466 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 467 | } |
ddfa975a | 468 | |
a9dcad5e HD |
469 | /* |
470 | * H/W pagetable operations | |
471 | */ | |
bfee0cf0 JA |
472 | static void flush_iopte_range(struct device *dev, dma_addr_t dma, |
473 | unsigned long offset, int num_entries) | |
a9dcad5e | 474 | { |
bfee0cf0 | 475 | size_t size = num_entries * sizeof(u32); |
a9dcad5e | 476 | |
bfee0cf0 | 477 | dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE); |
a9dcad5e HD |
478 | } |
479 | ||
bfee0cf0 | 480 | static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid) |
a9dcad5e | 481 | { |
bfee0cf0 JA |
482 | dma_addr_t pt_dma; |
483 | ||
a9dcad5e | 484 | /* Note: freed iopte's must be clean ready for re-use */ |
bfee0cf0 JA |
485 | if (iopte) { |
486 | if (dma_valid) { | |
487 | pt_dma = virt_to_phys(iopte); | |
488 | dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE, | |
489 | DMA_TO_DEVICE); | |
490 | } | |
491 | ||
e28045ab | 492 | kmem_cache_free(iopte_cachep, iopte); |
bfee0cf0 | 493 | } |
a9dcad5e HD |
494 | } |
495 | ||
bfee0cf0 JA |
496 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, |
497 | dma_addr_t *pt_dma, u32 da) | |
a9dcad5e HD |
498 | { |
499 | u32 *iopte; | |
bfee0cf0 | 500 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
501 | |
502 | /* a table has already existed */ | |
503 | if (*iopgd) | |
504 | goto pte_ready; | |
505 | ||
506 | /* | |
507 | * do the allocation outside the page table lock | |
508 | */ | |
509 | spin_unlock(&obj->page_table_lock); | |
510 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
511 | spin_lock(&obj->page_table_lock); | |
512 | ||
513 | if (!*iopgd) { | |
514 | if (!iopte) | |
515 | return ERR_PTR(-ENOMEM); | |
516 | ||
bfee0cf0 JA |
517 | *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE, |
518 | DMA_TO_DEVICE); | |
519 | if (dma_mapping_error(obj->dev, *pt_dma)) { | |
520 | dev_err(obj->dev, "DMA map error for L2 table\n"); | |
521 | iopte_free(obj, iopte, false); | |
522 | return ERR_PTR(-ENOMEM); | |
523 | } | |
524 | ||
525 | /* | |
526 | * we rely on dma address and the physical address to be | |
527 | * the same for mapping the L2 table | |
528 | */ | |
529 | if (WARN_ON(*pt_dma != virt_to_phys(iopte))) { | |
530 | dev_err(obj->dev, "DMA translation error for L2 table\n"); | |
531 | dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE, | |
532 | DMA_TO_DEVICE); | |
533 | iopte_free(obj, iopte, false); | |
534 | return ERR_PTR(-ENOMEM); | |
535 | } | |
536 | ||
a9dcad5e | 537 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; |
a9dcad5e | 538 | |
bfee0cf0 | 539 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
540 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); |
541 | } else { | |
542 | /* We raced, free the reduniovant table */ | |
bfee0cf0 | 543 | iopte_free(obj, iopte, false); |
a9dcad5e HD |
544 | } |
545 | ||
546 | pte_ready: | |
547 | iopte = iopte_offset(iopgd, da); | |
04c532a1 | 548 | *pt_dma = iopgd_page_paddr(iopgd); |
a9dcad5e HD |
549 | dev_vdbg(obj->dev, |
550 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
551 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
552 | ||
553 | return iopte; | |
554 | } | |
555 | ||
6c32df43 | 556 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
557 | { |
558 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 559 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e | 560 | |
4abb7617 HD |
561 | if ((da | pa) & ~IOSECTION_MASK) { |
562 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
563 | __func__, da, pa, IOSECTION_SIZE); | |
564 | return -EINVAL; | |
565 | } | |
566 | ||
a9dcad5e | 567 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
bfee0cf0 | 568 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
569 | return 0; |
570 | } | |
571 | ||
6c32df43 | 572 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
573 | { |
574 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 575 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
576 | int i; |
577 | ||
4abb7617 HD |
578 | if ((da | pa) & ~IOSUPER_MASK) { |
579 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
580 | __func__, da, pa, IOSUPER_SIZE); | |
581 | return -EINVAL; | |
582 | } | |
583 | ||
a9dcad5e HD |
584 | for (i = 0; i < 16; i++) |
585 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
bfee0cf0 | 586 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 16); |
a9dcad5e HD |
587 | return 0; |
588 | } | |
589 | ||
6c32df43 | 590 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
591 | { |
592 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
593 | dma_addr_t pt_dma; |
594 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
595 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
596 | |
597 | if (IS_ERR(iopte)) | |
598 | return PTR_ERR(iopte); | |
599 | ||
600 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
bfee0cf0 | 601 | flush_iopte_range(obj->dev, pt_dma, offset, 1); |
a9dcad5e HD |
602 | |
603 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
604 | __func__, da, pa, iopte, *iopte); | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
6c32df43 | 609 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
610 | { |
611 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
612 | dma_addr_t pt_dma; |
613 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
614 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
615 | int i; |
616 | ||
4abb7617 HD |
617 | if ((da | pa) & ~IOLARGE_MASK) { |
618 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
619 | __func__, da, pa, IOLARGE_SIZE); | |
620 | return -EINVAL; | |
621 | } | |
622 | ||
a9dcad5e HD |
623 | if (IS_ERR(iopte)) |
624 | return PTR_ERR(iopte); | |
625 | ||
626 | for (i = 0; i < 16; i++) | |
627 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
bfee0cf0 | 628 | flush_iopte_range(obj->dev, pt_dma, offset, 16); |
a9dcad5e HD |
629 | return 0; |
630 | } | |
631 | ||
6c32df43 OBC |
632 | static int |
633 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 634 | { |
6c32df43 | 635 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
636 | u32 prot; |
637 | int err; | |
638 | ||
639 | if (!obj || !e) | |
640 | return -EINVAL; | |
641 | ||
642 | switch (e->pgsz) { | |
643 | case MMU_CAM_PGSZ_16M: | |
644 | fn = iopgd_alloc_super; | |
645 | break; | |
646 | case MMU_CAM_PGSZ_1M: | |
647 | fn = iopgd_alloc_section; | |
648 | break; | |
649 | case MMU_CAM_PGSZ_64K: | |
650 | fn = iopte_alloc_large; | |
651 | break; | |
652 | case MMU_CAM_PGSZ_4K: | |
653 | fn = iopte_alloc_page; | |
654 | break; | |
655 | default: | |
656 | fn = NULL; | |
a9dcad5e HD |
657 | break; |
658 | } | |
659 | ||
7c1ab600 SA |
660 | if (WARN_ON(!fn)) |
661 | return -EINVAL; | |
662 | ||
a9dcad5e HD |
663 | prot = get_iopte_attr(e); |
664 | ||
665 | spin_lock(&obj->page_table_lock); | |
666 | err = fn(obj, e->da, e->pa, prot); | |
667 | spin_unlock(&obj->page_table_lock); | |
668 | ||
669 | return err; | |
670 | } | |
671 | ||
672 | /** | |
6c32df43 | 673 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
674 | * @obj: target iommu |
675 | * @e: an iommu tlb entry info | |
676 | **/ | |
4899a563 SA |
677 | static int |
678 | omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e HD |
679 | { |
680 | int err; | |
681 | ||
682 | flush_iotlb_page(obj, e->da); | |
683 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 684 | if (!err) |
5da14a47 | 685 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
686 | return err; |
687 | } | |
a9dcad5e HD |
688 | |
689 | /** | |
690 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
691 | * @obj: target iommu | |
692 | * @da: iommu device virtual address | |
693 | * @ppgd: iommu pgd entry pointer to be returned | |
694 | * @ppte: iommu pte entry pointer to be returned | |
695 | **/ | |
e1f23813 OBC |
696 | static void |
697 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
698 | { |
699 | u32 *iopgd, *iopte = NULL; | |
700 | ||
701 | iopgd = iopgd_offset(obj, da); | |
702 | if (!*iopgd) | |
703 | goto out; | |
704 | ||
a1a54456 | 705 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
706 | iopte = iopte_offset(iopgd, da); |
707 | out: | |
708 | *ppgd = iopgd; | |
709 | *ppte = iopte; | |
710 | } | |
a9dcad5e | 711 | |
6c32df43 | 712 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
713 | { |
714 | size_t bytes; | |
715 | u32 *iopgd = iopgd_offset(obj, da); | |
716 | int nent = 1; | |
bfee0cf0 JA |
717 | dma_addr_t pt_dma; |
718 | unsigned long pd_offset = iopgd_index(da) * sizeof(da); | |
719 | unsigned long pt_offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
720 | |
721 | if (!*iopgd) | |
722 | return 0; | |
723 | ||
a1a54456 | 724 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
725 | int i; |
726 | u32 *iopte = iopte_offset(iopgd, da); | |
727 | ||
728 | bytes = IOPTE_SIZE; | |
729 | if (*iopte & IOPTE_LARGE) { | |
730 | nent *= 16; | |
731 | /* rewind to the 1st entry */ | |
c127c7dc | 732 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
733 | } |
734 | bytes *= nent; | |
735 | memset(iopte, 0, nent * sizeof(*iopte)); | |
04c532a1 | 736 | pt_dma = iopgd_page_paddr(iopgd); |
bfee0cf0 | 737 | flush_iopte_range(obj->dev, pt_dma, pt_offset, nent); |
a9dcad5e HD |
738 | |
739 | /* | |
740 | * do table walk to check if this table is necessary or not | |
741 | */ | |
742 | iopte = iopte_offset(iopgd, 0); | |
743 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
744 | if (iopte[i]) | |
745 | goto out; | |
746 | ||
bfee0cf0 | 747 | iopte_free(obj, iopte, true); |
a9dcad5e HD |
748 | nent = 1; /* for the next L1 entry */ |
749 | } else { | |
750 | bytes = IOPGD_SIZE; | |
dcc730dc | 751 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
752 | nent *= 16; |
753 | /* rewind to the 1st entry */ | |
8d33ea58 | 754 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
755 | } |
756 | bytes *= nent; | |
757 | } | |
758 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
bfee0cf0 | 759 | flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent); |
a9dcad5e HD |
760 | out: |
761 | return bytes; | |
762 | } | |
763 | ||
764 | /** | |
765 | * iopgtable_clear_entry - Remove an iommu pte entry | |
766 | * @obj: target iommu | |
767 | * @da: iommu device virtual address | |
768 | **/ | |
6c32df43 | 769 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
770 | { |
771 | size_t bytes; | |
772 | ||
773 | spin_lock(&obj->page_table_lock); | |
774 | ||
775 | bytes = iopgtable_clear_entry_core(obj, da); | |
776 | flush_iotlb_page(obj, da); | |
777 | ||
778 | spin_unlock(&obj->page_table_lock); | |
779 | ||
780 | return bytes; | |
781 | } | |
a9dcad5e | 782 | |
6c32df43 | 783 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e | 784 | { |
bfee0cf0 | 785 | unsigned long offset; |
a9dcad5e HD |
786 | int i; |
787 | ||
788 | spin_lock(&obj->page_table_lock); | |
789 | ||
790 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
791 | u32 da; | |
792 | u32 *iopgd; | |
793 | ||
794 | da = i << IOPGD_SHIFT; | |
795 | iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 796 | offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
797 | |
798 | if (!*iopgd) | |
799 | continue; | |
800 | ||
a1a54456 | 801 | if (iopgd_is_table(*iopgd)) |
bfee0cf0 | 802 | iopte_free(obj, iopte_offset(iopgd, 0), true); |
a9dcad5e HD |
803 | |
804 | *iopgd = 0; | |
bfee0cf0 | 805 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
806 | } |
807 | ||
808 | flush_iotlb_all(obj); | |
809 | ||
810 | spin_unlock(&obj->page_table_lock); | |
811 | } | |
812 | ||
813 | /* | |
814 | * Device IOMMU generic operations | |
815 | */ | |
816 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
817 | { | |
d594f1f3 | 818 | u32 da, errs; |
a9dcad5e | 819 | u32 *iopgd, *iopte; |
6c32df43 | 820 | struct omap_iommu *obj = data; |
e7f10f02 | 821 | struct iommu_domain *domain = obj->domain; |
8cf851e0 | 822 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
a9dcad5e | 823 | |
0d364288 | 824 | if (!omap_domain->dev) |
a9dcad5e HD |
825 | return IRQ_NONE; |
826 | ||
d594f1f3 | 827 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
828 | if (errs == 0) |
829 | return IRQ_HANDLED; | |
d594f1f3 DC |
830 | |
831 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 832 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
833 | return IRQ_HANDLED; |
834 | ||
159d3e35 | 835 | iommu_write_reg(obj, 0, MMU_IRQENABLE); |
37b29810 | 836 | |
a9dcad5e HD |
837 | iopgd = iopgd_offset(obj, da); |
838 | ||
a1a54456 | 839 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f | 840 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
5835b6a6 | 841 | obj->name, errs, da, iopgd, *iopgd); |
a9dcad5e HD |
842 | return IRQ_NONE; |
843 | } | |
844 | ||
845 | iopte = iopte_offset(iopgd, da); | |
846 | ||
b6c2e09f | 847 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
5835b6a6 | 848 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); |
a9dcad5e HD |
849 | |
850 | return IRQ_NONE; | |
851 | } | |
852 | ||
a9dcad5e | 853 | /** |
f626b52d | 854 | * omap_iommu_attach() - attach iommu device to an iommu domain |
ede1c2e7 | 855 | * @obj: target omap iommu device |
f626b52d | 856 | * @iopgd: page table |
a9dcad5e | 857 | **/ |
ede1c2e7 | 858 | static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd) |
a9dcad5e | 859 | { |
7ee08b9e | 860 | int err; |
a9dcad5e | 861 | |
f626b52d | 862 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 863 | |
bfee0cf0 JA |
864 | obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE, |
865 | DMA_TO_DEVICE); | |
866 | if (dma_mapping_error(obj->dev, obj->pd_dma)) { | |
867 | dev_err(obj->dev, "DMA map error for L1 table\n"); | |
868 | err = -ENOMEM; | |
869 | goto out_err; | |
870 | } | |
871 | ||
f626b52d OBC |
872 | obj->iopgd = iopgd; |
873 | err = iommu_enable(obj); | |
874 | if (err) | |
bfee0cf0 | 875 | goto out_err; |
f626b52d OBC |
876 | flush_iotlb_all(obj); |
877 | ||
f626b52d | 878 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
879 | |
880 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
ede1c2e7 JR |
881 | |
882 | return 0; | |
a9dcad5e | 883 | |
bfee0cf0 | 884 | out_err: |
f626b52d | 885 | spin_unlock(&obj->iommu_lock); |
ede1c2e7 JR |
886 | |
887 | return err; | |
a9dcad5e | 888 | } |
a9dcad5e HD |
889 | |
890 | /** | |
f626b52d | 891 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
892 | * @obj: target iommu |
893 | **/ | |
6c32df43 | 894 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 895 | { |
acf9d467 | 896 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
897 | return; |
898 | ||
f626b52d | 899 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 900 | |
bfee0cf0 JA |
901 | dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE, |
902 | DMA_TO_DEVICE); | |
bfee0cf0 | 903 | obj->pd_dma = 0; |
f626b52d | 904 | obj->iopgd = NULL; |
c3b44a06 | 905 | iommu_disable(obj); |
d594f1f3 | 906 | |
f626b52d | 907 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 908 | |
a9dcad5e | 909 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 910 | } |
d594f1f3 | 911 | |
c3b44a06 SA |
912 | static void omap_iommu_save_tlb_entries(struct omap_iommu *obj) |
913 | { | |
914 | struct iotlb_lock lock; | |
915 | struct cr_regs cr; | |
916 | struct cr_regs *tmp; | |
917 | int i; | |
918 | ||
919 | /* check if there are any locked tlbs to save */ | |
920 | iotlb_lock_get(obj, &lock); | |
921 | obj->num_cr_ctx = lock.base; | |
922 | if (!obj->num_cr_ctx) | |
923 | return; | |
924 | ||
925 | tmp = obj->cr_ctx; | |
926 | for_each_iotlb_cr(obj, obj->num_cr_ctx, i, cr) | |
927 | * tmp++ = cr; | |
928 | } | |
929 | ||
930 | static void omap_iommu_restore_tlb_entries(struct omap_iommu *obj) | |
931 | { | |
932 | struct iotlb_lock l; | |
933 | struct cr_regs *tmp; | |
934 | int i; | |
935 | ||
936 | /* no locked tlbs to restore */ | |
937 | if (!obj->num_cr_ctx) | |
938 | return; | |
939 | ||
940 | l.base = 0; | |
941 | tmp = obj->cr_ctx; | |
942 | for (i = 0; i < obj->num_cr_ctx; i++, tmp++) { | |
943 | l.vict = i; | |
944 | iotlb_lock_set(obj, &l); | |
945 | iotlb_load_cr(obj, tmp); | |
946 | } | |
947 | l.base = obj->num_cr_ctx; | |
948 | l.vict = i; | |
949 | iotlb_lock_set(obj, &l); | |
950 | } | |
951 | ||
d9c4d8a6 SA |
952 | /** |
953 | * omap_iommu_domain_deactivate - deactivate attached iommu devices | |
954 | * @domain: iommu domain attached to the target iommu device | |
955 | * | |
956 | * This API allows the client devices of IOMMU devices to suspend | |
957 | * the IOMMUs they control at runtime, after they are idled and | |
958 | * suspended all activity. System Suspend will leverage the PM | |
959 | * driver late callbacks. | |
960 | **/ | |
961 | int omap_iommu_domain_deactivate(struct iommu_domain *domain) | |
962 | { | |
963 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); | |
964 | struct omap_iommu_device *iommu; | |
965 | struct omap_iommu *oiommu; | |
966 | int i; | |
967 | ||
968 | if (!omap_domain->dev) | |
969 | return 0; | |
970 | ||
971 | iommu = omap_domain->iommus; | |
972 | iommu += (omap_domain->num_iommus - 1); | |
973 | for (i = 0; i < omap_domain->num_iommus; i++, iommu--) { | |
974 | oiommu = iommu->iommu_dev; | |
975 | pm_runtime_put_sync(oiommu->dev); | |
976 | } | |
977 | ||
978 | return 0; | |
979 | } | |
980 | EXPORT_SYMBOL_GPL(omap_iommu_domain_deactivate); | |
981 | ||
982 | /** | |
983 | * omap_iommu_domain_activate - activate attached iommu devices | |
984 | * @domain: iommu domain attached to the target iommu device | |
985 | * | |
986 | * This API allows the client devices of IOMMU devices to resume the | |
987 | * IOMMUs they control at runtime, before they can resume operations. | |
988 | * System Resume will leverage the PM driver late callbacks. | |
989 | **/ | |
990 | int omap_iommu_domain_activate(struct iommu_domain *domain) | |
991 | { | |
992 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); | |
993 | struct omap_iommu_device *iommu; | |
994 | struct omap_iommu *oiommu; | |
995 | int i; | |
996 | ||
997 | if (!omap_domain->dev) | |
998 | return 0; | |
999 | ||
1000 | iommu = omap_domain->iommus; | |
1001 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1002 | oiommu = iommu->iommu_dev; | |
1003 | pm_runtime_get_sync(oiommu->dev); | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | EXPORT_SYMBOL_GPL(omap_iommu_domain_activate); | |
1009 | ||
db8918f6 SA |
1010 | /** |
1011 | * omap_iommu_runtime_suspend - disable an iommu device | |
1012 | * @dev: iommu device | |
1013 | * | |
1014 | * This function performs all that is necessary to disable an | |
1015 | * IOMMU device, either during final detachment from a client | |
1016 | * device, or during system/runtime suspend of the device. This | |
1017 | * includes programming all the appropriate IOMMU registers, and | |
1018 | * managing the associated omap_hwmod's state and the device's | |
c3b44a06 SA |
1019 | * reset line. This function also saves the context of any |
1020 | * locked TLBs if suspending. | |
db8918f6 | 1021 | **/ |
96088a20 | 1022 | static __maybe_unused int omap_iommu_runtime_suspend(struct device *dev) |
db8918f6 SA |
1023 | { |
1024 | struct platform_device *pdev = to_platform_device(dev); | |
1025 | struct iommu_platform_data *pdata = dev_get_platdata(dev); | |
1026 | struct omap_iommu *obj = to_iommu(dev); | |
1027 | int ret; | |
1028 | ||
c3b44a06 SA |
1029 | /* save the TLBs only during suspend, and not for power down */ |
1030 | if (obj->domain && obj->iopgd) | |
1031 | omap_iommu_save_tlb_entries(obj); | |
1032 | ||
db8918f6 SA |
1033 | omap2_iommu_disable(obj); |
1034 | ||
1035 | if (pdata && pdata->device_idle) | |
1036 | pdata->device_idle(pdev); | |
1037 | ||
1038 | if (pdata && pdata->assert_reset) | |
1039 | pdata->assert_reset(pdev, pdata->reset_name); | |
1040 | ||
1041 | if (pdata && pdata->set_pwrdm_constraint) { | |
1042 | ret = pdata->set_pwrdm_constraint(pdev, false, &obj->pwrst); | |
1043 | if (ret) { | |
1044 | dev_warn(obj->dev, "pwrdm_constraint failed to be reset, status = %d\n", | |
1045 | ret); | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | /** | |
1053 | * omap_iommu_runtime_resume - enable an iommu device | |
1054 | * @dev: iommu device | |
1055 | * | |
1056 | * This function performs all that is necessary to enable an | |
1057 | * IOMMU device, either during initial attachment to a client | |
1058 | * device, or during system/runtime resume of the device. This | |
1059 | * includes programming all the appropriate IOMMU registers, and | |
1060 | * managing the associated omap_hwmod's state and the device's | |
c3b44a06 SA |
1061 | * reset line. The function also restores any locked TLBs if |
1062 | * resuming after a suspend. | |
db8918f6 | 1063 | **/ |
96088a20 | 1064 | static __maybe_unused int omap_iommu_runtime_resume(struct device *dev) |
db8918f6 SA |
1065 | { |
1066 | struct platform_device *pdev = to_platform_device(dev); | |
1067 | struct iommu_platform_data *pdata = dev_get_platdata(dev); | |
1068 | struct omap_iommu *obj = to_iommu(dev); | |
1069 | int ret = 0; | |
1070 | ||
1071 | if (pdata && pdata->set_pwrdm_constraint) { | |
1072 | ret = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst); | |
1073 | if (ret) { | |
1074 | dev_warn(obj->dev, "pwrdm_constraint failed to be set, status = %d\n", | |
1075 | ret); | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | if (pdata && pdata->deassert_reset) { | |
1080 | ret = pdata->deassert_reset(pdev, pdata->reset_name); | |
1081 | if (ret) { | |
1082 | dev_err(dev, "deassert_reset failed: %d\n", ret); | |
1083 | return ret; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | if (pdata && pdata->device_enable) | |
1088 | pdata->device_enable(pdev); | |
1089 | ||
c3b44a06 SA |
1090 | /* restore the TLBs only during resume, and not for power up */ |
1091 | if (obj->domain) | |
1092 | omap_iommu_restore_tlb_entries(obj); | |
1093 | ||
db8918f6 SA |
1094 | ret = omap2_iommu_enable(obj); |
1095 | ||
1096 | return ret; | |
1097 | } | |
1098 | ||
c4206c4e SA |
1099 | /** |
1100 | * omap_iommu_suspend_prepare - prepare() dev_pm_ops implementation | |
1101 | * @dev: iommu device | |
1102 | * | |
1103 | * This function performs the necessary checks to determine if the IOMMU | |
1104 | * device needs suspending or not. The function checks if the runtime_pm | |
1105 | * status of the device is suspended, and returns 1 in that case. This | |
1106 | * results in the PM core to skip invoking any of the Sleep PM callbacks | |
1107 | * (suspend, suspend_late, resume, resume_early etc). | |
1108 | */ | |
1109 | static int omap_iommu_prepare(struct device *dev) | |
1110 | { | |
1111 | if (pm_runtime_status_suspended(dev)) | |
1112 | return 1; | |
1113 | return 0; | |
1114 | } | |
1115 | ||
9d5018de SA |
1116 | static bool omap_iommu_can_register(struct platform_device *pdev) |
1117 | { | |
1118 | struct device_node *np = pdev->dev.of_node; | |
1119 | ||
1120 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
1121 | return true; | |
1122 | ||
1123 | /* | |
1124 | * restrict IOMMU core registration only for processor-port MDMA MMUs | |
1125 | * on DRA7 DSPs | |
1126 | */ | |
1127 | if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) || | |
1128 | (!strcmp(dev_name(&pdev->dev), "41501000.mmu"))) | |
1129 | return true; | |
1130 | ||
1131 | return false; | |
1132 | } | |
1133 | ||
3ca9299e SA |
1134 | static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev, |
1135 | struct omap_iommu *obj) | |
1136 | { | |
1137 | struct device_node *np = pdev->dev.of_node; | |
1138 | int ret; | |
1139 | ||
1140 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
1141 | return 0; | |
1142 | ||
1143 | if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) { | |
1144 | dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n"); | |
1145 | return -EINVAL; | |
1146 | } | |
1147 | ||
1148 | obj->syscfg = | |
1149 | syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig"); | |
1150 | if (IS_ERR(obj->syscfg)) { | |
1151 | /* can fail with -EPROBE_DEFER */ | |
1152 | ret = PTR_ERR(obj->syscfg); | |
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1, | |
1157 | &obj->id)) { | |
1158 | dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n"); | |
1159 | return -EINVAL; | |
1160 | } | |
1161 | ||
1162 | if (obj->id != 0 && obj->id != 1) { | |
1163 | dev_err(&pdev->dev, "invalid IOMMU instance id\n"); | |
1164 | return -EINVAL; | |
1165 | } | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
a9dcad5e HD |
1170 | /* |
1171 | * OMAP Device MMU(IOMMU) detection | |
1172 | */ | |
d34d6517 | 1173 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
1174 | { |
1175 | int err = -ENODEV; | |
a9dcad5e | 1176 | int irq; |
6c32df43 | 1177 | struct omap_iommu *obj; |
a9dcad5e | 1178 | struct resource *res; |
3c92748d | 1179 | struct device_node *of = pdev->dev.of_node; |
604629bc | 1180 | struct orphan_dev *orphan_dev, *tmp; |
a9dcad5e | 1181 | |
49a57ef7 SA |
1182 | if (!of) { |
1183 | pr_err("%s: only DT-based devices are supported\n", __func__); | |
1184 | return -ENODEV; | |
1185 | } | |
1186 | ||
f129b3df | 1187 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
1188 | if (!obj) |
1189 | return -ENOMEM; | |
1190 | ||
db8918f6 SA |
1191 | /* |
1192 | * self-manage the ordering dependencies between omap_device_enable/idle | |
1193 | * and omap_device_assert/deassert_hardreset API | |
1194 | */ | |
1195 | if (pdev->dev.pm_domain) { | |
1196 | dev_dbg(&pdev->dev, "device pm_domain is being reset\n"); | |
1197 | pdev->dev.pm_domain = NULL; | |
1198 | } | |
1199 | ||
49a57ef7 SA |
1200 | obj->name = dev_name(&pdev->dev); |
1201 | obj->nr_tlb_entries = 32; | |
1202 | err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries); | |
1203 | if (err && err != -EINVAL) | |
1204 | return err; | |
1205 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
1206 | return -EINVAL; | |
1207 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) | |
1208 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d | 1209 | |
a9dcad5e HD |
1210 | obj->dev = &pdev->dev; |
1211 | obj->ctx = (void *)obj + sizeof(*obj); | |
c3b44a06 SA |
1212 | obj->cr_ctx = devm_kzalloc(&pdev->dev, |
1213 | sizeof(*obj->cr_ctx) * obj->nr_tlb_entries, | |
1214 | GFP_KERNEL); | |
1215 | if (!obj->cr_ctx) | |
1216 | return -ENOMEM; | |
a9dcad5e | 1217 | |
f626b52d | 1218 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 1219 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
1220 | |
1221 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
1222 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
1223 | if (IS_ERR(obj->regbase)) | |
1224 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 1225 | |
3ca9299e SA |
1226 | err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj); |
1227 | if (err) | |
1228 | return err; | |
1229 | ||
a9dcad5e | 1230 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
1231 | if (irq < 0) |
1232 | return -ENODEV; | |
1233 | ||
1234 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
1235 | dev_name(obj->dev), obj); | |
a9dcad5e | 1236 | if (err < 0) |
f129b3df | 1237 | return err; |
a9dcad5e HD |
1238 | platform_set_drvdata(pdev, obj); |
1239 | ||
9d5018de SA |
1240 | if (omap_iommu_can_register(pdev)) { |
1241 | obj->group = iommu_group_alloc(); | |
1242 | if (IS_ERR(obj->group)) | |
1243 | return PTR_ERR(obj->group); | |
28ae1e3e | 1244 | |
9d5018de SA |
1245 | err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL, |
1246 | obj->name); | |
1247 | if (err) | |
1248 | goto out_group; | |
01611fe8 | 1249 | |
9d5018de | 1250 | iommu_device_set_ops(&obj->iommu, &omap_iommu_ops); |
01611fe8 | 1251 | |
9d5018de SA |
1252 | err = iommu_device_register(&obj->iommu); |
1253 | if (err) | |
1254 | goto out_sysfs; | |
1255 | } | |
01611fe8 | 1256 | |
ebf7cda0 ORL |
1257 | pm_runtime_enable(obj->dev); |
1258 | ||
61c75352 SA |
1259 | omap_iommu_debugfs_add(obj); |
1260 | ||
a9dcad5e | 1261 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
28ae1e3e | 1262 | |
604629bc TK |
1263 | list_for_each_entry_safe(orphan_dev, tmp, &orphan_dev_list, node) { |
1264 | err = _omap_iommu_add_device(orphan_dev->dev); | |
1265 | if (!err) { | |
1266 | list_del(&orphan_dev->node); | |
1267 | kfree(orphan_dev); | |
1268 | } | |
1269 | } | |
1270 | ||
a9dcad5e | 1271 | return 0; |
01611fe8 JR |
1272 | |
1273 | out_sysfs: | |
1274 | iommu_device_sysfs_remove(&obj->iommu); | |
28ae1e3e JR |
1275 | out_group: |
1276 | iommu_group_put(obj->group); | |
01611fe8 | 1277 | return err; |
a9dcad5e HD |
1278 | } |
1279 | ||
d34d6517 | 1280 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 1281 | { |
6c32df43 | 1282 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 1283 | |
9d5018de SA |
1284 | if (obj->group) { |
1285 | iommu_group_put(obj->group); | |
1286 | obj->group = NULL; | |
28ae1e3e | 1287 | |
9d5018de SA |
1288 | iommu_device_sysfs_remove(&obj->iommu); |
1289 | iommu_device_unregister(&obj->iommu); | |
1290 | } | |
01611fe8 | 1291 | |
61c75352 | 1292 | omap_iommu_debugfs_remove(obj); |
a9dcad5e | 1293 | |
ebf7cda0 ORL |
1294 | pm_runtime_disable(obj->dev); |
1295 | ||
a9dcad5e | 1296 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
1297 | return 0; |
1298 | } | |
1299 | ||
db8918f6 | 1300 | static const struct dev_pm_ops omap_iommu_pm_ops = { |
c4206c4e SA |
1301 | .prepare = omap_iommu_prepare, |
1302 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1303 | pm_runtime_force_resume) | |
db8918f6 SA |
1304 | SET_RUNTIME_PM_OPS(omap_iommu_runtime_suspend, |
1305 | omap_iommu_runtime_resume, NULL) | |
1306 | }; | |
1307 | ||
d943b0ff | 1308 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
1309 | { .compatible = "ti,omap2-iommu" }, |
1310 | { .compatible = "ti,omap4-iommu" }, | |
1311 | { .compatible = "ti,dra7-iommu" }, | |
3ca9299e | 1312 | { .compatible = "ti,dra7-dsp-iommu" }, |
3c92748d FV |
1313 | {}, |
1314 | }; | |
3c92748d | 1315 | |
a9dcad5e HD |
1316 | static struct platform_driver omap_iommu_driver = { |
1317 | .probe = omap_iommu_probe, | |
d34d6517 | 1318 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1319 | .driver = { |
1320 | .name = "omap-iommu", | |
db8918f6 | 1321 | .pm = &omap_iommu_pm_ops, |
3c92748d | 1322 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1323 | }, |
1324 | }; | |
1325 | ||
286f600b | 1326 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1327 | { |
1328 | memset(e, 0, sizeof(*e)); | |
1329 | ||
1330 | e->da = da; | |
1331 | e->pa = pa; | |
d760e3e0 | 1332 | e->valid = MMU_CAM_V; |
286f600b LP |
1333 | e->pgsz = pgsz; |
1334 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1335 | e->elsz = MMU_RAM_ELSZ_8; | |
1336 | e->mixed = 0; | |
ed1c7de2 TL |
1337 | |
1338 | return iopgsz_to_bytes(e->pgsz); | |
1339 | } | |
1340 | ||
f626b52d | 1341 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5835b6a6 | 1342 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d | 1343 | { |
8cf851e0 | 1344 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1345 | struct device *dev = omap_domain->dev; |
1346 | struct omap_iommu_device *iommu; | |
1347 | struct omap_iommu *oiommu; | |
f626b52d OBC |
1348 | struct iotlb_entry e; |
1349 | int omap_pgsz; | |
9d5018de SA |
1350 | u32 ret = -EINVAL; |
1351 | int i; | |
f626b52d | 1352 | |
f626b52d OBC |
1353 | omap_pgsz = bytes_to_iopgsz(bytes); |
1354 | if (omap_pgsz < 0) { | |
1355 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1356 | return -EINVAL; | |
1357 | } | |
1358 | ||
1d7f449c | 1359 | dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes); |
f626b52d | 1360 | |
286f600b | 1361 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1362 | |
9d5018de SA |
1363 | iommu = omap_domain->iommus; |
1364 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1365 | oiommu = iommu->iommu_dev; | |
1366 | ret = omap_iopgtable_store_entry(oiommu, &e); | |
1367 | if (ret) { | |
1368 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", | |
1369 | ret); | |
1370 | break; | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | if (ret) { | |
1375 | while (i--) { | |
1376 | iommu--; | |
1377 | oiommu = iommu->iommu_dev; | |
1378 | iopgtable_clear_entry(oiommu, da); | |
1379 | } | |
1380 | } | |
f626b52d | 1381 | |
b4550d41 | 1382 | return ret; |
f626b52d OBC |
1383 | } |
1384 | ||
5009065d | 1385 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
56f8af5e | 1386 | size_t size, struct iommu_iotlb_gather *gather) |
f626b52d | 1387 | { |
8cf851e0 | 1388 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1389 | struct device *dev = omap_domain->dev; |
1390 | struct omap_iommu_device *iommu; | |
1391 | struct omap_iommu *oiommu; | |
1392 | bool error = false; | |
1393 | size_t bytes = 0; | |
1394 | int i; | |
f626b52d | 1395 | |
5009065d | 1396 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1397 | |
9d5018de SA |
1398 | iommu = omap_domain->iommus; |
1399 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1400 | oiommu = iommu->iommu_dev; | |
1401 | bytes = iopgtable_clear_entry(oiommu, da); | |
1402 | if (!bytes) | |
1403 | error = true; | |
1404 | } | |
1405 | ||
1406 | /* | |
1407 | * simplify return - we are only checking if any of the iommus | |
1408 | * reported an error, but not if all of them are unmapping the | |
1409 | * same number of entries. This should not occur due to the | |
1410 | * mirror programming. | |
1411 | */ | |
1412 | return error ? 0 : bytes; | |
1413 | } | |
1414 | ||
1415 | static int omap_iommu_count(struct device *dev) | |
1416 | { | |
1417 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1418 | int count = 0; | |
1419 | ||
1420 | while (arch_data->iommu_dev) { | |
1421 | count++; | |
1422 | arch_data++; | |
1423 | } | |
1424 | ||
1425 | return count; | |
1426 | } | |
1427 | ||
1428 | /* caller should call cleanup if this function fails */ | |
1429 | static int omap_iommu_attach_init(struct device *dev, | |
1430 | struct omap_iommu_domain *odomain) | |
1431 | { | |
1432 | struct omap_iommu_device *iommu; | |
1433 | int i; | |
1434 | ||
1435 | odomain->num_iommus = omap_iommu_count(dev); | |
1436 | if (!odomain->num_iommus) | |
1437 | return -EINVAL; | |
1438 | ||
1439 | odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu), | |
1440 | GFP_ATOMIC); | |
1441 | if (!odomain->iommus) | |
1442 | return -ENOMEM; | |
1443 | ||
1444 | iommu = odomain->iommus; | |
1445 | for (i = 0; i < odomain->num_iommus; i++, iommu++) { | |
1446 | iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC); | |
1447 | if (!iommu->pgtable) | |
1448 | return -ENOMEM; | |
1449 | ||
1450 | /* | |
1451 | * should never fail, but please keep this around to ensure | |
1452 | * we keep the hardware happy | |
1453 | */ | |
1454 | if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable, | |
1455 | IOPGD_TABLE_SIZE))) | |
1456 | return -EINVAL; | |
1457 | } | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain) | |
1463 | { | |
1464 | int i; | |
1465 | struct omap_iommu_device *iommu = odomain->iommus; | |
1466 | ||
1467 | for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++) | |
1468 | kfree(iommu->pgtable); | |
1469 | ||
1470 | kfree(odomain->iommus); | |
1471 | odomain->num_iommus = 0; | |
1472 | odomain->iommus = NULL; | |
f626b52d OBC |
1473 | } |
1474 | ||
1475 | static int | |
1476 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1477 | { | |
8cf851e0 | 1478 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
fabdbca8 | 1479 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
9d5018de | 1480 | struct omap_iommu_device *iommu; |
ede1c2e7 | 1481 | struct omap_iommu *oiommu; |
f626b52d | 1482 | int ret = 0; |
9d5018de | 1483 | int i; |
f626b52d | 1484 | |
ede1c2e7 | 1485 | if (!arch_data || !arch_data->iommu_dev) { |
e3f595b9 SA |
1486 | dev_err(dev, "device doesn't have an associated iommu\n"); |
1487 | return -EINVAL; | |
1488 | } | |
1489 | ||
f626b52d OBC |
1490 | spin_lock(&omap_domain->lock); |
1491 | ||
0d364288 SA |
1492 | /* only a single client device can be attached to a domain */ |
1493 | if (omap_domain->dev) { | |
f626b52d OBC |
1494 | dev_err(dev, "iommu domain is already attached\n"); |
1495 | ret = -EBUSY; | |
1496 | goto out; | |
1497 | } | |
1498 | ||
9d5018de | 1499 | ret = omap_iommu_attach_init(dev, omap_domain); |
ede1c2e7 | 1500 | if (ret) { |
9d5018de SA |
1501 | dev_err(dev, "failed to allocate required iommu data %d\n", |
1502 | ret); | |
1503 | goto init_fail; | |
1504 | } | |
1505 | ||
1506 | iommu = omap_domain->iommus; | |
1507 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) { | |
1508 | /* configure and enable the omap iommu */ | |
1509 | oiommu = arch_data->iommu_dev; | |
1510 | ret = omap_iommu_attach(oiommu, iommu->pgtable); | |
1511 | if (ret) { | |
1512 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1513 | goto attach_fail; | |
1514 | } | |
1515 | ||
1516 | oiommu->domain = domain; | |
1517 | iommu->iommu_dev = oiommu; | |
f626b52d OBC |
1518 | } |
1519 | ||
803b5277 | 1520 | omap_domain->dev = dev; |
f626b52d | 1521 | |
9d5018de SA |
1522 | goto out; |
1523 | ||
1524 | attach_fail: | |
1525 | while (i--) { | |
1526 | iommu--; | |
1527 | arch_data--; | |
1528 | oiommu = iommu->iommu_dev; | |
1529 | omap_iommu_detach(oiommu); | |
1530 | iommu->iommu_dev = NULL; | |
1531 | oiommu->domain = NULL; | |
1532 | } | |
1533 | init_fail: | |
1534 | omap_iommu_detach_fini(omap_domain); | |
f626b52d OBC |
1535 | out: |
1536 | spin_unlock(&omap_domain->lock); | |
1537 | return ret; | |
1538 | } | |
1539 | ||
803b5277 | 1540 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
5835b6a6 | 1541 | struct device *dev) |
f626b52d | 1542 | { |
9d5018de SA |
1543 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
1544 | struct omap_iommu_device *iommu = omap_domain->iommus; | |
1545 | struct omap_iommu *oiommu; | |
1546 | int i; | |
f626b52d | 1547 | |
0d364288 SA |
1548 | if (!omap_domain->dev) { |
1549 | dev_err(dev, "domain has no attached device\n"); | |
1550 | return; | |
1551 | } | |
1552 | ||
f626b52d | 1553 | /* only a single device is supported per domain for now */ |
0d364288 SA |
1554 | if (omap_domain->dev != dev) { |
1555 | dev_err(dev, "invalid attached device\n"); | |
803b5277 | 1556 | return; |
f626b52d OBC |
1557 | } |
1558 | ||
9d5018de SA |
1559 | /* |
1560 | * cleanup in the reverse order of attachment - this addresses | |
1561 | * any h/w dependencies between multiple instances, if any | |
1562 | */ | |
1563 | iommu += (omap_domain->num_iommus - 1); | |
1564 | arch_data += (omap_domain->num_iommus - 1); | |
1565 | for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) { | |
1566 | oiommu = iommu->iommu_dev; | |
1567 | iopgtable_clear_entry_all(oiommu); | |
1568 | ||
1569 | omap_iommu_detach(oiommu); | |
1570 | iommu->iommu_dev = NULL; | |
1571 | oiommu->domain = NULL; | |
1572 | } | |
f626b52d | 1573 | |
9d5018de | 1574 | omap_iommu_detach_fini(omap_domain); |
f626b52d | 1575 | |
803b5277 ORL |
1576 | omap_domain->dev = NULL; |
1577 | } | |
f626b52d | 1578 | |
803b5277 | 1579 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
5835b6a6 | 1580 | struct device *dev) |
803b5277 | 1581 | { |
8cf851e0 | 1582 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
803b5277 ORL |
1583 | |
1584 | spin_lock(&omap_domain->lock); | |
1585 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1586 | spin_unlock(&omap_domain->lock); |
1587 | } | |
1588 | ||
8cf851e0 | 1589 | static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) |
f626b52d OBC |
1590 | { |
1591 | struct omap_iommu_domain *omap_domain; | |
1592 | ||
8cf851e0 JR |
1593 | if (type != IOMMU_DOMAIN_UNMANAGED) |
1594 | return NULL; | |
1595 | ||
f626b52d | 1596 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); |
99ee98d6 | 1597 | if (!omap_domain) |
9d5018de | 1598 | return NULL; |
f626b52d | 1599 | |
f626b52d OBC |
1600 | spin_lock_init(&omap_domain->lock); |
1601 | ||
8cf851e0 JR |
1602 | omap_domain->domain.geometry.aperture_start = 0; |
1603 | omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; | |
1604 | omap_domain->domain.geometry.force_aperture = true; | |
f626b52d | 1605 | |
8cf851e0 | 1606 | return &omap_domain->domain; |
f626b52d OBC |
1607 | } |
1608 | ||
8cf851e0 | 1609 | static void omap_iommu_domain_free(struct iommu_domain *domain) |
f626b52d | 1610 | { |
8cf851e0 | 1611 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
f626b52d | 1612 | |
803b5277 ORL |
1613 | /* |
1614 | * An iommu device is still attached | |
1615 | * (currently, only one device can be attached) ? | |
1616 | */ | |
0d364288 | 1617 | if (omap_domain->dev) |
803b5277 ORL |
1618 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); |
1619 | ||
f626b52d OBC |
1620 | kfree(omap_domain); |
1621 | } | |
1622 | ||
1623 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
5835b6a6 | 1624 | dma_addr_t da) |
f626b52d | 1625 | { |
8cf851e0 | 1626 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1627 | struct omap_iommu_device *iommu = omap_domain->iommus; |
1628 | struct omap_iommu *oiommu = iommu->iommu_dev; | |
f626b52d OBC |
1629 | struct device *dev = oiommu->dev; |
1630 | u32 *pgd, *pte; | |
1631 | phys_addr_t ret = 0; | |
1632 | ||
9d5018de SA |
1633 | /* |
1634 | * all the iommus within the domain will have identical programming, | |
1635 | * so perform the lookup using just the first iommu | |
1636 | */ | |
f626b52d OBC |
1637 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); |
1638 | ||
1639 | if (pte) { | |
1640 | if (iopte_is_small(*pte)) | |
1641 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1642 | else if (iopte_is_large(*pte)) | |
1643 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1644 | else | |
2abfcfbc | 1645 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
5835b6a6 | 1646 | (unsigned long long)da); |
f626b52d OBC |
1647 | } else { |
1648 | if (iopgd_is_section(*pgd)) | |
1649 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1650 | else if (iopgd_is_super(*pgd)) | |
1651 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1652 | else | |
2abfcfbc | 1653 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
5835b6a6 | 1654 | (unsigned long long)da); |
f626b52d OBC |
1655 | } |
1656 | ||
1657 | return ret; | |
1658 | } | |
1659 | ||
604629bc | 1660 | static int _omap_iommu_add_device(struct device *dev) |
07a02030 | 1661 | { |
9d5018de | 1662 | struct omap_iommu_arch_data *arch_data, *tmp; |
ede1c2e7 | 1663 | struct omap_iommu *oiommu; |
28ae1e3e | 1664 | struct iommu_group *group; |
07a02030 | 1665 | struct device_node *np; |
7d682774 | 1666 | struct platform_device *pdev; |
9d5018de | 1667 | int num_iommus, i; |
01611fe8 | 1668 | int ret; |
604629bc TK |
1669 | struct orphan_dev *orphan_dev; |
1670 | unsigned long flags; | |
07a02030 LP |
1671 | |
1672 | /* | |
1673 | * Allocate the archdata iommu structure for DT-based devices. | |
1674 | * | |
1675 | * TODO: Simplify this when removing non-DT support completely from the | |
1676 | * IOMMU users. | |
1677 | */ | |
1678 | if (!dev->of_node) | |
1679 | return 0; | |
1680 | ||
9d5018de SA |
1681 | /* |
1682 | * retrieve the count of IOMMU nodes using phandle size as element size | |
1683 | * since #iommu-cells = 0 for OMAP | |
1684 | */ | |
1685 | num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", | |
1686 | sizeof(phandle)); | |
1687 | if (num_iommus < 0) | |
07a02030 LP |
1688 | return 0; |
1689 | ||
6396bb22 | 1690 | arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); |
9d5018de SA |
1691 | if (!arch_data) |
1692 | return -ENOMEM; | |
7d682774 | 1693 | |
9d5018de SA |
1694 | for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) { |
1695 | np = of_parse_phandle(dev->of_node, "iommus", i); | |
1696 | if (!np) { | |
1697 | kfree(arch_data); | |
1698 | return -EINVAL; | |
1699 | } | |
1700 | ||
1701 | pdev = of_find_device_by_node(np); | |
604629bc | 1702 | if (!pdev) { |
9d5018de SA |
1703 | of_node_put(np); |
1704 | kfree(arch_data); | |
604629bc TK |
1705 | spin_lock_irqsave(&orphan_lock, flags); |
1706 | list_for_each_entry(orphan_dev, &orphan_dev_list, | |
1707 | node) { | |
1708 | if (orphan_dev->dev == dev) | |
1709 | break; | |
1710 | } | |
1711 | spin_unlock_irqrestore(&orphan_lock, flags); | |
1712 | ||
1713 | if (orphan_dev && orphan_dev->dev == dev) | |
1714 | return -EPROBE_DEFER; | |
1715 | ||
1716 | orphan_dev = kzalloc(sizeof(*orphan_dev), GFP_KERNEL); | |
1717 | orphan_dev->dev = dev; | |
1718 | spin_lock_irqsave(&orphan_lock, flags); | |
1719 | list_add(&orphan_dev->node, &orphan_dev_list); | |
1720 | spin_unlock_irqrestore(&orphan_lock, flags); | |
1721 | return -EPROBE_DEFER; | |
9d5018de SA |
1722 | } |
1723 | ||
1724 | oiommu = platform_get_drvdata(pdev); | |
1725 | if (!oiommu) { | |
1726 | of_node_put(np); | |
1727 | kfree(arch_data); | |
1728 | return -EINVAL; | |
1729 | } | |
1730 | ||
1731 | tmp->iommu_dev = oiommu; | |
604629bc | 1732 | tmp->dev = &pdev->dev; |
ede1c2e7 | 1733 | |
07a02030 | 1734 | of_node_put(np); |
07a02030 LP |
1735 | } |
1736 | ||
9d5018de SA |
1737 | /* |
1738 | * use the first IOMMU alone for the sysfs device linking. | |
1739 | * TODO: Evaluate if a single iommu_group needs to be | |
1740 | * maintained for both IOMMUs | |
1741 | */ | |
1742 | oiommu = arch_data->iommu_dev; | |
01611fe8 JR |
1743 | ret = iommu_device_link(&oiommu->iommu, dev); |
1744 | if (ret) { | |
1745 | kfree(arch_data); | |
01611fe8 JR |
1746 | return ret; |
1747 | } | |
1748 | ||
07a02030 LP |
1749 | dev->archdata.iommu = arch_data; |
1750 | ||
28ae1e3e JR |
1751 | /* |
1752 | * IOMMU group initialization calls into omap_iommu_device_group, which | |
1753 | * needs a valid dev->archdata.iommu pointer | |
1754 | */ | |
1755 | group = iommu_group_get_for_dev(dev); | |
1756 | if (IS_ERR(group)) { | |
1757 | iommu_device_unlink(&oiommu->iommu, dev); | |
1758 | dev->archdata.iommu = NULL; | |
1759 | kfree(arch_data); | |
1760 | return PTR_ERR(group); | |
1761 | } | |
1762 | iommu_group_put(group); | |
1763 | ||
07a02030 LP |
1764 | return 0; |
1765 | } | |
1766 | ||
604629bc TK |
1767 | static int omap_iommu_add_device(struct device *dev) |
1768 | { | |
1769 | int ret; | |
1770 | ||
1771 | ret = _omap_iommu_add_device(dev); | |
1772 | if (ret == -EPROBE_DEFER) | |
1773 | return 0; | |
1774 | ||
1775 | return ret; | |
1776 | } | |
1777 | ||
07a02030 LP |
1778 | static void omap_iommu_remove_device(struct device *dev) |
1779 | { | |
1780 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1781 | ||
1782 | if (!dev->of_node || !arch_data) | |
1783 | return; | |
1784 | ||
01611fe8 | 1785 | iommu_device_unlink(&arch_data->iommu_dev->iommu, dev); |
28ae1e3e | 1786 | iommu_group_remove_device(dev); |
01611fe8 | 1787 | |
ede1c2e7 | 1788 | dev->archdata.iommu = NULL; |
07a02030 | 1789 | kfree(arch_data); |
01611fe8 | 1790 | |
07a02030 LP |
1791 | } |
1792 | ||
28ae1e3e JR |
1793 | static struct iommu_group *omap_iommu_device_group(struct device *dev) |
1794 | { | |
1795 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
8faf5e5a | 1796 | struct iommu_group *group = ERR_PTR(-EINVAL); |
28ae1e3e JR |
1797 | |
1798 | if (arch_data->iommu_dev) | |
b6d57f1d | 1799 | group = iommu_group_ref_get(arch_data->iommu_dev->group); |
28ae1e3e JR |
1800 | |
1801 | return group; | |
1802 | } | |
1803 | ||
b22f6434 | 1804 | static const struct iommu_ops omap_iommu_ops = { |
8cf851e0 JR |
1805 | .domain_alloc = omap_iommu_domain_alloc, |
1806 | .domain_free = omap_iommu_domain_free, | |
f626b52d OBC |
1807 | .attach_dev = omap_iommu_attach_dev, |
1808 | .detach_dev = omap_iommu_detach_dev, | |
1809 | .map = omap_iommu_map, | |
1810 | .unmap = omap_iommu_unmap, | |
1811 | .iova_to_phys = omap_iommu_iova_to_phys, | |
07a02030 LP |
1812 | .add_device = omap_iommu_add_device, |
1813 | .remove_device = omap_iommu_remove_device, | |
28ae1e3e | 1814 | .device_group = omap_iommu_device_group, |
66bc8cf3 | 1815 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1816 | }; |
1817 | ||
a9dcad5e HD |
1818 | static int __init omap_iommu_init(void) |
1819 | { | |
1820 | struct kmem_cache *p; | |
24ce0bab | 1821 | const slab_flags_t flags = SLAB_HWCACHE_ALIGN; |
a9dcad5e | 1822 | size_t align = 1 << 10; /* L2 pagetable alignement */ |
f938aab2 | 1823 | struct device_node *np; |
abaa7e5b | 1824 | int ret; |
f938aab2 TR |
1825 | |
1826 | np = of_find_matching_node(NULL, omap_iommu_of_match); | |
1827 | if (!np) | |
1828 | return 0; | |
1829 | ||
1830 | of_node_put(np); | |
a9dcad5e HD |
1831 | |
1832 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
bfee0cf0 | 1833 | NULL); |
a9dcad5e HD |
1834 | if (!p) |
1835 | return -ENOMEM; | |
1836 | iopte_cachep = p; | |
1837 | ||
61c75352 SA |
1838 | omap_iommu_debugfs_init(); |
1839 | ||
abaa7e5b SA |
1840 | ret = platform_driver_register(&omap_iommu_driver); |
1841 | if (ret) { | |
1842 | pr_err("%s: failed to register driver\n", __func__); | |
1843 | goto fail_driver; | |
1844 | } | |
1845 | ||
1846 | ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops); | |
1847 | if (ret) | |
1848 | goto fail_bus; | |
1849 | ||
1850 | return 0; | |
1851 | ||
1852 | fail_bus: | |
1853 | platform_driver_unregister(&omap_iommu_driver); | |
1854 | fail_driver: | |
1855 | kmem_cache_destroy(iopte_cachep); | |
1856 | return ret; | |
a9dcad5e | 1857 | } |
435792d9 | 1858 | subsys_initcall(omap_iommu_init); |
0cdbf727 | 1859 | /* must be ready before omap3isp is probed */ |