Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
a9dcad5e | 19 | #include <linux/platform_device.h> |
f626b52d | 20 | #include <linux/iommu.h> |
c8d35c84 | 21 | #include <linux/omap-iommu.h> |
f626b52d OBC |
22 | #include <linux/mutex.h> |
23 | #include <linux/spinlock.h> | |
ed1c7de2 | 24 | #include <linux/io.h> |
ebf7cda0 | 25 | #include <linux/pm_runtime.h> |
3c92748d FV |
26 | #include <linux/of.h> |
27 | #include <linux/of_iommu.h> | |
28 | #include <linux/of_irq.h> | |
7d682774 | 29 | #include <linux/of_platform.h> |
a9dcad5e HD |
30 | |
31 | #include <asm/cacheflush.h> | |
32 | ||
2ab7c848 | 33 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 34 | |
2f7702af | 35 | #include "omap-iopgtable.h" |
ed1c7de2 | 36 | #include "omap-iommu.h" |
a9dcad5e | 37 | |
5acc97db SA |
38 | #define to_iommu(dev) \ |
39 | ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))) | |
40 | ||
37c2836c HD |
41 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
42 | for (__i = 0; \ | |
43 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
44 | __i++) | |
45 | ||
66bc8cf3 OBC |
46 | /* bitmap of the page sizes currently supported */ |
47 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
48 | ||
f626b52d OBC |
49 | /** |
50 | * struct omap_iommu_domain - omap iommu domain | |
51 | * @pgtable: the page table | |
52 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
53 | * iommu device can be attached for now. | |
803b5277 | 54 | * @dev: Device using this domain. |
f626b52d OBC |
55 | * @lock: domain lock, should be taken when attaching/detaching |
56 | */ | |
57 | struct omap_iommu_domain { | |
58 | u32 *pgtable; | |
6c32df43 | 59 | struct omap_iommu *iommu_dev; |
803b5277 | 60 | struct device *dev; |
f626b52d OBC |
61 | spinlock_t lock; |
62 | }; | |
63 | ||
7bd9e25f IY |
64 | #define MMU_LOCK_BASE_SHIFT 10 |
65 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
66 | #define MMU_LOCK_BASE(x) \ | |
67 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
68 | ||
69 | #define MMU_LOCK_VICT_SHIFT 4 | |
70 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
71 | #define MMU_LOCK_VICT(x) \ | |
72 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
73 | ||
74 | struct iotlb_lock { | |
75 | short base; | |
76 | short vict; | |
77 | }; | |
78 | ||
a9dcad5e HD |
79 | /* accommodate the difference between omap1 and omap2/3 */ |
80 | static const struct iommu_functions *arch_iommu; | |
81 | ||
82 | static struct platform_driver omap_iommu_driver; | |
83 | static struct kmem_cache *iopte_cachep; | |
84 | ||
85 | /** | |
6c32df43 | 86 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
87 | * @ops: a pointer to architecture specific iommu functions |
88 | * | |
89 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
90 | * omap series. This interface installs such an iommu algorighm. | |
91 | **/ | |
6c32df43 | 92 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
93 | { |
94 | if (arch_iommu) | |
95 | return -EBUSY; | |
96 | ||
97 | arch_iommu = ops; | |
98 | return 0; | |
99 | } | |
6c32df43 | 100 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
101 | |
102 | /** | |
6c32df43 | 103 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
104 | * @ops: a pointer to architecture specific iommu functions |
105 | * | |
106 | * This interface uninstalls the iommu algorighm installed previously. | |
107 | **/ | |
6c32df43 | 108 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
109 | { |
110 | if (arch_iommu != ops) | |
111 | pr_err("%s: not your arch\n", __func__); | |
112 | ||
113 | arch_iommu = NULL; | |
114 | } | |
6c32df43 | 115 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
116 | |
117 | /** | |
6c32df43 | 118 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 119 | * @dev: client device |
a9dcad5e | 120 | **/ |
fabdbca8 | 121 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 122 | { |
fabdbca8 OBC |
123 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
124 | ||
a9dcad5e HD |
125 | arch_iommu->save_ctx(obj); |
126 | } | |
6c32df43 | 127 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
128 | |
129 | /** | |
6c32df43 | 130 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 131 | * @dev: client device |
a9dcad5e | 132 | **/ |
fabdbca8 | 133 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 134 | { |
fabdbca8 OBC |
135 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
136 | ||
a9dcad5e HD |
137 | arch_iommu->restore_ctx(obj); |
138 | } | |
6c32df43 | 139 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
140 | |
141 | /** | |
6c32df43 | 142 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 143 | **/ |
6c32df43 | 144 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
145 | { |
146 | return arch_iommu->version; | |
147 | } | |
6c32df43 | 148 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 149 | |
6c32df43 | 150 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
151 | { |
152 | int err; | |
72b15b6a ORL |
153 | struct platform_device *pdev = to_platform_device(obj->dev); |
154 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
a9dcad5e | 155 | |
ef4815ab MH |
156 | if (!arch_iommu) |
157 | return -ENODEV; | |
158 | ||
90e569c4 | 159 | if (pdata && pdata->deassert_reset) { |
72b15b6a ORL |
160 | err = pdata->deassert_reset(pdev, pdata->reset_name); |
161 | if (err) { | |
162 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
163 | return err; | |
164 | } | |
165 | } | |
166 | ||
ebf7cda0 | 167 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
168 | |
169 | err = arch_iommu->enable(obj); | |
170 | ||
a9dcad5e HD |
171 | return err; |
172 | } | |
173 | ||
6c32df43 | 174 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 175 | { |
72b15b6a ORL |
176 | struct platform_device *pdev = to_platform_device(obj->dev); |
177 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
178 | ||
a9dcad5e HD |
179 | arch_iommu->disable(obj); |
180 | ||
ebf7cda0 | 181 | pm_runtime_put_sync(obj->dev); |
72b15b6a | 182 | |
90e569c4 | 183 | if (pdata && pdata->assert_reset) |
72b15b6a | 184 | pdata->assert_reset(pdev, pdata->reset_name); |
a9dcad5e HD |
185 | } |
186 | ||
187 | /* | |
188 | * TLB operations | |
189 | */ | |
6c32df43 | 190 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
191 | { |
192 | BUG_ON(!cr || !e); | |
193 | ||
194 | arch_iommu->cr_to_e(cr, e); | |
195 | } | |
6c32df43 | 196 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
197 | |
198 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
199 | { | |
200 | if (!cr) | |
201 | return -EINVAL; | |
202 | ||
203 | return arch_iommu->cr_valid(cr); | |
204 | } | |
205 | ||
6c32df43 | 206 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
207 | struct iotlb_entry *e) |
208 | { | |
209 | if (!e) | |
210 | return NULL; | |
211 | ||
212 | return arch_iommu->alloc_cr(obj, e); | |
213 | } | |
214 | ||
e1f23813 | 215 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
216 | { |
217 | return arch_iommu->cr_to_virt(cr); | |
218 | } | |
a9dcad5e HD |
219 | |
220 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
221 | { | |
222 | return arch_iommu->get_pte_attr(e); | |
223 | } | |
224 | ||
6c32df43 | 225 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
226 | { |
227 | return arch_iommu->fault_isr(obj, da); | |
228 | } | |
229 | ||
6c32df43 | 230 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
231 | { |
232 | u32 val; | |
233 | ||
234 | val = iommu_read_reg(obj, MMU_LOCK); | |
235 | ||
236 | l->base = MMU_LOCK_BASE(val); | |
237 | l->vict = MMU_LOCK_VICT(val); | |
238 | ||
a9dcad5e HD |
239 | } |
240 | ||
6c32df43 | 241 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
242 | { |
243 | u32 val; | |
244 | ||
a9dcad5e HD |
245 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
246 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
247 | ||
248 | iommu_write_reg(obj, val, MMU_LOCK); | |
249 | } | |
250 | ||
6c32df43 | 251 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
252 | { |
253 | arch_iommu->tlb_read_cr(obj, cr); | |
254 | } | |
255 | ||
6c32df43 | 256 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
257 | { |
258 | arch_iommu->tlb_load_cr(obj, cr); | |
259 | ||
260 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
261 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
262 | } | |
263 | ||
264 | /** | |
265 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
266 | * @obj: target iommu | |
267 | * @cr: contents of cam and ram register | |
268 | * @buf: output buffer | |
269 | **/ | |
6c32df43 | 270 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
271 | char *buf) |
272 | { | |
273 | BUG_ON(!cr || !buf); | |
274 | ||
275 | return arch_iommu->dump_cr(obj, cr, buf); | |
276 | } | |
277 | ||
37c2836c | 278 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 279 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
280 | { |
281 | struct cr_regs cr; | |
282 | struct iotlb_lock l; | |
283 | ||
284 | iotlb_lock_get(obj, &l); | |
285 | l.vict = n; | |
286 | iotlb_lock_set(obj, &l); | |
287 | iotlb_read_cr(obj, &cr); | |
288 | ||
289 | return cr; | |
290 | } | |
291 | ||
a9dcad5e HD |
292 | /** |
293 | * load_iotlb_entry - Set an iommu tlb entry | |
294 | * @obj: target iommu | |
295 | * @e: an iommu tlb entry info | |
296 | **/ | |
5da14a47 | 297 | #ifdef PREFETCH_IOTLB |
6c32df43 | 298 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 299 | { |
a9dcad5e HD |
300 | int err = 0; |
301 | struct iotlb_lock l; | |
302 | struct cr_regs *cr; | |
303 | ||
304 | if (!obj || !obj->nr_tlb_entries || !e) | |
305 | return -EINVAL; | |
306 | ||
ebf7cda0 | 307 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 308 | |
be6d8026 KH |
309 | iotlb_lock_get(obj, &l); |
310 | if (l.base == obj->nr_tlb_entries) { | |
311 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
312 | err = -EBUSY; |
313 | goto out; | |
314 | } | |
be6d8026 | 315 | if (!e->prsvd) { |
37c2836c HD |
316 | int i; |
317 | struct cr_regs tmp; | |
be6d8026 | 318 | |
37c2836c | 319 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
320 | if (!iotlb_cr_valid(&tmp)) |
321 | break; | |
37c2836c | 322 | |
be6d8026 KH |
323 | if (i == obj->nr_tlb_entries) { |
324 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
325 | err = -EBUSY; | |
326 | goto out; | |
327 | } | |
37c2836c HD |
328 | |
329 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
330 | } else { |
331 | l.vict = l.base; | |
332 | iotlb_lock_set(obj, &l); | |
333 | } | |
a9dcad5e HD |
334 | |
335 | cr = iotlb_alloc_cr(obj, e); | |
336 | if (IS_ERR(cr)) { | |
ebf7cda0 | 337 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
338 | return PTR_ERR(cr); |
339 | } | |
340 | ||
341 | iotlb_load_cr(obj, cr); | |
342 | kfree(cr); | |
343 | ||
be6d8026 KH |
344 | if (e->prsvd) |
345 | l.base++; | |
a9dcad5e HD |
346 | /* increment victim for next tlb load */ |
347 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 348 | l.vict = l.base; |
a9dcad5e HD |
349 | iotlb_lock_set(obj, &l); |
350 | out: | |
ebf7cda0 | 351 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
352 | return err; |
353 | } | |
a9dcad5e | 354 | |
5da14a47 OBC |
355 | #else /* !PREFETCH_IOTLB */ |
356 | ||
6c32df43 | 357 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
358 | { |
359 | return 0; | |
360 | } | |
361 | ||
362 | #endif /* !PREFETCH_IOTLB */ | |
363 | ||
6c32df43 | 364 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
365 | { |
366 | return load_iotlb_entry(obj, e); | |
367 | } | |
a9dcad5e HD |
368 | |
369 | /** | |
370 | * flush_iotlb_page - Clear an iommu tlb entry | |
371 | * @obj: target iommu | |
372 | * @da: iommu device virtual address | |
373 | * | |
374 | * Clear an iommu tlb entry which includes 'da' address. | |
375 | **/ | |
6c32df43 | 376 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 377 | { |
a9dcad5e | 378 | int i; |
37c2836c | 379 | struct cr_regs cr; |
a9dcad5e | 380 | |
ebf7cda0 | 381 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 382 | |
37c2836c | 383 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
384 | u32 start; |
385 | size_t bytes; | |
386 | ||
a9dcad5e HD |
387 | if (!iotlb_cr_valid(&cr)) |
388 | continue; | |
389 | ||
390 | start = iotlb_cr_to_virt(&cr); | |
391 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
392 | ||
393 | if ((start <= da) && (da < start + bytes)) { | |
394 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
395 | __func__, start, da, bytes); | |
0fa035e5 | 396 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 397 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 398 | break; |
a9dcad5e HD |
399 | } |
400 | } | |
ebf7cda0 | 401 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
402 | |
403 | if (i == obj->nr_tlb_entries) | |
404 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
405 | } | |
a9dcad5e HD |
406 | |
407 | /** | |
408 | * flush_iotlb_all - Clear all iommu tlb entries | |
409 | * @obj: target iommu | |
410 | **/ | |
6c32df43 | 411 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
412 | { |
413 | struct iotlb_lock l; | |
414 | ||
ebf7cda0 | 415 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
416 | |
417 | l.base = 0; | |
418 | l.vict = 0; | |
419 | iotlb_lock_set(obj, &l); | |
420 | ||
421 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
422 | ||
ebf7cda0 | 423 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 424 | } |
ddfa975a | 425 | |
e4efd94b | 426 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 427 | |
6c32df43 | 428 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 429 | { |
a9dcad5e HD |
430 | if (!obj || !buf) |
431 | return -EINVAL; | |
432 | ||
ebf7cda0 | 433 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 434 | |
14e0e679 | 435 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e | 436 | |
ebf7cda0 | 437 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
438 | |
439 | return bytes; | |
440 | } | |
6c32df43 | 441 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 442 | |
6c32df43 OBC |
443 | static int |
444 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
445 | { |
446 | int i; | |
37c2836c HD |
447 | struct iotlb_lock saved; |
448 | struct cr_regs tmp; | |
a9dcad5e HD |
449 | struct cr_regs *p = crs; |
450 | ||
ebf7cda0 | 451 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 452 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 453 | |
37c2836c | 454 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
455 | if (!iotlb_cr_valid(&tmp)) |
456 | continue; | |
a9dcad5e HD |
457 | *p++ = tmp; |
458 | } | |
37c2836c | 459 | |
a9dcad5e | 460 | iotlb_lock_set(obj, &saved); |
ebf7cda0 | 461 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
462 | |
463 | return p - crs; | |
464 | } | |
465 | ||
466 | /** | |
6c32df43 | 467 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
468 | * @obj: target iommu |
469 | * @buf: output buffer | |
470 | **/ | |
6c32df43 | 471 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 472 | { |
14e0e679 | 473 | int i, num; |
a9dcad5e HD |
474 | struct cr_regs *cr; |
475 | char *p = buf; | |
476 | ||
14e0e679 HD |
477 | num = bytes / sizeof(*cr); |
478 | num = min(obj->nr_tlb_entries, num); | |
479 | ||
480 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
481 | if (!cr) |
482 | return 0; | |
483 | ||
14e0e679 HD |
484 | num = __dump_tlb_entries(obj, cr, num); |
485 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
486 | p += iotlb_dump_cr(obj, cr + i, p); |
487 | kfree(cr); | |
488 | ||
489 | return p - buf; | |
490 | } | |
6c32df43 | 491 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 492 | |
6c32df43 | 493 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
494 | { |
495 | return driver_for_each_device(&omap_iommu_driver.driver, | |
496 | NULL, data, fn); | |
497 | } | |
6c32df43 | 498 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
499 | |
500 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
501 | ||
502 | /* | |
503 | * H/W pagetable operations | |
504 | */ | |
505 | static void flush_iopgd_range(u32 *first, u32 *last) | |
506 | { | |
507 | /* FIXME: L2 cache should be taken care of if it exists */ | |
508 | do { | |
509 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
510 | : : "r" (first)); | |
511 | first += L1_CACHE_BYTES / sizeof(*first); | |
512 | } while (first <= last); | |
513 | } | |
514 | ||
515 | static void flush_iopte_range(u32 *first, u32 *last) | |
516 | { | |
517 | /* FIXME: L2 cache should be taken care of if it exists */ | |
518 | do { | |
519 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
520 | : : "r" (first)); | |
521 | first += L1_CACHE_BYTES / sizeof(*first); | |
522 | } while (first <= last); | |
523 | } | |
524 | ||
525 | static void iopte_free(u32 *iopte) | |
526 | { | |
527 | /* Note: freed iopte's must be clean ready for re-use */ | |
e28045ab ZZ |
528 | if (iopte) |
529 | kmem_cache_free(iopte_cachep, iopte); | |
a9dcad5e HD |
530 | } |
531 | ||
6c32df43 | 532 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
533 | { |
534 | u32 *iopte; | |
535 | ||
536 | /* a table has already existed */ | |
537 | if (*iopgd) | |
538 | goto pte_ready; | |
539 | ||
540 | /* | |
541 | * do the allocation outside the page table lock | |
542 | */ | |
543 | spin_unlock(&obj->page_table_lock); | |
544 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
545 | spin_lock(&obj->page_table_lock); | |
546 | ||
547 | if (!*iopgd) { | |
548 | if (!iopte) | |
549 | return ERR_PTR(-ENOMEM); | |
550 | ||
551 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
552 | flush_iopgd_range(iopgd, iopgd); | |
553 | ||
554 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
555 | } else { | |
556 | /* We raced, free the reduniovant table */ | |
557 | iopte_free(iopte); | |
558 | } | |
559 | ||
560 | pte_ready: | |
561 | iopte = iopte_offset(iopgd, da); | |
562 | ||
563 | dev_vdbg(obj->dev, | |
564 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
565 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
566 | ||
567 | return iopte; | |
568 | } | |
569 | ||
6c32df43 | 570 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
571 | { |
572 | u32 *iopgd = iopgd_offset(obj, da); | |
573 | ||
4abb7617 HD |
574 | if ((da | pa) & ~IOSECTION_MASK) { |
575 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
576 | __func__, da, pa, IOSECTION_SIZE); | |
577 | return -EINVAL; | |
578 | } | |
579 | ||
a9dcad5e HD |
580 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
581 | flush_iopgd_range(iopgd, iopgd); | |
582 | return 0; | |
583 | } | |
584 | ||
6c32df43 | 585 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
586 | { |
587 | u32 *iopgd = iopgd_offset(obj, da); | |
588 | int i; | |
589 | ||
4abb7617 HD |
590 | if ((da | pa) & ~IOSUPER_MASK) { |
591 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
592 | __func__, da, pa, IOSUPER_SIZE); | |
593 | return -EINVAL; | |
594 | } | |
595 | ||
a9dcad5e HD |
596 | for (i = 0; i < 16; i++) |
597 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
598 | flush_iopgd_range(iopgd, iopgd + 15); | |
599 | return 0; | |
600 | } | |
601 | ||
6c32df43 | 602 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
603 | { |
604 | u32 *iopgd = iopgd_offset(obj, da); | |
605 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
606 | ||
607 | if (IS_ERR(iopte)) | |
608 | return PTR_ERR(iopte); | |
609 | ||
610 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
611 | flush_iopte_range(iopte, iopte); | |
612 | ||
613 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
614 | __func__, da, pa, iopte, *iopte); | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
6c32df43 | 619 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
620 | { |
621 | u32 *iopgd = iopgd_offset(obj, da); | |
622 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
623 | int i; | |
624 | ||
4abb7617 HD |
625 | if ((da | pa) & ~IOLARGE_MASK) { |
626 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
627 | __func__, da, pa, IOLARGE_SIZE); | |
628 | return -EINVAL; | |
629 | } | |
630 | ||
a9dcad5e HD |
631 | if (IS_ERR(iopte)) |
632 | return PTR_ERR(iopte); | |
633 | ||
634 | for (i = 0; i < 16; i++) | |
635 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
636 | flush_iopte_range(iopte, iopte + 15); | |
637 | return 0; | |
638 | } | |
639 | ||
6c32df43 OBC |
640 | static int |
641 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 642 | { |
6c32df43 | 643 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
644 | u32 prot; |
645 | int err; | |
646 | ||
647 | if (!obj || !e) | |
648 | return -EINVAL; | |
649 | ||
650 | switch (e->pgsz) { | |
651 | case MMU_CAM_PGSZ_16M: | |
652 | fn = iopgd_alloc_super; | |
653 | break; | |
654 | case MMU_CAM_PGSZ_1M: | |
655 | fn = iopgd_alloc_section; | |
656 | break; | |
657 | case MMU_CAM_PGSZ_64K: | |
658 | fn = iopte_alloc_large; | |
659 | break; | |
660 | case MMU_CAM_PGSZ_4K: | |
661 | fn = iopte_alloc_page; | |
662 | break; | |
663 | default: | |
664 | fn = NULL; | |
665 | BUG(); | |
666 | break; | |
667 | } | |
668 | ||
669 | prot = get_iopte_attr(e); | |
670 | ||
671 | spin_lock(&obj->page_table_lock); | |
672 | err = fn(obj, e->da, e->pa, prot); | |
673 | spin_unlock(&obj->page_table_lock); | |
674 | ||
675 | return err; | |
676 | } | |
677 | ||
678 | /** | |
6c32df43 | 679 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
680 | * @obj: target iommu |
681 | * @e: an iommu tlb entry info | |
682 | **/ | |
6c32df43 | 683 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
684 | { |
685 | int err; | |
686 | ||
687 | flush_iotlb_page(obj, e->da); | |
688 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 689 | if (!err) |
5da14a47 | 690 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
691 | return err; |
692 | } | |
6c32df43 | 693 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
694 | |
695 | /** | |
696 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
697 | * @obj: target iommu | |
698 | * @da: iommu device virtual address | |
699 | * @ppgd: iommu pgd entry pointer to be returned | |
700 | * @ppte: iommu pte entry pointer to be returned | |
701 | **/ | |
e1f23813 OBC |
702 | static void |
703 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
704 | { |
705 | u32 *iopgd, *iopte = NULL; | |
706 | ||
707 | iopgd = iopgd_offset(obj, da); | |
708 | if (!*iopgd) | |
709 | goto out; | |
710 | ||
a1a54456 | 711 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
712 | iopte = iopte_offset(iopgd, da); |
713 | out: | |
714 | *ppgd = iopgd; | |
715 | *ppte = iopte; | |
716 | } | |
a9dcad5e | 717 | |
6c32df43 | 718 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
719 | { |
720 | size_t bytes; | |
721 | u32 *iopgd = iopgd_offset(obj, da); | |
722 | int nent = 1; | |
723 | ||
724 | if (!*iopgd) | |
725 | return 0; | |
726 | ||
a1a54456 | 727 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
728 | int i; |
729 | u32 *iopte = iopte_offset(iopgd, da); | |
730 | ||
731 | bytes = IOPTE_SIZE; | |
732 | if (*iopte & IOPTE_LARGE) { | |
733 | nent *= 16; | |
734 | /* rewind to the 1st entry */ | |
c127c7dc | 735 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
736 | } |
737 | bytes *= nent; | |
738 | memset(iopte, 0, nent * sizeof(*iopte)); | |
739 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
740 | ||
741 | /* | |
742 | * do table walk to check if this table is necessary or not | |
743 | */ | |
744 | iopte = iopte_offset(iopgd, 0); | |
745 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
746 | if (iopte[i]) | |
747 | goto out; | |
748 | ||
749 | iopte_free(iopte); | |
750 | nent = 1; /* for the next L1 entry */ | |
751 | } else { | |
752 | bytes = IOPGD_SIZE; | |
dcc730dc | 753 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
754 | nent *= 16; |
755 | /* rewind to the 1st entry */ | |
8d33ea58 | 756 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
757 | } |
758 | bytes *= nent; | |
759 | } | |
760 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
761 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
762 | out: | |
763 | return bytes; | |
764 | } | |
765 | ||
766 | /** | |
767 | * iopgtable_clear_entry - Remove an iommu pte entry | |
768 | * @obj: target iommu | |
769 | * @da: iommu device virtual address | |
770 | **/ | |
6c32df43 | 771 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
772 | { |
773 | size_t bytes; | |
774 | ||
775 | spin_lock(&obj->page_table_lock); | |
776 | ||
777 | bytes = iopgtable_clear_entry_core(obj, da); | |
778 | flush_iotlb_page(obj, da); | |
779 | ||
780 | spin_unlock(&obj->page_table_lock); | |
781 | ||
782 | return bytes; | |
783 | } | |
a9dcad5e | 784 | |
6c32df43 | 785 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
786 | { |
787 | int i; | |
788 | ||
789 | spin_lock(&obj->page_table_lock); | |
790 | ||
791 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
792 | u32 da; | |
793 | u32 *iopgd; | |
794 | ||
795 | da = i << IOPGD_SHIFT; | |
796 | iopgd = iopgd_offset(obj, da); | |
797 | ||
798 | if (!*iopgd) | |
799 | continue; | |
800 | ||
a1a54456 | 801 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
802 | iopte_free(iopte_offset(iopgd, 0)); |
803 | ||
804 | *iopgd = 0; | |
805 | flush_iopgd_range(iopgd, iopgd); | |
806 | } | |
807 | ||
808 | flush_iotlb_all(obj); | |
809 | ||
810 | spin_unlock(&obj->page_table_lock); | |
811 | } | |
812 | ||
813 | /* | |
814 | * Device IOMMU generic operations | |
815 | */ | |
816 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
817 | { | |
d594f1f3 | 818 | u32 da, errs; |
a9dcad5e | 819 | u32 *iopgd, *iopte; |
6c32df43 | 820 | struct omap_iommu *obj = data; |
e7f10f02 | 821 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
822 | |
823 | if (!obj->refcount) | |
824 | return IRQ_NONE; | |
825 | ||
d594f1f3 | 826 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
827 | if (errs == 0) |
828 | return IRQ_HANDLED; | |
d594f1f3 DC |
829 | |
830 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 831 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
832 | return IRQ_HANDLED; |
833 | ||
37b29810 HD |
834 | iommu_disable(obj); |
835 | ||
a9dcad5e HD |
836 | iopgd = iopgd_offset(obj, da); |
837 | ||
a1a54456 | 838 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f SA |
839 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
840 | obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
841 | return IRQ_NONE; |
842 | } | |
843 | ||
844 | iopte = iopte_offset(iopgd, da); | |
845 | ||
b6c2e09f SA |
846 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
847 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); | |
a9dcad5e HD |
848 | |
849 | return IRQ_NONE; | |
850 | } | |
851 | ||
852 | static int device_match_by_alias(struct device *dev, void *data) | |
853 | { | |
6c32df43 | 854 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
855 | const char *name = data; |
856 | ||
857 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
858 | ||
859 | return strcmp(obj->name, name) == 0; | |
860 | } | |
861 | ||
862 | /** | |
f626b52d | 863 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 864 | * @name: name of target omap iommu device |
f626b52d | 865 | * @iopgd: page table |
a9dcad5e | 866 | **/ |
fabdbca8 | 867 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e | 868 | { |
7ee08b9e | 869 | int err; |
fabdbca8 OBC |
870 | struct device *dev; |
871 | struct omap_iommu *obj; | |
872 | ||
873 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
874 | (void *)name, | |
875 | device_match_by_alias); | |
876 | if (!dev) | |
7ee08b9e | 877 | return ERR_PTR(-ENODEV); |
fabdbca8 OBC |
878 | |
879 | obj = to_iommu(dev); | |
a9dcad5e | 880 | |
f626b52d | 881 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 882 | |
f626b52d OBC |
883 | /* an iommu device can only be attached once */ |
884 | if (++obj->refcount > 1) { | |
885 | dev_err(dev, "%s: already attached!\n", obj->name); | |
886 | err = -EBUSY; | |
887 | goto err_enable; | |
a9dcad5e HD |
888 | } |
889 | ||
f626b52d OBC |
890 | obj->iopgd = iopgd; |
891 | err = iommu_enable(obj); | |
892 | if (err) | |
893 | goto err_enable; | |
894 | flush_iotlb_all(obj); | |
895 | ||
f626b52d | 896 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
897 | |
898 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
899 | return obj; | |
900 | ||
a9dcad5e HD |
901 | err_enable: |
902 | obj->refcount--; | |
f626b52d | 903 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
904 | return ERR_PTR(err); |
905 | } | |
a9dcad5e HD |
906 | |
907 | /** | |
f626b52d | 908 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
909 | * @obj: target iommu |
910 | **/ | |
6c32df43 | 911 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 912 | { |
acf9d467 | 913 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
914 | return; |
915 | ||
f626b52d | 916 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
917 | |
918 | if (--obj->refcount == 0) | |
919 | iommu_disable(obj); | |
920 | ||
f626b52d | 921 | obj->iopgd = NULL; |
d594f1f3 | 922 | |
f626b52d | 923 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 924 | |
a9dcad5e | 925 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 926 | } |
d594f1f3 | 927 | |
a9dcad5e HD |
928 | /* |
929 | * OMAP Device MMU(IOMMU) detection | |
930 | */ | |
d34d6517 | 931 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
932 | { |
933 | int err = -ENODEV; | |
a9dcad5e | 934 | int irq; |
6c32df43 | 935 | struct omap_iommu *obj; |
a9dcad5e HD |
936 | struct resource *res; |
937 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
3c92748d | 938 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 939 | |
f129b3df | 940 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
941 | if (!obj) |
942 | return -ENOMEM; | |
943 | ||
3c92748d FV |
944 | if (of) { |
945 | obj->name = dev_name(&pdev->dev); | |
946 | obj->nr_tlb_entries = 32; | |
947 | err = of_property_read_u32(of, "ti,#tlb-entries", | |
948 | &obj->nr_tlb_entries); | |
949 | if (err && err != -EINVAL) | |
950 | return err; | |
951 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
952 | return -EINVAL; | |
b148d5fb SA |
953 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) |
954 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d FV |
955 | } else { |
956 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
957 | obj->name = pdata->name; | |
3c92748d | 958 | } |
3c92748d | 959 | |
a9dcad5e HD |
960 | obj->dev = &pdev->dev; |
961 | obj->ctx = (void *)obj + sizeof(*obj); | |
962 | ||
f626b52d | 963 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 964 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
965 | |
966 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
967 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
968 | if (IS_ERR(obj->regbase)) | |
969 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 970 | |
a9dcad5e | 971 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
972 | if (irq < 0) |
973 | return -ENODEV; | |
974 | ||
975 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
976 | dev_name(obj->dev), obj); | |
a9dcad5e | 977 | if (err < 0) |
f129b3df | 978 | return err; |
a9dcad5e HD |
979 | platform_set_drvdata(pdev, obj); |
980 | ||
ebf7cda0 ORL |
981 | pm_runtime_irq_safe(obj->dev); |
982 | pm_runtime_enable(obj->dev); | |
983 | ||
a9dcad5e HD |
984 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
985 | return 0; | |
a9dcad5e HD |
986 | } |
987 | ||
d34d6517 | 988 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 989 | { |
6c32df43 | 990 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 991 | |
a9dcad5e | 992 | iopgtable_clear_entry_all(obj); |
a9dcad5e | 993 | |
ebf7cda0 ORL |
994 | pm_runtime_disable(obj->dev); |
995 | ||
a9dcad5e | 996 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
997 | return 0; |
998 | } | |
999 | ||
d943b0ff | 1000 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
1001 | { .compatible = "ti,omap2-iommu" }, |
1002 | { .compatible = "ti,omap4-iommu" }, | |
1003 | { .compatible = "ti,dra7-iommu" }, | |
1004 | {}, | |
1005 | }; | |
1006 | MODULE_DEVICE_TABLE(of, omap_iommu_of_match); | |
1007 | ||
a9dcad5e HD |
1008 | static struct platform_driver omap_iommu_driver = { |
1009 | .probe = omap_iommu_probe, | |
d34d6517 | 1010 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1011 | .driver = { |
1012 | .name = "omap-iommu", | |
3c92748d | 1013 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1014 | }, |
1015 | }; | |
1016 | ||
1017 | static void iopte_cachep_ctor(void *iopte) | |
1018 | { | |
1019 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1020 | } | |
1021 | ||
286f600b | 1022 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1023 | { |
1024 | memset(e, 0, sizeof(*e)); | |
1025 | ||
1026 | e->da = da; | |
1027 | e->pa = pa; | |
d760e3e0 | 1028 | e->valid = MMU_CAM_V; |
ed1c7de2 | 1029 | /* FIXME: add OMAP1 support */ |
286f600b LP |
1030 | e->pgsz = pgsz; |
1031 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1032 | e->elsz = MMU_RAM_ELSZ_8; | |
1033 | e->mixed = 0; | |
ed1c7de2 TL |
1034 | |
1035 | return iopgsz_to_bytes(e->pgsz); | |
1036 | } | |
1037 | ||
f626b52d | 1038 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1039 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1040 | { |
1041 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1042 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1043 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1044 | struct iotlb_entry e; |
1045 | int omap_pgsz; | |
286f600b | 1046 | u32 ret; |
f626b52d | 1047 | |
f626b52d OBC |
1048 | omap_pgsz = bytes_to_iopgsz(bytes); |
1049 | if (omap_pgsz < 0) { | |
1050 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1055 | ||
286f600b | 1056 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1057 | |
6c32df43 | 1058 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1059 | if (ret) |
6c32df43 | 1060 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1061 | |
b4550d41 | 1062 | return ret; |
f626b52d OBC |
1063 | } |
1064 | ||
5009065d OBC |
1065 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1066 | size_t size) | |
f626b52d OBC |
1067 | { |
1068 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1069 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1070 | struct device *dev = oiommu->dev; |
f626b52d | 1071 | |
5009065d | 1072 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1073 | |
5009065d | 1074 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1075 | } |
1076 | ||
1077 | static int | |
1078 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1079 | { | |
1080 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1081 | struct omap_iommu *oiommu; |
fabdbca8 | 1082 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1083 | int ret = 0; |
1084 | ||
e3f595b9 SA |
1085 | if (!arch_data || !arch_data->name) { |
1086 | dev_err(dev, "device doesn't have an associated iommu\n"); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
f626b52d OBC |
1090 | spin_lock(&omap_domain->lock); |
1091 | ||
1092 | /* only a single device is supported per domain for now */ | |
1093 | if (omap_domain->iommu_dev) { | |
1094 | dev_err(dev, "iommu domain is already attached\n"); | |
1095 | ret = -EBUSY; | |
1096 | goto out; | |
1097 | } | |
1098 | ||
1099 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1100 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1101 | if (IS_ERR(oiommu)) { |
1102 | ret = PTR_ERR(oiommu); | |
1103 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1104 | goto out; | |
1105 | } | |
1106 | ||
fabdbca8 | 1107 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1108 | omap_domain->dev = dev; |
e7f10f02 | 1109 | oiommu->domain = domain; |
f626b52d OBC |
1110 | |
1111 | out: | |
1112 | spin_unlock(&omap_domain->lock); | |
1113 | return ret; | |
1114 | } | |
1115 | ||
803b5277 ORL |
1116 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1117 | struct device *dev) | |
f626b52d | 1118 | { |
fabdbca8 | 1119 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1120 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1121 | |
1122 | /* only a single device is supported per domain for now */ | |
1123 | if (omap_domain->iommu_dev != oiommu) { | |
1124 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1125 | return; |
f626b52d OBC |
1126 | } |
1127 | ||
1128 | iopgtable_clear_entry_all(oiommu); | |
1129 | ||
1130 | omap_iommu_detach(oiommu); | |
1131 | ||
fabdbca8 | 1132 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1133 | omap_domain->dev = NULL; |
1134 | } | |
f626b52d | 1135 | |
803b5277 ORL |
1136 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1137 | struct device *dev) | |
1138 | { | |
1139 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1140 | ||
1141 | spin_lock(&omap_domain->lock); | |
1142 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1143 | spin_unlock(&omap_domain->lock); |
1144 | } | |
1145 | ||
1146 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1147 | { | |
1148 | struct omap_iommu_domain *omap_domain; | |
1149 | ||
1150 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1151 | if (!omap_domain) { | |
1152 | pr_err("kzalloc failed\n"); | |
1153 | goto out; | |
1154 | } | |
1155 | ||
1156 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1157 | if (!omap_domain->pgtable) { | |
1158 | pr_err("kzalloc failed\n"); | |
1159 | goto fail_nomem; | |
1160 | } | |
1161 | ||
1162 | /* | |
1163 | * should never fail, but please keep this around to ensure | |
1164 | * we keep the hardware happy | |
1165 | */ | |
1166 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1167 | ||
1168 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1169 | spin_lock_init(&omap_domain->lock); | |
1170 | ||
1171 | domain->priv = omap_domain; | |
1172 | ||
2c6edb0c JR |
1173 | domain->geometry.aperture_start = 0; |
1174 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1175 | domain->geometry.force_aperture = true; | |
1176 | ||
f626b52d OBC |
1177 | return 0; |
1178 | ||
1179 | fail_nomem: | |
1180 | kfree(omap_domain); | |
1181 | out: | |
1182 | return -ENOMEM; | |
1183 | } | |
1184 | ||
f626b52d OBC |
1185 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1186 | { | |
1187 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1188 | ||
1189 | domain->priv = NULL; | |
1190 | ||
803b5277 ORL |
1191 | /* |
1192 | * An iommu device is still attached | |
1193 | * (currently, only one device can be attached) ? | |
1194 | */ | |
1195 | if (omap_domain->iommu_dev) | |
1196 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1197 | ||
f626b52d OBC |
1198 | kfree(omap_domain->pgtable); |
1199 | kfree(omap_domain); | |
1200 | } | |
1201 | ||
1202 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 1203 | dma_addr_t da) |
f626b52d OBC |
1204 | { |
1205 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1206 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1207 | struct device *dev = oiommu->dev; |
1208 | u32 *pgd, *pte; | |
1209 | phys_addr_t ret = 0; | |
1210 | ||
1211 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1212 | ||
1213 | if (pte) { | |
1214 | if (iopte_is_small(*pte)) | |
1215 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1216 | else if (iopte_is_large(*pte)) | |
1217 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1218 | else | |
2abfcfbc SA |
1219 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
1220 | (unsigned long long)da); | |
f626b52d OBC |
1221 | } else { |
1222 | if (iopgd_is_section(*pgd)) | |
1223 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1224 | else if (iopgd_is_super(*pgd)) | |
1225 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1226 | else | |
2abfcfbc SA |
1227 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
1228 | (unsigned long long)da); | |
f626b52d OBC |
1229 | } |
1230 | ||
1231 | return ret; | |
1232 | } | |
1233 | ||
07a02030 LP |
1234 | static int omap_iommu_add_device(struct device *dev) |
1235 | { | |
1236 | struct omap_iommu_arch_data *arch_data; | |
1237 | struct device_node *np; | |
7d682774 | 1238 | struct platform_device *pdev; |
07a02030 LP |
1239 | |
1240 | /* | |
1241 | * Allocate the archdata iommu structure for DT-based devices. | |
1242 | * | |
1243 | * TODO: Simplify this when removing non-DT support completely from the | |
1244 | * IOMMU users. | |
1245 | */ | |
1246 | if (!dev->of_node) | |
1247 | return 0; | |
1248 | ||
1249 | np = of_parse_phandle(dev->of_node, "iommus", 0); | |
1250 | if (!np) | |
1251 | return 0; | |
1252 | ||
7d682774 SA |
1253 | pdev = of_find_device_by_node(np); |
1254 | if (WARN_ON(!pdev)) { | |
1255 | of_node_put(np); | |
1256 | return -EINVAL; | |
1257 | } | |
1258 | ||
07a02030 LP |
1259 | arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); |
1260 | if (!arch_data) { | |
1261 | of_node_put(np); | |
1262 | return -ENOMEM; | |
1263 | } | |
1264 | ||
7d682774 | 1265 | arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL); |
07a02030 LP |
1266 | dev->archdata.iommu = arch_data; |
1267 | ||
1268 | of_node_put(np); | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | static void omap_iommu_remove_device(struct device *dev) | |
1274 | { | |
1275 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1276 | ||
1277 | if (!dev->of_node || !arch_data) | |
1278 | return; | |
1279 | ||
1280 | kfree(arch_data->name); | |
1281 | kfree(arch_data); | |
1282 | } | |
1283 | ||
b22f6434 | 1284 | static const struct iommu_ops omap_iommu_ops = { |
f626b52d OBC |
1285 | .domain_init = omap_iommu_domain_init, |
1286 | .domain_destroy = omap_iommu_domain_destroy, | |
1287 | .attach_dev = omap_iommu_attach_dev, | |
1288 | .detach_dev = omap_iommu_detach_dev, | |
1289 | .map = omap_iommu_map, | |
1290 | .unmap = omap_iommu_unmap, | |
1291 | .iova_to_phys = omap_iommu_iova_to_phys, | |
07a02030 LP |
1292 | .add_device = omap_iommu_add_device, |
1293 | .remove_device = omap_iommu_remove_device, | |
66bc8cf3 | 1294 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1295 | }; |
1296 | ||
a9dcad5e HD |
1297 | static int __init omap_iommu_init(void) |
1298 | { | |
1299 | struct kmem_cache *p; | |
1300 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1301 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1302 | ||
1303 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1304 | iopte_cachep_ctor); | |
1305 | if (!p) | |
1306 | return -ENOMEM; | |
1307 | iopte_cachep = p; | |
1308 | ||
a65bc64f | 1309 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1310 | |
a9dcad5e HD |
1311 | return platform_driver_register(&omap_iommu_driver); |
1312 | } | |
435792d9 OBC |
1313 | /* must be ready before omap3isp is probed */ |
1314 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1315 | |
1316 | static void __exit omap_iommu_exit(void) | |
1317 | { | |
1318 | kmem_cache_destroy(iopte_cachep); | |
1319 | ||
1320 | platform_driver_unregister(&omap_iommu_driver); | |
1321 | } | |
1322 | module_exit(omap_iommu_exit); | |
1323 | ||
1324 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1325 | MODULE_ALIAS("platform:omap-iommu"); | |
1326 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1327 | MODULE_LICENSE("GPL v2"); |