Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a9dcad5e HD |
2 | /* |
3 | * omap iommu: tlb and pagetable primitives | |
4 | * | |
c127c7dc | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
9d5018de | 6 | * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ |
a9dcad5e HD |
7 | * |
8 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
9 | * Paul Mundt and Toshihiro Kobayashi | |
a9dcad5e HD |
10 | */ |
11 | ||
bfee0cf0 | 12 | #include <linux/dma-mapping.h> |
a9dcad5e | 13 | #include <linux/err.h> |
5a0e3ad6 | 14 | #include <linux/slab.h> |
a9dcad5e HD |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioport.h> | |
a9dcad5e | 17 | #include <linux/platform_device.h> |
f626b52d | 18 | #include <linux/iommu.h> |
c8d35c84 | 19 | #include <linux/omap-iommu.h> |
f626b52d OBC |
20 | #include <linux/mutex.h> |
21 | #include <linux/spinlock.h> | |
ed1c7de2 | 22 | #include <linux/io.h> |
ebf7cda0 | 23 | #include <linux/pm_runtime.h> |
3c92748d FV |
24 | #include <linux/of.h> |
25 | #include <linux/of_iommu.h> | |
26 | #include <linux/of_irq.h> | |
7d682774 | 27 | #include <linux/of_platform.h> |
3ca9299e SA |
28 | #include <linux/regmap.h> |
29 | #include <linux/mfd/syscon.h> | |
a9dcad5e | 30 | |
2ab7c848 | 31 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 32 | |
2f7702af | 33 | #include "omap-iopgtable.h" |
ed1c7de2 | 34 | #include "omap-iommu.h" |
a9dcad5e | 35 | |
01611fe8 JR |
36 | static const struct iommu_ops omap_iommu_ops; |
37 | ||
6e8b5668 | 38 | #define to_iommu(dev) ((struct omap_iommu *)dev_get_drvdata(dev)) |
5acc97db | 39 | |
66bc8cf3 OBC |
40 | /* bitmap of the page sizes currently supported */ |
41 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
42 | ||
7bd9e25f IY |
43 | #define MMU_LOCK_BASE_SHIFT 10 |
44 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
45 | #define MMU_LOCK_BASE(x) \ | |
46 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
47 | ||
48 | #define MMU_LOCK_VICT_SHIFT 4 | |
49 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
50 | #define MMU_LOCK_VICT(x) \ | |
51 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
52 | ||
a9dcad5e HD |
53 | static struct platform_driver omap_iommu_driver; |
54 | static struct kmem_cache *iopte_cachep; | |
55 | ||
8cf851e0 JR |
56 | /** |
57 | * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain | |
58 | * @dom: generic iommu domain handle | |
59 | **/ | |
60 | static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) | |
61 | { | |
62 | return container_of(dom, struct omap_iommu_domain, domain); | |
63 | } | |
64 | ||
a9dcad5e | 65 | /** |
6c32df43 | 66 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 67 | * @dev: client device |
a9dcad5e | 68 | **/ |
fabdbca8 | 69 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 70 | { |
9d5018de SA |
71 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
72 | struct omap_iommu *obj; | |
73 | u32 *p; | |
bd4396f0 | 74 | int i; |
fabdbca8 | 75 | |
9d5018de SA |
76 | if (!arch_data) |
77 | return; | |
78 | ||
79 | while (arch_data->iommu_dev) { | |
80 | obj = arch_data->iommu_dev; | |
81 | p = obj->ctx; | |
82 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
83 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
84 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
85 | p[i]); | |
86 | } | |
87 | arch_data++; | |
bd4396f0 | 88 | } |
a9dcad5e | 89 | } |
6c32df43 | 90 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
91 | |
92 | /** | |
6c32df43 | 93 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 94 | * @dev: client device |
a9dcad5e | 95 | **/ |
fabdbca8 | 96 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 97 | { |
9d5018de SA |
98 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
99 | struct omap_iommu *obj; | |
100 | u32 *p; | |
bd4396f0 | 101 | int i; |
fabdbca8 | 102 | |
9d5018de SA |
103 | if (!arch_data) |
104 | return; | |
105 | ||
106 | while (arch_data->iommu_dev) { | |
107 | obj = arch_data->iommu_dev; | |
108 | p = obj->ctx; | |
109 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
110 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
111 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
112 | p[i]); | |
113 | } | |
114 | arch_data++; | |
bd4396f0 | 115 | } |
a9dcad5e | 116 | } |
6c32df43 | 117 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e | 118 | |
3ca9299e SA |
119 | static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable) |
120 | { | |
121 | u32 val, mask; | |
122 | ||
123 | if (!obj->syscfg) | |
124 | return; | |
125 | ||
126 | mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT)); | |
127 | val = enable ? mask : 0; | |
128 | regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); | |
129 | } | |
130 | ||
bd4396f0 SA |
131 | static void __iommu_set_twl(struct omap_iommu *obj, bool on) |
132 | { | |
133 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
134 | ||
135 | if (on) | |
136 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | |
137 | else | |
138 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | |
139 | ||
140 | l &= ~MMU_CNTL_MASK; | |
141 | if (on) | |
142 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
143 | else | |
144 | l |= (MMU_CNTL_MMU_EN); | |
145 | ||
146 | iommu_write_reg(obj, l, MMU_CNTL); | |
147 | } | |
148 | ||
149 | static int omap2_iommu_enable(struct omap_iommu *obj) | |
150 | { | |
151 | u32 l, pa; | |
152 | ||
153 | if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | |
154 | return -EINVAL; | |
155 | ||
156 | pa = virt_to_phys(obj->iopgd); | |
157 | if (!IS_ALIGNED(pa, SZ_16K)) | |
158 | return -EINVAL; | |
159 | ||
160 | l = iommu_read_reg(obj, MMU_REVISION); | |
161 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
162 | (l >> 4) & 0xf, l & 0xf); | |
163 | ||
164 | iommu_write_reg(obj, pa, MMU_TTB); | |
165 | ||
3ca9299e SA |
166 | dra7_cfg_dspsys_mmu(obj, true); |
167 | ||
bd4396f0 SA |
168 | if (obj->has_bus_err_back) |
169 | iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); | |
170 | ||
171 | __iommu_set_twl(obj, true); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static void omap2_iommu_disable(struct omap_iommu *obj) | |
177 | { | |
178 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
179 | ||
180 | l &= ~MMU_CNTL_MASK; | |
181 | iommu_write_reg(obj, l, MMU_CNTL); | |
3ca9299e | 182 | dra7_cfg_dspsys_mmu(obj, false); |
bd4396f0 SA |
183 | |
184 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
185 | } | |
186 | ||
6c32df43 | 187 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
188 | { |
189 | int err; | |
72b15b6a | 190 | struct platform_device *pdev = to_platform_device(obj->dev); |
99cb9aee | 191 | struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); |
a9dcad5e | 192 | |
90e569c4 | 193 | if (pdata && pdata->deassert_reset) { |
72b15b6a ORL |
194 | err = pdata->deassert_reset(pdev, pdata->reset_name); |
195 | if (err) { | |
196 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
197 | return err; | |
198 | } | |
199 | } | |
200 | ||
ebf7cda0 | 201 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 202 | |
bd4396f0 | 203 | err = omap2_iommu_enable(obj); |
a9dcad5e | 204 | |
a9dcad5e HD |
205 | return err; |
206 | } | |
207 | ||
6c32df43 | 208 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 209 | { |
72b15b6a | 210 | struct platform_device *pdev = to_platform_device(obj->dev); |
99cb9aee | 211 | struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev); |
72b15b6a | 212 | |
bd4396f0 | 213 | omap2_iommu_disable(obj); |
a9dcad5e | 214 | |
ebf7cda0 | 215 | pm_runtime_put_sync(obj->dev); |
72b15b6a | 216 | |
90e569c4 | 217 | if (pdata && pdata->assert_reset) |
72b15b6a | 218 | pdata->assert_reset(pdev, pdata->reset_name); |
a9dcad5e HD |
219 | } |
220 | ||
221 | /* | |
222 | * TLB operations | |
223 | */ | |
e1f23813 | 224 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e | 225 | { |
bd4396f0 SA |
226 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; |
227 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
228 | ||
229 | return cr->cam & mask; | |
a9dcad5e | 230 | } |
a9dcad5e HD |
231 | |
232 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
233 | { | |
bd4396f0 SA |
234 | u32 attr; |
235 | ||
236 | attr = e->mixed << 5; | |
237 | attr |= e->endian; | |
238 | attr |= e->elsz >> 3; | |
239 | attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || | |
240 | (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); | |
241 | return attr; | |
a9dcad5e HD |
242 | } |
243 | ||
6c32df43 | 244 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e | 245 | { |
bd4396f0 SA |
246 | u32 status, fault_addr; |
247 | ||
248 | status = iommu_read_reg(obj, MMU_IRQSTATUS); | |
249 | status &= MMU_IRQ_MASK; | |
250 | if (!status) { | |
251 | *da = 0; | |
252 | return 0; | |
253 | } | |
254 | ||
255 | fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); | |
256 | *da = fault_addr; | |
257 | ||
258 | iommu_write_reg(obj, status, MMU_IRQSTATUS); | |
259 | ||
260 | return status; | |
a9dcad5e HD |
261 | } |
262 | ||
69c2c196 | 263 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
264 | { |
265 | u32 val; | |
266 | ||
267 | val = iommu_read_reg(obj, MMU_LOCK); | |
268 | ||
269 | l->base = MMU_LOCK_BASE(val); | |
270 | l->vict = MMU_LOCK_VICT(val); | |
a9dcad5e HD |
271 | } |
272 | ||
69c2c196 | 273 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
274 | { |
275 | u32 val; | |
276 | ||
a9dcad5e HD |
277 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
278 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
279 | ||
280 | iommu_write_reg(obj, val, MMU_LOCK); | |
281 | } | |
282 | ||
6c32df43 | 283 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 284 | { |
bd4396f0 SA |
285 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); |
286 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
a9dcad5e HD |
287 | } |
288 | ||
6c32df43 | 289 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 290 | { |
bd4396f0 SA |
291 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); |
292 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
a9dcad5e HD |
293 | |
294 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
295 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
296 | } | |
297 | ||
37c2836c | 298 | /* only used in iotlb iteration for-loop */ |
69c2c196 | 299 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
300 | { |
301 | struct cr_regs cr; | |
302 | struct iotlb_lock l; | |
303 | ||
304 | iotlb_lock_get(obj, &l); | |
305 | l.vict = n; | |
306 | iotlb_lock_set(obj, &l); | |
307 | iotlb_read_cr(obj, &cr); | |
308 | ||
309 | return cr; | |
310 | } | |
311 | ||
bd4396f0 SA |
312 | #ifdef PREFETCH_IOTLB |
313 | static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, | |
314 | struct iotlb_entry *e) | |
315 | { | |
316 | struct cr_regs *cr; | |
317 | ||
318 | if (!e) | |
319 | return NULL; | |
320 | ||
321 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
322 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
323 | e->da); | |
324 | return ERR_PTR(-EINVAL); | |
325 | } | |
326 | ||
327 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
328 | if (!cr) | |
329 | return ERR_PTR(-ENOMEM); | |
330 | ||
331 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; | |
332 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; | |
333 | ||
334 | return cr; | |
335 | } | |
336 | ||
a9dcad5e HD |
337 | /** |
338 | * load_iotlb_entry - Set an iommu tlb entry | |
339 | * @obj: target iommu | |
340 | * @e: an iommu tlb entry info | |
341 | **/ | |
6c32df43 | 342 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 343 | { |
a9dcad5e HD |
344 | int err = 0; |
345 | struct iotlb_lock l; | |
346 | struct cr_regs *cr; | |
347 | ||
348 | if (!obj || !obj->nr_tlb_entries || !e) | |
349 | return -EINVAL; | |
350 | ||
ebf7cda0 | 351 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 352 | |
be6d8026 KH |
353 | iotlb_lock_get(obj, &l); |
354 | if (l.base == obj->nr_tlb_entries) { | |
355 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
356 | err = -EBUSY; |
357 | goto out; | |
358 | } | |
be6d8026 | 359 | if (!e->prsvd) { |
37c2836c HD |
360 | int i; |
361 | struct cr_regs tmp; | |
be6d8026 | 362 | |
37c2836c | 363 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
364 | if (!iotlb_cr_valid(&tmp)) |
365 | break; | |
37c2836c | 366 | |
be6d8026 KH |
367 | if (i == obj->nr_tlb_entries) { |
368 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
369 | err = -EBUSY; | |
370 | goto out; | |
371 | } | |
37c2836c HD |
372 | |
373 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
374 | } else { |
375 | l.vict = l.base; | |
376 | iotlb_lock_set(obj, &l); | |
377 | } | |
a9dcad5e HD |
378 | |
379 | cr = iotlb_alloc_cr(obj, e); | |
380 | if (IS_ERR(cr)) { | |
ebf7cda0 | 381 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
382 | return PTR_ERR(cr); |
383 | } | |
384 | ||
385 | iotlb_load_cr(obj, cr); | |
386 | kfree(cr); | |
387 | ||
be6d8026 KH |
388 | if (e->prsvd) |
389 | l.base++; | |
a9dcad5e HD |
390 | /* increment victim for next tlb load */ |
391 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 392 | l.vict = l.base; |
a9dcad5e HD |
393 | iotlb_lock_set(obj, &l); |
394 | out: | |
ebf7cda0 | 395 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
396 | return err; |
397 | } | |
a9dcad5e | 398 | |
5da14a47 OBC |
399 | #else /* !PREFETCH_IOTLB */ |
400 | ||
6c32df43 | 401 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
402 | { |
403 | return 0; | |
404 | } | |
405 | ||
406 | #endif /* !PREFETCH_IOTLB */ | |
407 | ||
6c32df43 | 408 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
409 | { |
410 | return load_iotlb_entry(obj, e); | |
411 | } | |
a9dcad5e HD |
412 | |
413 | /** | |
414 | * flush_iotlb_page - Clear an iommu tlb entry | |
415 | * @obj: target iommu | |
416 | * @da: iommu device virtual address | |
417 | * | |
418 | * Clear an iommu tlb entry which includes 'da' address. | |
419 | **/ | |
6c32df43 | 420 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 421 | { |
a9dcad5e | 422 | int i; |
37c2836c | 423 | struct cr_regs cr; |
a9dcad5e | 424 | |
ebf7cda0 | 425 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 426 | |
37c2836c | 427 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
428 | u32 start; |
429 | size_t bytes; | |
430 | ||
a9dcad5e HD |
431 | if (!iotlb_cr_valid(&cr)) |
432 | continue; | |
433 | ||
434 | start = iotlb_cr_to_virt(&cr); | |
435 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
436 | ||
437 | if ((start <= da) && (da < start + bytes)) { | |
438 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
439 | __func__, start, da, bytes); | |
0fa035e5 | 440 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 441 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 442 | break; |
a9dcad5e HD |
443 | } |
444 | } | |
ebf7cda0 | 445 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
446 | |
447 | if (i == obj->nr_tlb_entries) | |
448 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
449 | } | |
a9dcad5e HD |
450 | |
451 | /** | |
452 | * flush_iotlb_all - Clear all iommu tlb entries | |
453 | * @obj: target iommu | |
454 | **/ | |
6c32df43 | 455 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
456 | { |
457 | struct iotlb_lock l; | |
458 | ||
ebf7cda0 | 459 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
460 | |
461 | l.base = 0; | |
462 | l.vict = 0; | |
463 | iotlb_lock_set(obj, &l); | |
464 | ||
465 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
466 | ||
ebf7cda0 | 467 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 468 | } |
ddfa975a | 469 | |
a9dcad5e HD |
470 | /* |
471 | * H/W pagetable operations | |
472 | */ | |
bfee0cf0 JA |
473 | static void flush_iopte_range(struct device *dev, dma_addr_t dma, |
474 | unsigned long offset, int num_entries) | |
a9dcad5e | 475 | { |
bfee0cf0 | 476 | size_t size = num_entries * sizeof(u32); |
a9dcad5e | 477 | |
bfee0cf0 | 478 | dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE); |
a9dcad5e HD |
479 | } |
480 | ||
bfee0cf0 | 481 | static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid) |
a9dcad5e | 482 | { |
bfee0cf0 JA |
483 | dma_addr_t pt_dma; |
484 | ||
a9dcad5e | 485 | /* Note: freed iopte's must be clean ready for re-use */ |
bfee0cf0 JA |
486 | if (iopte) { |
487 | if (dma_valid) { | |
488 | pt_dma = virt_to_phys(iopte); | |
489 | dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE, | |
490 | DMA_TO_DEVICE); | |
491 | } | |
492 | ||
e28045ab | 493 | kmem_cache_free(iopte_cachep, iopte); |
bfee0cf0 | 494 | } |
a9dcad5e HD |
495 | } |
496 | ||
bfee0cf0 JA |
497 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, |
498 | dma_addr_t *pt_dma, u32 da) | |
a9dcad5e HD |
499 | { |
500 | u32 *iopte; | |
bfee0cf0 | 501 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
502 | |
503 | /* a table has already existed */ | |
504 | if (*iopgd) | |
505 | goto pte_ready; | |
506 | ||
507 | /* | |
508 | * do the allocation outside the page table lock | |
509 | */ | |
510 | spin_unlock(&obj->page_table_lock); | |
511 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
512 | spin_lock(&obj->page_table_lock); | |
513 | ||
514 | if (!*iopgd) { | |
515 | if (!iopte) | |
516 | return ERR_PTR(-ENOMEM); | |
517 | ||
bfee0cf0 JA |
518 | *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE, |
519 | DMA_TO_DEVICE); | |
520 | if (dma_mapping_error(obj->dev, *pt_dma)) { | |
521 | dev_err(obj->dev, "DMA map error for L2 table\n"); | |
522 | iopte_free(obj, iopte, false); | |
523 | return ERR_PTR(-ENOMEM); | |
524 | } | |
525 | ||
526 | /* | |
527 | * we rely on dma address and the physical address to be | |
528 | * the same for mapping the L2 table | |
529 | */ | |
530 | if (WARN_ON(*pt_dma != virt_to_phys(iopte))) { | |
531 | dev_err(obj->dev, "DMA translation error for L2 table\n"); | |
532 | dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE, | |
533 | DMA_TO_DEVICE); | |
534 | iopte_free(obj, iopte, false); | |
535 | return ERR_PTR(-ENOMEM); | |
536 | } | |
537 | ||
a9dcad5e | 538 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; |
a9dcad5e | 539 | |
bfee0cf0 | 540 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
541 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); |
542 | } else { | |
543 | /* We raced, free the reduniovant table */ | |
bfee0cf0 | 544 | iopte_free(obj, iopte, false); |
a9dcad5e HD |
545 | } |
546 | ||
547 | pte_ready: | |
548 | iopte = iopte_offset(iopgd, da); | |
04c532a1 | 549 | *pt_dma = iopgd_page_paddr(iopgd); |
a9dcad5e HD |
550 | dev_vdbg(obj->dev, |
551 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
552 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
553 | ||
554 | return iopte; | |
555 | } | |
556 | ||
6c32df43 | 557 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
558 | { |
559 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 560 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e | 561 | |
4abb7617 HD |
562 | if ((da | pa) & ~IOSECTION_MASK) { |
563 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
564 | __func__, da, pa, IOSECTION_SIZE); | |
565 | return -EINVAL; | |
566 | } | |
567 | ||
a9dcad5e | 568 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
bfee0cf0 | 569 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
570 | return 0; |
571 | } | |
572 | ||
6c32df43 | 573 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
574 | { |
575 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 576 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
577 | int i; |
578 | ||
4abb7617 HD |
579 | if ((da | pa) & ~IOSUPER_MASK) { |
580 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
581 | __func__, da, pa, IOSUPER_SIZE); | |
582 | return -EINVAL; | |
583 | } | |
584 | ||
a9dcad5e HD |
585 | for (i = 0; i < 16; i++) |
586 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
bfee0cf0 | 587 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 16); |
a9dcad5e HD |
588 | return 0; |
589 | } | |
590 | ||
6c32df43 | 591 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
592 | { |
593 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
594 | dma_addr_t pt_dma; |
595 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
596 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
597 | |
598 | if (IS_ERR(iopte)) | |
599 | return PTR_ERR(iopte); | |
600 | ||
601 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
bfee0cf0 | 602 | flush_iopte_range(obj->dev, pt_dma, offset, 1); |
a9dcad5e HD |
603 | |
604 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
605 | __func__, da, pa, iopte, *iopte); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
6c32df43 | 610 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
611 | { |
612 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
613 | dma_addr_t pt_dma; |
614 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
615 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
616 | int i; |
617 | ||
4abb7617 HD |
618 | if ((da | pa) & ~IOLARGE_MASK) { |
619 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
620 | __func__, da, pa, IOLARGE_SIZE); | |
621 | return -EINVAL; | |
622 | } | |
623 | ||
a9dcad5e HD |
624 | if (IS_ERR(iopte)) |
625 | return PTR_ERR(iopte); | |
626 | ||
627 | for (i = 0; i < 16; i++) | |
628 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
bfee0cf0 | 629 | flush_iopte_range(obj->dev, pt_dma, offset, 16); |
a9dcad5e HD |
630 | return 0; |
631 | } | |
632 | ||
6c32df43 OBC |
633 | static int |
634 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 635 | { |
6c32df43 | 636 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
637 | u32 prot; |
638 | int err; | |
639 | ||
640 | if (!obj || !e) | |
641 | return -EINVAL; | |
642 | ||
643 | switch (e->pgsz) { | |
644 | case MMU_CAM_PGSZ_16M: | |
645 | fn = iopgd_alloc_super; | |
646 | break; | |
647 | case MMU_CAM_PGSZ_1M: | |
648 | fn = iopgd_alloc_section; | |
649 | break; | |
650 | case MMU_CAM_PGSZ_64K: | |
651 | fn = iopte_alloc_large; | |
652 | break; | |
653 | case MMU_CAM_PGSZ_4K: | |
654 | fn = iopte_alloc_page; | |
655 | break; | |
656 | default: | |
657 | fn = NULL; | |
a9dcad5e HD |
658 | break; |
659 | } | |
660 | ||
7c1ab600 SA |
661 | if (WARN_ON(!fn)) |
662 | return -EINVAL; | |
663 | ||
a9dcad5e HD |
664 | prot = get_iopte_attr(e); |
665 | ||
666 | spin_lock(&obj->page_table_lock); | |
667 | err = fn(obj, e->da, e->pa, prot); | |
668 | spin_unlock(&obj->page_table_lock); | |
669 | ||
670 | return err; | |
671 | } | |
672 | ||
673 | /** | |
6c32df43 | 674 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
675 | * @obj: target iommu |
676 | * @e: an iommu tlb entry info | |
677 | **/ | |
4899a563 SA |
678 | static int |
679 | omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e HD |
680 | { |
681 | int err; | |
682 | ||
683 | flush_iotlb_page(obj, e->da); | |
684 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 685 | if (!err) |
5da14a47 | 686 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
687 | return err; |
688 | } | |
a9dcad5e HD |
689 | |
690 | /** | |
691 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
692 | * @obj: target iommu | |
693 | * @da: iommu device virtual address | |
694 | * @ppgd: iommu pgd entry pointer to be returned | |
695 | * @ppte: iommu pte entry pointer to be returned | |
696 | **/ | |
e1f23813 OBC |
697 | static void |
698 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
699 | { |
700 | u32 *iopgd, *iopte = NULL; | |
701 | ||
702 | iopgd = iopgd_offset(obj, da); | |
703 | if (!*iopgd) | |
704 | goto out; | |
705 | ||
a1a54456 | 706 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
707 | iopte = iopte_offset(iopgd, da); |
708 | out: | |
709 | *ppgd = iopgd; | |
710 | *ppte = iopte; | |
711 | } | |
a9dcad5e | 712 | |
6c32df43 | 713 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
714 | { |
715 | size_t bytes; | |
716 | u32 *iopgd = iopgd_offset(obj, da); | |
717 | int nent = 1; | |
bfee0cf0 JA |
718 | dma_addr_t pt_dma; |
719 | unsigned long pd_offset = iopgd_index(da) * sizeof(da); | |
720 | unsigned long pt_offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
721 | |
722 | if (!*iopgd) | |
723 | return 0; | |
724 | ||
a1a54456 | 725 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
726 | int i; |
727 | u32 *iopte = iopte_offset(iopgd, da); | |
728 | ||
729 | bytes = IOPTE_SIZE; | |
730 | if (*iopte & IOPTE_LARGE) { | |
731 | nent *= 16; | |
732 | /* rewind to the 1st entry */ | |
c127c7dc | 733 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
734 | } |
735 | bytes *= nent; | |
736 | memset(iopte, 0, nent * sizeof(*iopte)); | |
04c532a1 | 737 | pt_dma = iopgd_page_paddr(iopgd); |
bfee0cf0 | 738 | flush_iopte_range(obj->dev, pt_dma, pt_offset, nent); |
a9dcad5e HD |
739 | |
740 | /* | |
741 | * do table walk to check if this table is necessary or not | |
742 | */ | |
743 | iopte = iopte_offset(iopgd, 0); | |
744 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
745 | if (iopte[i]) | |
746 | goto out; | |
747 | ||
bfee0cf0 | 748 | iopte_free(obj, iopte, true); |
a9dcad5e HD |
749 | nent = 1; /* for the next L1 entry */ |
750 | } else { | |
751 | bytes = IOPGD_SIZE; | |
dcc730dc | 752 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
753 | nent *= 16; |
754 | /* rewind to the 1st entry */ | |
8d33ea58 | 755 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
756 | } |
757 | bytes *= nent; | |
758 | } | |
759 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
bfee0cf0 | 760 | flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent); |
a9dcad5e HD |
761 | out: |
762 | return bytes; | |
763 | } | |
764 | ||
765 | /** | |
766 | * iopgtable_clear_entry - Remove an iommu pte entry | |
767 | * @obj: target iommu | |
768 | * @da: iommu device virtual address | |
769 | **/ | |
6c32df43 | 770 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
771 | { |
772 | size_t bytes; | |
773 | ||
774 | spin_lock(&obj->page_table_lock); | |
775 | ||
776 | bytes = iopgtable_clear_entry_core(obj, da); | |
777 | flush_iotlb_page(obj, da); | |
778 | ||
779 | spin_unlock(&obj->page_table_lock); | |
780 | ||
781 | return bytes; | |
782 | } | |
a9dcad5e | 783 | |
6c32df43 | 784 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e | 785 | { |
bfee0cf0 | 786 | unsigned long offset; |
a9dcad5e HD |
787 | int i; |
788 | ||
789 | spin_lock(&obj->page_table_lock); | |
790 | ||
791 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
792 | u32 da; | |
793 | u32 *iopgd; | |
794 | ||
795 | da = i << IOPGD_SHIFT; | |
796 | iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 797 | offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
798 | |
799 | if (!*iopgd) | |
800 | continue; | |
801 | ||
a1a54456 | 802 | if (iopgd_is_table(*iopgd)) |
bfee0cf0 | 803 | iopte_free(obj, iopte_offset(iopgd, 0), true); |
a9dcad5e HD |
804 | |
805 | *iopgd = 0; | |
bfee0cf0 | 806 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
807 | } |
808 | ||
809 | flush_iotlb_all(obj); | |
810 | ||
811 | spin_unlock(&obj->page_table_lock); | |
812 | } | |
813 | ||
814 | /* | |
815 | * Device IOMMU generic operations | |
816 | */ | |
817 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
818 | { | |
d594f1f3 | 819 | u32 da, errs; |
a9dcad5e | 820 | u32 *iopgd, *iopte; |
6c32df43 | 821 | struct omap_iommu *obj = data; |
e7f10f02 | 822 | struct iommu_domain *domain = obj->domain; |
8cf851e0 | 823 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
a9dcad5e | 824 | |
0d364288 | 825 | if (!omap_domain->dev) |
a9dcad5e HD |
826 | return IRQ_NONE; |
827 | ||
d594f1f3 | 828 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
829 | if (errs == 0) |
830 | return IRQ_HANDLED; | |
d594f1f3 DC |
831 | |
832 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 833 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
834 | return IRQ_HANDLED; |
835 | ||
159d3e35 | 836 | iommu_write_reg(obj, 0, MMU_IRQENABLE); |
37b29810 | 837 | |
a9dcad5e HD |
838 | iopgd = iopgd_offset(obj, da); |
839 | ||
a1a54456 | 840 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f | 841 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
5835b6a6 | 842 | obj->name, errs, da, iopgd, *iopgd); |
a9dcad5e HD |
843 | return IRQ_NONE; |
844 | } | |
845 | ||
846 | iopte = iopte_offset(iopgd, da); | |
847 | ||
b6c2e09f | 848 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
5835b6a6 | 849 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); |
a9dcad5e HD |
850 | |
851 | return IRQ_NONE; | |
852 | } | |
853 | ||
a9dcad5e | 854 | /** |
f626b52d | 855 | * omap_iommu_attach() - attach iommu device to an iommu domain |
ede1c2e7 | 856 | * @obj: target omap iommu device |
f626b52d | 857 | * @iopgd: page table |
a9dcad5e | 858 | **/ |
ede1c2e7 | 859 | static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd) |
a9dcad5e | 860 | { |
7ee08b9e | 861 | int err; |
a9dcad5e | 862 | |
f626b52d | 863 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 864 | |
bfee0cf0 JA |
865 | obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE, |
866 | DMA_TO_DEVICE); | |
867 | if (dma_mapping_error(obj->dev, obj->pd_dma)) { | |
868 | dev_err(obj->dev, "DMA map error for L1 table\n"); | |
869 | err = -ENOMEM; | |
870 | goto out_err; | |
871 | } | |
872 | ||
f626b52d OBC |
873 | obj->iopgd = iopgd; |
874 | err = iommu_enable(obj); | |
875 | if (err) | |
bfee0cf0 | 876 | goto out_err; |
f626b52d OBC |
877 | flush_iotlb_all(obj); |
878 | ||
f626b52d | 879 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
880 | |
881 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
ede1c2e7 JR |
882 | |
883 | return 0; | |
a9dcad5e | 884 | |
bfee0cf0 | 885 | out_err: |
f626b52d | 886 | spin_unlock(&obj->iommu_lock); |
ede1c2e7 JR |
887 | |
888 | return err; | |
a9dcad5e | 889 | } |
a9dcad5e HD |
890 | |
891 | /** | |
f626b52d | 892 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
893 | * @obj: target iommu |
894 | **/ | |
6c32df43 | 895 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 896 | { |
acf9d467 | 897 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
898 | return; |
899 | ||
f626b52d | 900 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 901 | |
bfee0cf0 JA |
902 | dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE, |
903 | DMA_TO_DEVICE); | |
2088ecba | 904 | iommu_disable(obj); |
bfee0cf0 | 905 | obj->pd_dma = 0; |
f626b52d | 906 | obj->iopgd = NULL; |
d594f1f3 | 907 | |
f626b52d | 908 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 909 | |
a9dcad5e | 910 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 911 | } |
d594f1f3 | 912 | |
9d5018de SA |
913 | static bool omap_iommu_can_register(struct platform_device *pdev) |
914 | { | |
915 | struct device_node *np = pdev->dev.of_node; | |
916 | ||
917 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
918 | return true; | |
919 | ||
920 | /* | |
921 | * restrict IOMMU core registration only for processor-port MDMA MMUs | |
922 | * on DRA7 DSPs | |
923 | */ | |
924 | if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) || | |
925 | (!strcmp(dev_name(&pdev->dev), "41501000.mmu"))) | |
926 | return true; | |
927 | ||
928 | return false; | |
929 | } | |
930 | ||
3ca9299e SA |
931 | static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev, |
932 | struct omap_iommu *obj) | |
933 | { | |
934 | struct device_node *np = pdev->dev.of_node; | |
935 | int ret; | |
936 | ||
937 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
938 | return 0; | |
939 | ||
940 | if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) { | |
941 | dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n"); | |
942 | return -EINVAL; | |
943 | } | |
944 | ||
945 | obj->syscfg = | |
946 | syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig"); | |
947 | if (IS_ERR(obj->syscfg)) { | |
948 | /* can fail with -EPROBE_DEFER */ | |
949 | ret = PTR_ERR(obj->syscfg); | |
950 | return ret; | |
951 | } | |
952 | ||
953 | if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1, | |
954 | &obj->id)) { | |
955 | dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n"); | |
956 | return -EINVAL; | |
957 | } | |
958 | ||
959 | if (obj->id != 0 && obj->id != 1) { | |
960 | dev_err(&pdev->dev, "invalid IOMMU instance id\n"); | |
961 | return -EINVAL; | |
962 | } | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
a9dcad5e HD |
967 | /* |
968 | * OMAP Device MMU(IOMMU) detection | |
969 | */ | |
d34d6517 | 970 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
971 | { |
972 | int err = -ENODEV; | |
a9dcad5e | 973 | int irq; |
6c32df43 | 974 | struct omap_iommu *obj; |
a9dcad5e | 975 | struct resource *res; |
3c92748d | 976 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 977 | |
49a57ef7 SA |
978 | if (!of) { |
979 | pr_err("%s: only DT-based devices are supported\n", __func__); | |
980 | return -ENODEV; | |
981 | } | |
982 | ||
f129b3df | 983 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
984 | if (!obj) |
985 | return -ENOMEM; | |
986 | ||
49a57ef7 SA |
987 | obj->name = dev_name(&pdev->dev); |
988 | obj->nr_tlb_entries = 32; | |
989 | err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries); | |
990 | if (err && err != -EINVAL) | |
991 | return err; | |
992 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
993 | return -EINVAL; | |
994 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) | |
995 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d | 996 | |
a9dcad5e HD |
997 | obj->dev = &pdev->dev; |
998 | obj->ctx = (void *)obj + sizeof(*obj); | |
999 | ||
f626b52d | 1000 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 1001 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
1002 | |
1003 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
1004 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
1005 | if (IS_ERR(obj->regbase)) | |
1006 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 1007 | |
3ca9299e SA |
1008 | err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj); |
1009 | if (err) | |
1010 | return err; | |
1011 | ||
a9dcad5e | 1012 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
1013 | if (irq < 0) |
1014 | return -ENODEV; | |
1015 | ||
1016 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
1017 | dev_name(obj->dev), obj); | |
a9dcad5e | 1018 | if (err < 0) |
f129b3df | 1019 | return err; |
a9dcad5e HD |
1020 | platform_set_drvdata(pdev, obj); |
1021 | ||
9d5018de SA |
1022 | if (omap_iommu_can_register(pdev)) { |
1023 | obj->group = iommu_group_alloc(); | |
1024 | if (IS_ERR(obj->group)) | |
1025 | return PTR_ERR(obj->group); | |
28ae1e3e | 1026 | |
9d5018de SA |
1027 | err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL, |
1028 | obj->name); | |
1029 | if (err) | |
1030 | goto out_group; | |
01611fe8 | 1031 | |
9d5018de | 1032 | iommu_device_set_ops(&obj->iommu, &omap_iommu_ops); |
01611fe8 | 1033 | |
9d5018de SA |
1034 | err = iommu_device_register(&obj->iommu); |
1035 | if (err) | |
1036 | goto out_sysfs; | |
1037 | } | |
01611fe8 | 1038 | |
ebf7cda0 ORL |
1039 | pm_runtime_irq_safe(obj->dev); |
1040 | pm_runtime_enable(obj->dev); | |
1041 | ||
61c75352 SA |
1042 | omap_iommu_debugfs_add(obj); |
1043 | ||
a9dcad5e | 1044 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
28ae1e3e | 1045 | |
a9dcad5e | 1046 | return 0; |
01611fe8 JR |
1047 | |
1048 | out_sysfs: | |
1049 | iommu_device_sysfs_remove(&obj->iommu); | |
28ae1e3e JR |
1050 | out_group: |
1051 | iommu_group_put(obj->group); | |
01611fe8 | 1052 | return err; |
a9dcad5e HD |
1053 | } |
1054 | ||
d34d6517 | 1055 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 1056 | { |
6c32df43 | 1057 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 1058 | |
9d5018de SA |
1059 | if (obj->group) { |
1060 | iommu_group_put(obj->group); | |
1061 | obj->group = NULL; | |
28ae1e3e | 1062 | |
9d5018de SA |
1063 | iommu_device_sysfs_remove(&obj->iommu); |
1064 | iommu_device_unregister(&obj->iommu); | |
1065 | } | |
01611fe8 | 1066 | |
61c75352 | 1067 | omap_iommu_debugfs_remove(obj); |
a9dcad5e | 1068 | |
ebf7cda0 ORL |
1069 | pm_runtime_disable(obj->dev); |
1070 | ||
a9dcad5e | 1071 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
1072 | return 0; |
1073 | } | |
1074 | ||
d943b0ff | 1075 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
1076 | { .compatible = "ti,omap2-iommu" }, |
1077 | { .compatible = "ti,omap4-iommu" }, | |
1078 | { .compatible = "ti,dra7-iommu" }, | |
3ca9299e | 1079 | { .compatible = "ti,dra7-dsp-iommu" }, |
3c92748d FV |
1080 | {}, |
1081 | }; | |
3c92748d | 1082 | |
a9dcad5e HD |
1083 | static struct platform_driver omap_iommu_driver = { |
1084 | .probe = omap_iommu_probe, | |
d34d6517 | 1085 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1086 | .driver = { |
1087 | .name = "omap-iommu", | |
3c92748d | 1088 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1089 | }, |
1090 | }; | |
1091 | ||
286f600b | 1092 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1093 | { |
1094 | memset(e, 0, sizeof(*e)); | |
1095 | ||
1096 | e->da = da; | |
1097 | e->pa = pa; | |
d760e3e0 | 1098 | e->valid = MMU_CAM_V; |
286f600b LP |
1099 | e->pgsz = pgsz; |
1100 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1101 | e->elsz = MMU_RAM_ELSZ_8; | |
1102 | e->mixed = 0; | |
ed1c7de2 TL |
1103 | |
1104 | return iopgsz_to_bytes(e->pgsz); | |
1105 | } | |
1106 | ||
f626b52d | 1107 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5835b6a6 | 1108 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d | 1109 | { |
8cf851e0 | 1110 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1111 | struct device *dev = omap_domain->dev; |
1112 | struct omap_iommu_device *iommu; | |
1113 | struct omap_iommu *oiommu; | |
f626b52d OBC |
1114 | struct iotlb_entry e; |
1115 | int omap_pgsz; | |
9d5018de SA |
1116 | u32 ret = -EINVAL; |
1117 | int i; | |
f626b52d | 1118 | |
f626b52d OBC |
1119 | omap_pgsz = bytes_to_iopgsz(bytes); |
1120 | if (omap_pgsz < 0) { | |
1121 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | ||
1d7f449c | 1125 | dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes); |
f626b52d | 1126 | |
286f600b | 1127 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1128 | |
9d5018de SA |
1129 | iommu = omap_domain->iommus; |
1130 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1131 | oiommu = iommu->iommu_dev; | |
1132 | ret = omap_iopgtable_store_entry(oiommu, &e); | |
1133 | if (ret) { | |
1134 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", | |
1135 | ret); | |
1136 | break; | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | if (ret) { | |
1141 | while (i--) { | |
1142 | iommu--; | |
1143 | oiommu = iommu->iommu_dev; | |
1144 | iopgtable_clear_entry(oiommu, da); | |
1145 | } | |
1146 | } | |
f626b52d | 1147 | |
b4550d41 | 1148 | return ret; |
f626b52d OBC |
1149 | } |
1150 | ||
5009065d | 1151 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
5835b6a6 | 1152 | size_t size) |
f626b52d | 1153 | { |
8cf851e0 | 1154 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1155 | struct device *dev = omap_domain->dev; |
1156 | struct omap_iommu_device *iommu; | |
1157 | struct omap_iommu *oiommu; | |
1158 | bool error = false; | |
1159 | size_t bytes = 0; | |
1160 | int i; | |
f626b52d | 1161 | |
5009065d | 1162 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1163 | |
9d5018de SA |
1164 | iommu = omap_domain->iommus; |
1165 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1166 | oiommu = iommu->iommu_dev; | |
1167 | bytes = iopgtable_clear_entry(oiommu, da); | |
1168 | if (!bytes) | |
1169 | error = true; | |
1170 | } | |
1171 | ||
1172 | /* | |
1173 | * simplify return - we are only checking if any of the iommus | |
1174 | * reported an error, but not if all of them are unmapping the | |
1175 | * same number of entries. This should not occur due to the | |
1176 | * mirror programming. | |
1177 | */ | |
1178 | return error ? 0 : bytes; | |
1179 | } | |
1180 | ||
1181 | static int omap_iommu_count(struct device *dev) | |
1182 | { | |
1183 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1184 | int count = 0; | |
1185 | ||
1186 | while (arch_data->iommu_dev) { | |
1187 | count++; | |
1188 | arch_data++; | |
1189 | } | |
1190 | ||
1191 | return count; | |
1192 | } | |
1193 | ||
1194 | /* caller should call cleanup if this function fails */ | |
1195 | static int omap_iommu_attach_init(struct device *dev, | |
1196 | struct omap_iommu_domain *odomain) | |
1197 | { | |
1198 | struct omap_iommu_device *iommu; | |
1199 | int i; | |
1200 | ||
1201 | odomain->num_iommus = omap_iommu_count(dev); | |
1202 | if (!odomain->num_iommus) | |
1203 | return -EINVAL; | |
1204 | ||
1205 | odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu), | |
1206 | GFP_ATOMIC); | |
1207 | if (!odomain->iommus) | |
1208 | return -ENOMEM; | |
1209 | ||
1210 | iommu = odomain->iommus; | |
1211 | for (i = 0; i < odomain->num_iommus; i++, iommu++) { | |
1212 | iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC); | |
1213 | if (!iommu->pgtable) | |
1214 | return -ENOMEM; | |
1215 | ||
1216 | /* | |
1217 | * should never fail, but please keep this around to ensure | |
1218 | * we keep the hardware happy | |
1219 | */ | |
1220 | if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable, | |
1221 | IOPGD_TABLE_SIZE))) | |
1222 | return -EINVAL; | |
1223 | } | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain) | |
1229 | { | |
1230 | int i; | |
1231 | struct omap_iommu_device *iommu = odomain->iommus; | |
1232 | ||
1233 | for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++) | |
1234 | kfree(iommu->pgtable); | |
1235 | ||
1236 | kfree(odomain->iommus); | |
1237 | odomain->num_iommus = 0; | |
1238 | odomain->iommus = NULL; | |
f626b52d OBC |
1239 | } |
1240 | ||
1241 | static int | |
1242 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1243 | { | |
8cf851e0 | 1244 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
fabdbca8 | 1245 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
9d5018de | 1246 | struct omap_iommu_device *iommu; |
ede1c2e7 | 1247 | struct omap_iommu *oiommu; |
f626b52d | 1248 | int ret = 0; |
9d5018de | 1249 | int i; |
f626b52d | 1250 | |
ede1c2e7 | 1251 | if (!arch_data || !arch_data->iommu_dev) { |
e3f595b9 SA |
1252 | dev_err(dev, "device doesn't have an associated iommu\n"); |
1253 | return -EINVAL; | |
1254 | } | |
1255 | ||
f626b52d OBC |
1256 | spin_lock(&omap_domain->lock); |
1257 | ||
0d364288 SA |
1258 | /* only a single client device can be attached to a domain */ |
1259 | if (omap_domain->dev) { | |
f626b52d OBC |
1260 | dev_err(dev, "iommu domain is already attached\n"); |
1261 | ret = -EBUSY; | |
1262 | goto out; | |
1263 | } | |
1264 | ||
9d5018de | 1265 | ret = omap_iommu_attach_init(dev, omap_domain); |
ede1c2e7 | 1266 | if (ret) { |
9d5018de SA |
1267 | dev_err(dev, "failed to allocate required iommu data %d\n", |
1268 | ret); | |
1269 | goto init_fail; | |
1270 | } | |
1271 | ||
1272 | iommu = omap_domain->iommus; | |
1273 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) { | |
1274 | /* configure and enable the omap iommu */ | |
1275 | oiommu = arch_data->iommu_dev; | |
1276 | ret = omap_iommu_attach(oiommu, iommu->pgtable); | |
1277 | if (ret) { | |
1278 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1279 | goto attach_fail; | |
1280 | } | |
1281 | ||
1282 | oiommu->domain = domain; | |
1283 | iommu->iommu_dev = oiommu; | |
f626b52d OBC |
1284 | } |
1285 | ||
803b5277 | 1286 | omap_domain->dev = dev; |
f626b52d | 1287 | |
9d5018de SA |
1288 | goto out; |
1289 | ||
1290 | attach_fail: | |
1291 | while (i--) { | |
1292 | iommu--; | |
1293 | arch_data--; | |
1294 | oiommu = iommu->iommu_dev; | |
1295 | omap_iommu_detach(oiommu); | |
1296 | iommu->iommu_dev = NULL; | |
1297 | oiommu->domain = NULL; | |
1298 | } | |
1299 | init_fail: | |
1300 | omap_iommu_detach_fini(omap_domain); | |
f626b52d OBC |
1301 | out: |
1302 | spin_unlock(&omap_domain->lock); | |
1303 | return ret; | |
1304 | } | |
1305 | ||
803b5277 | 1306 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
5835b6a6 | 1307 | struct device *dev) |
f626b52d | 1308 | { |
9d5018de SA |
1309 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
1310 | struct omap_iommu_device *iommu = omap_domain->iommus; | |
1311 | struct omap_iommu *oiommu; | |
1312 | int i; | |
f626b52d | 1313 | |
0d364288 SA |
1314 | if (!omap_domain->dev) { |
1315 | dev_err(dev, "domain has no attached device\n"); | |
1316 | return; | |
1317 | } | |
1318 | ||
f626b52d | 1319 | /* only a single device is supported per domain for now */ |
0d364288 SA |
1320 | if (omap_domain->dev != dev) { |
1321 | dev_err(dev, "invalid attached device\n"); | |
803b5277 | 1322 | return; |
f626b52d OBC |
1323 | } |
1324 | ||
9d5018de SA |
1325 | /* |
1326 | * cleanup in the reverse order of attachment - this addresses | |
1327 | * any h/w dependencies between multiple instances, if any | |
1328 | */ | |
1329 | iommu += (omap_domain->num_iommus - 1); | |
1330 | arch_data += (omap_domain->num_iommus - 1); | |
1331 | for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) { | |
1332 | oiommu = iommu->iommu_dev; | |
1333 | iopgtable_clear_entry_all(oiommu); | |
1334 | ||
1335 | omap_iommu_detach(oiommu); | |
1336 | iommu->iommu_dev = NULL; | |
1337 | oiommu->domain = NULL; | |
1338 | } | |
f626b52d | 1339 | |
9d5018de | 1340 | omap_iommu_detach_fini(omap_domain); |
f626b52d | 1341 | |
803b5277 ORL |
1342 | omap_domain->dev = NULL; |
1343 | } | |
f626b52d | 1344 | |
803b5277 | 1345 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
5835b6a6 | 1346 | struct device *dev) |
803b5277 | 1347 | { |
8cf851e0 | 1348 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
803b5277 ORL |
1349 | |
1350 | spin_lock(&omap_domain->lock); | |
1351 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1352 | spin_unlock(&omap_domain->lock); |
1353 | } | |
1354 | ||
8cf851e0 | 1355 | static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) |
f626b52d OBC |
1356 | { |
1357 | struct omap_iommu_domain *omap_domain; | |
1358 | ||
8cf851e0 JR |
1359 | if (type != IOMMU_DOMAIN_UNMANAGED) |
1360 | return NULL; | |
1361 | ||
f626b52d | 1362 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); |
99ee98d6 | 1363 | if (!omap_domain) |
9d5018de | 1364 | return NULL; |
f626b52d | 1365 | |
f626b52d OBC |
1366 | spin_lock_init(&omap_domain->lock); |
1367 | ||
8cf851e0 JR |
1368 | omap_domain->domain.geometry.aperture_start = 0; |
1369 | omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; | |
1370 | omap_domain->domain.geometry.force_aperture = true; | |
f626b52d | 1371 | |
8cf851e0 | 1372 | return &omap_domain->domain; |
f626b52d OBC |
1373 | } |
1374 | ||
8cf851e0 | 1375 | static void omap_iommu_domain_free(struct iommu_domain *domain) |
f626b52d | 1376 | { |
8cf851e0 | 1377 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
f626b52d | 1378 | |
803b5277 ORL |
1379 | /* |
1380 | * An iommu device is still attached | |
1381 | * (currently, only one device can be attached) ? | |
1382 | */ | |
0d364288 | 1383 | if (omap_domain->dev) |
803b5277 ORL |
1384 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); |
1385 | ||
f626b52d OBC |
1386 | kfree(omap_domain); |
1387 | } | |
1388 | ||
1389 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
5835b6a6 | 1390 | dma_addr_t da) |
f626b52d | 1391 | { |
8cf851e0 | 1392 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1393 | struct omap_iommu_device *iommu = omap_domain->iommus; |
1394 | struct omap_iommu *oiommu = iommu->iommu_dev; | |
f626b52d OBC |
1395 | struct device *dev = oiommu->dev; |
1396 | u32 *pgd, *pte; | |
1397 | phys_addr_t ret = 0; | |
1398 | ||
9d5018de SA |
1399 | /* |
1400 | * all the iommus within the domain will have identical programming, | |
1401 | * so perform the lookup using just the first iommu | |
1402 | */ | |
f626b52d OBC |
1403 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); |
1404 | ||
1405 | if (pte) { | |
1406 | if (iopte_is_small(*pte)) | |
1407 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1408 | else if (iopte_is_large(*pte)) | |
1409 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1410 | else | |
2abfcfbc | 1411 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
5835b6a6 | 1412 | (unsigned long long)da); |
f626b52d OBC |
1413 | } else { |
1414 | if (iopgd_is_section(*pgd)) | |
1415 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1416 | else if (iopgd_is_super(*pgd)) | |
1417 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1418 | else | |
2abfcfbc | 1419 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
5835b6a6 | 1420 | (unsigned long long)da); |
f626b52d OBC |
1421 | } |
1422 | ||
1423 | return ret; | |
1424 | } | |
1425 | ||
07a02030 LP |
1426 | static int omap_iommu_add_device(struct device *dev) |
1427 | { | |
9d5018de | 1428 | struct omap_iommu_arch_data *arch_data, *tmp; |
ede1c2e7 | 1429 | struct omap_iommu *oiommu; |
28ae1e3e | 1430 | struct iommu_group *group; |
07a02030 | 1431 | struct device_node *np; |
7d682774 | 1432 | struct platform_device *pdev; |
9d5018de | 1433 | int num_iommus, i; |
01611fe8 | 1434 | int ret; |
07a02030 LP |
1435 | |
1436 | /* | |
1437 | * Allocate the archdata iommu structure for DT-based devices. | |
1438 | * | |
1439 | * TODO: Simplify this when removing non-DT support completely from the | |
1440 | * IOMMU users. | |
1441 | */ | |
1442 | if (!dev->of_node) | |
1443 | return 0; | |
1444 | ||
9d5018de SA |
1445 | /* |
1446 | * retrieve the count of IOMMU nodes using phandle size as element size | |
1447 | * since #iommu-cells = 0 for OMAP | |
1448 | */ | |
1449 | num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", | |
1450 | sizeof(phandle)); | |
1451 | if (num_iommus < 0) | |
07a02030 LP |
1452 | return 0; |
1453 | ||
6396bb22 | 1454 | arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); |
9d5018de SA |
1455 | if (!arch_data) |
1456 | return -ENOMEM; | |
7d682774 | 1457 | |
9d5018de SA |
1458 | for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) { |
1459 | np = of_parse_phandle(dev->of_node, "iommus", i); | |
1460 | if (!np) { | |
1461 | kfree(arch_data); | |
1462 | return -EINVAL; | |
1463 | } | |
1464 | ||
1465 | pdev = of_find_device_by_node(np); | |
1466 | if (WARN_ON(!pdev)) { | |
1467 | of_node_put(np); | |
1468 | kfree(arch_data); | |
1469 | return -EINVAL; | |
1470 | } | |
1471 | ||
1472 | oiommu = platform_get_drvdata(pdev); | |
1473 | if (!oiommu) { | |
1474 | of_node_put(np); | |
1475 | kfree(arch_data); | |
1476 | return -EINVAL; | |
1477 | } | |
1478 | ||
1479 | tmp->iommu_dev = oiommu; | |
ede1c2e7 | 1480 | |
07a02030 | 1481 | of_node_put(np); |
07a02030 LP |
1482 | } |
1483 | ||
9d5018de SA |
1484 | /* |
1485 | * use the first IOMMU alone for the sysfs device linking. | |
1486 | * TODO: Evaluate if a single iommu_group needs to be | |
1487 | * maintained for both IOMMUs | |
1488 | */ | |
1489 | oiommu = arch_data->iommu_dev; | |
01611fe8 JR |
1490 | ret = iommu_device_link(&oiommu->iommu, dev); |
1491 | if (ret) { | |
1492 | kfree(arch_data); | |
01611fe8 JR |
1493 | return ret; |
1494 | } | |
1495 | ||
07a02030 LP |
1496 | dev->archdata.iommu = arch_data; |
1497 | ||
28ae1e3e JR |
1498 | /* |
1499 | * IOMMU group initialization calls into omap_iommu_device_group, which | |
1500 | * needs a valid dev->archdata.iommu pointer | |
1501 | */ | |
1502 | group = iommu_group_get_for_dev(dev); | |
1503 | if (IS_ERR(group)) { | |
1504 | iommu_device_unlink(&oiommu->iommu, dev); | |
1505 | dev->archdata.iommu = NULL; | |
1506 | kfree(arch_data); | |
1507 | return PTR_ERR(group); | |
1508 | } | |
1509 | iommu_group_put(group); | |
1510 | ||
07a02030 LP |
1511 | return 0; |
1512 | } | |
1513 | ||
1514 | static void omap_iommu_remove_device(struct device *dev) | |
1515 | { | |
1516 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1517 | ||
1518 | if (!dev->of_node || !arch_data) | |
1519 | return; | |
1520 | ||
01611fe8 | 1521 | iommu_device_unlink(&arch_data->iommu_dev->iommu, dev); |
28ae1e3e | 1522 | iommu_group_remove_device(dev); |
01611fe8 | 1523 | |
ede1c2e7 | 1524 | dev->archdata.iommu = NULL; |
07a02030 | 1525 | kfree(arch_data); |
01611fe8 | 1526 | |
07a02030 LP |
1527 | } |
1528 | ||
28ae1e3e JR |
1529 | static struct iommu_group *omap_iommu_device_group(struct device *dev) |
1530 | { | |
1531 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
8faf5e5a | 1532 | struct iommu_group *group = ERR_PTR(-EINVAL); |
28ae1e3e JR |
1533 | |
1534 | if (arch_data->iommu_dev) | |
b6d57f1d | 1535 | group = iommu_group_ref_get(arch_data->iommu_dev->group); |
28ae1e3e JR |
1536 | |
1537 | return group; | |
1538 | } | |
1539 | ||
b22f6434 | 1540 | static const struct iommu_ops omap_iommu_ops = { |
8cf851e0 JR |
1541 | .domain_alloc = omap_iommu_domain_alloc, |
1542 | .domain_free = omap_iommu_domain_free, | |
f626b52d OBC |
1543 | .attach_dev = omap_iommu_attach_dev, |
1544 | .detach_dev = omap_iommu_detach_dev, | |
1545 | .map = omap_iommu_map, | |
1546 | .unmap = omap_iommu_unmap, | |
1547 | .iova_to_phys = omap_iommu_iova_to_phys, | |
07a02030 LP |
1548 | .add_device = omap_iommu_add_device, |
1549 | .remove_device = omap_iommu_remove_device, | |
28ae1e3e | 1550 | .device_group = omap_iommu_device_group, |
66bc8cf3 | 1551 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1552 | }; |
1553 | ||
a9dcad5e HD |
1554 | static int __init omap_iommu_init(void) |
1555 | { | |
1556 | struct kmem_cache *p; | |
1557 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1558 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
f938aab2 | 1559 | struct device_node *np; |
abaa7e5b | 1560 | int ret; |
f938aab2 TR |
1561 | |
1562 | np = of_find_matching_node(NULL, omap_iommu_of_match); | |
1563 | if (!np) | |
1564 | return 0; | |
1565 | ||
1566 | of_node_put(np); | |
a9dcad5e HD |
1567 | |
1568 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
bfee0cf0 | 1569 | NULL); |
a9dcad5e HD |
1570 | if (!p) |
1571 | return -ENOMEM; | |
1572 | iopte_cachep = p; | |
1573 | ||
61c75352 SA |
1574 | omap_iommu_debugfs_init(); |
1575 | ||
abaa7e5b SA |
1576 | ret = platform_driver_register(&omap_iommu_driver); |
1577 | if (ret) { | |
1578 | pr_err("%s: failed to register driver\n", __func__); | |
1579 | goto fail_driver; | |
1580 | } | |
1581 | ||
1582 | ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops); | |
1583 | if (ret) | |
1584 | goto fail_bus; | |
1585 | ||
1586 | return 0; | |
1587 | ||
1588 | fail_bus: | |
1589 | platform_driver_unregister(&omap_iommu_driver); | |
1590 | fail_driver: | |
1591 | kmem_cache_destroy(iopte_cachep); | |
1592 | return ret; | |
a9dcad5e | 1593 | } |
435792d9 | 1594 | subsys_initcall(omap_iommu_init); |
0cdbf727 | 1595 | /* must be ready before omap3isp is probed */ |