Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a9dcad5e HD |
2 | /* |
3 | * omap iommu: tlb and pagetable primitives | |
4 | * | |
c127c7dc | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
f512eefc | 6 | * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ |
a9dcad5e HD |
7 | * |
8 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
9 | * Paul Mundt and Toshihiro Kobayashi | |
a9dcad5e HD |
10 | */ |
11 | ||
bfee0cf0 | 12 | #include <linux/dma-mapping.h> |
a9dcad5e | 13 | #include <linux/err.h> |
5a0e3ad6 | 14 | #include <linux/slab.h> |
a9dcad5e HD |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioport.h> | |
a9dcad5e | 17 | #include <linux/platform_device.h> |
f626b52d | 18 | #include <linux/iommu.h> |
c8d35c84 | 19 | #include <linux/omap-iommu.h> |
f626b52d OBC |
20 | #include <linux/mutex.h> |
21 | #include <linux/spinlock.h> | |
ed1c7de2 | 22 | #include <linux/io.h> |
ebf7cda0 | 23 | #include <linux/pm_runtime.h> |
3c92748d | 24 | #include <linux/of.h> |
3c92748d | 25 | #include <linux/of_irq.h> |
7d682774 | 26 | #include <linux/of_platform.h> |
3ca9299e SA |
27 | #include <linux/regmap.h> |
28 | #include <linux/mfd/syscon.h> | |
a9dcad5e | 29 | |
2ab7c848 | 30 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 31 | |
2f7702af | 32 | #include "omap-iopgtable.h" |
ed1c7de2 | 33 | #include "omap-iommu.h" |
a9dcad5e | 34 | |
01611fe8 JR |
35 | static const struct iommu_ops omap_iommu_ops; |
36 | ||
6e8b5668 | 37 | #define to_iommu(dev) ((struct omap_iommu *)dev_get_drvdata(dev)) |
5acc97db | 38 | |
66bc8cf3 OBC |
39 | /* bitmap of the page sizes currently supported */ |
40 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
41 | ||
7bd9e25f IY |
42 | #define MMU_LOCK_BASE_SHIFT 10 |
43 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
44 | #define MMU_LOCK_BASE(x) \ | |
45 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
46 | ||
47 | #define MMU_LOCK_VICT_SHIFT 4 | |
48 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
49 | #define MMU_LOCK_VICT(x) \ | |
50 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
51 | ||
a9dcad5e HD |
52 | static struct platform_driver omap_iommu_driver; |
53 | static struct kmem_cache *iopte_cachep; | |
54 | ||
8cf851e0 JR |
55 | /** |
56 | * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain | |
57 | * @dom: generic iommu domain handle | |
58 | **/ | |
59 | static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) | |
60 | { | |
61 | return container_of(dom, struct omap_iommu_domain, domain); | |
62 | } | |
63 | ||
a9dcad5e | 64 | /** |
6c32df43 | 65 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 66 | * @dev: client device |
c4206c4e SA |
67 | * |
68 | * This should be treated as an deprecated API. It is preserved only | |
69 | * to maintain existing functionality for OMAP3 ISP driver. | |
a9dcad5e | 70 | **/ |
fabdbca8 | 71 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 72 | { |
97ea1202 | 73 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
9d5018de SA |
74 | struct omap_iommu *obj; |
75 | u32 *p; | |
bd4396f0 | 76 | int i; |
fabdbca8 | 77 | |
9d5018de SA |
78 | if (!arch_data) |
79 | return; | |
80 | ||
81 | while (arch_data->iommu_dev) { | |
82 | obj = arch_data->iommu_dev; | |
83 | p = obj->ctx; | |
84 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
85 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
86 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
87 | p[i]); | |
88 | } | |
89 | arch_data++; | |
bd4396f0 | 90 | } |
a9dcad5e | 91 | } |
6c32df43 | 92 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
93 | |
94 | /** | |
6c32df43 | 95 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 96 | * @dev: client device |
c4206c4e SA |
97 | * |
98 | * This should be treated as an deprecated API. It is preserved only | |
99 | * to maintain existing functionality for OMAP3 ISP driver. | |
a9dcad5e | 100 | **/ |
fabdbca8 | 101 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 102 | { |
97ea1202 | 103 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
9d5018de SA |
104 | struct omap_iommu *obj; |
105 | u32 *p; | |
bd4396f0 | 106 | int i; |
fabdbca8 | 107 | |
9d5018de SA |
108 | if (!arch_data) |
109 | return; | |
110 | ||
111 | while (arch_data->iommu_dev) { | |
112 | obj = arch_data->iommu_dev; | |
113 | p = obj->ctx; | |
114 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { | |
115 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
116 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, | |
117 | p[i]); | |
118 | } | |
119 | arch_data++; | |
bd4396f0 | 120 | } |
a9dcad5e | 121 | } |
6c32df43 | 122 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e | 123 | |
3ca9299e SA |
124 | static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable) |
125 | { | |
126 | u32 val, mask; | |
127 | ||
128 | if (!obj->syscfg) | |
129 | return; | |
130 | ||
131 | mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT)); | |
132 | val = enable ? mask : 0; | |
133 | regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); | |
134 | } | |
135 | ||
bd4396f0 SA |
136 | static void __iommu_set_twl(struct omap_iommu *obj, bool on) |
137 | { | |
138 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
139 | ||
140 | if (on) | |
141 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | |
142 | else | |
143 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | |
144 | ||
145 | l &= ~MMU_CNTL_MASK; | |
146 | if (on) | |
147 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
148 | else | |
149 | l |= (MMU_CNTL_MMU_EN); | |
150 | ||
151 | iommu_write_reg(obj, l, MMU_CNTL); | |
152 | } | |
153 | ||
154 | static int omap2_iommu_enable(struct omap_iommu *obj) | |
155 | { | |
156 | u32 l, pa; | |
157 | ||
f2ce16c3 | 158 | if (!obj->iopgd || !IS_ALIGNED((unsigned long)obj->iopgd, SZ_16K)) |
bd4396f0 SA |
159 | return -EINVAL; |
160 | ||
161 | pa = virt_to_phys(obj->iopgd); | |
162 | if (!IS_ALIGNED(pa, SZ_16K)) | |
163 | return -EINVAL; | |
164 | ||
165 | l = iommu_read_reg(obj, MMU_REVISION); | |
166 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
167 | (l >> 4) & 0xf, l & 0xf); | |
168 | ||
169 | iommu_write_reg(obj, pa, MMU_TTB); | |
170 | ||
3ca9299e SA |
171 | dra7_cfg_dspsys_mmu(obj, true); |
172 | ||
bd4396f0 SA |
173 | if (obj->has_bus_err_back) |
174 | iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); | |
175 | ||
176 | __iommu_set_twl(obj, true); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
181 | static void omap2_iommu_disable(struct omap_iommu *obj) | |
182 | { | |
183 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
184 | ||
185 | l &= ~MMU_CNTL_MASK; | |
186 | iommu_write_reg(obj, l, MMU_CNTL); | |
3ca9299e | 187 | dra7_cfg_dspsys_mmu(obj, false); |
bd4396f0 SA |
188 | |
189 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
190 | } | |
191 | ||
6c32df43 | 192 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e | 193 | { |
db8918f6 | 194 | int ret; |
a9dcad5e | 195 | |
db8918f6 SA |
196 | ret = pm_runtime_get_sync(obj->dev); |
197 | if (ret < 0) | |
198 | pm_runtime_put_noidle(obj->dev); | |
a9dcad5e | 199 | |
db8918f6 | 200 | return ret < 0 ? ret : 0; |
a9dcad5e HD |
201 | } |
202 | ||
6c32df43 | 203 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 204 | { |
ebf7cda0 | 205 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
206 | } |
207 | ||
208 | /* | |
209 | * TLB operations | |
210 | */ | |
e1f23813 | 211 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e | 212 | { |
bd4396f0 SA |
213 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; |
214 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
215 | ||
216 | return cr->cam & mask; | |
a9dcad5e | 217 | } |
a9dcad5e HD |
218 | |
219 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
220 | { | |
bd4396f0 SA |
221 | u32 attr; |
222 | ||
223 | attr = e->mixed << 5; | |
224 | attr |= e->endian; | |
225 | attr |= e->elsz >> 3; | |
226 | attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || | |
227 | (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); | |
228 | return attr; | |
a9dcad5e HD |
229 | } |
230 | ||
6c32df43 | 231 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e | 232 | { |
bd4396f0 SA |
233 | u32 status, fault_addr; |
234 | ||
235 | status = iommu_read_reg(obj, MMU_IRQSTATUS); | |
236 | status &= MMU_IRQ_MASK; | |
237 | if (!status) { | |
238 | *da = 0; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); | |
243 | *da = fault_addr; | |
244 | ||
245 | iommu_write_reg(obj, status, MMU_IRQSTATUS); | |
246 | ||
247 | return status; | |
a9dcad5e HD |
248 | } |
249 | ||
69c2c196 | 250 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
251 | { |
252 | u32 val; | |
253 | ||
254 | val = iommu_read_reg(obj, MMU_LOCK); | |
255 | ||
256 | l->base = MMU_LOCK_BASE(val); | |
257 | l->vict = MMU_LOCK_VICT(val); | |
a9dcad5e HD |
258 | } |
259 | ||
69c2c196 | 260 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
261 | { |
262 | u32 val; | |
263 | ||
a9dcad5e HD |
264 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
265 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
266 | ||
267 | iommu_write_reg(obj, val, MMU_LOCK); | |
268 | } | |
269 | ||
6c32df43 | 270 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 271 | { |
bd4396f0 SA |
272 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); |
273 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
a9dcad5e HD |
274 | } |
275 | ||
6c32df43 | 276 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 277 | { |
bd4396f0 SA |
278 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); |
279 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
a9dcad5e HD |
280 | |
281 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
282 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
283 | } | |
284 | ||
37c2836c | 285 | /* only used in iotlb iteration for-loop */ |
69c2c196 | 286 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
287 | { |
288 | struct cr_regs cr; | |
289 | struct iotlb_lock l; | |
290 | ||
291 | iotlb_lock_get(obj, &l); | |
292 | l.vict = n; | |
293 | iotlb_lock_set(obj, &l); | |
294 | iotlb_read_cr(obj, &cr); | |
295 | ||
296 | return cr; | |
297 | } | |
298 | ||
bd4396f0 SA |
299 | #ifdef PREFETCH_IOTLB |
300 | static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, | |
301 | struct iotlb_entry *e) | |
302 | { | |
303 | struct cr_regs *cr; | |
304 | ||
305 | if (!e) | |
306 | return NULL; | |
307 | ||
308 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
309 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
310 | e->da); | |
311 | return ERR_PTR(-EINVAL); | |
312 | } | |
313 | ||
314 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
315 | if (!cr) | |
316 | return ERR_PTR(-ENOMEM); | |
317 | ||
318 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; | |
319 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; | |
320 | ||
321 | return cr; | |
322 | } | |
323 | ||
a9dcad5e HD |
324 | /** |
325 | * load_iotlb_entry - Set an iommu tlb entry | |
326 | * @obj: target iommu | |
327 | * @e: an iommu tlb entry info | |
328 | **/ | |
6c32df43 | 329 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 330 | { |
a9dcad5e HD |
331 | int err = 0; |
332 | struct iotlb_lock l; | |
333 | struct cr_regs *cr; | |
334 | ||
335 | if (!obj || !obj->nr_tlb_entries || !e) | |
336 | return -EINVAL; | |
337 | ||
ebf7cda0 | 338 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 339 | |
be6d8026 KH |
340 | iotlb_lock_get(obj, &l); |
341 | if (l.base == obj->nr_tlb_entries) { | |
342 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
343 | err = -EBUSY; |
344 | goto out; | |
345 | } | |
be6d8026 | 346 | if (!e->prsvd) { |
37c2836c HD |
347 | int i; |
348 | struct cr_regs tmp; | |
be6d8026 | 349 | |
37c2836c | 350 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
351 | if (!iotlb_cr_valid(&tmp)) |
352 | break; | |
37c2836c | 353 | |
be6d8026 KH |
354 | if (i == obj->nr_tlb_entries) { |
355 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
356 | err = -EBUSY; | |
357 | goto out; | |
358 | } | |
37c2836c HD |
359 | |
360 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
361 | } else { |
362 | l.vict = l.base; | |
363 | iotlb_lock_set(obj, &l); | |
364 | } | |
a9dcad5e HD |
365 | |
366 | cr = iotlb_alloc_cr(obj, e); | |
367 | if (IS_ERR(cr)) { | |
ebf7cda0 | 368 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
369 | return PTR_ERR(cr); |
370 | } | |
371 | ||
372 | iotlb_load_cr(obj, cr); | |
373 | kfree(cr); | |
374 | ||
be6d8026 KH |
375 | if (e->prsvd) |
376 | l.base++; | |
a9dcad5e HD |
377 | /* increment victim for next tlb load */ |
378 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 379 | l.vict = l.base; |
a9dcad5e HD |
380 | iotlb_lock_set(obj, &l); |
381 | out: | |
ebf7cda0 | 382 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
383 | return err; |
384 | } | |
a9dcad5e | 385 | |
5da14a47 OBC |
386 | #else /* !PREFETCH_IOTLB */ |
387 | ||
6c32df43 | 388 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
389 | { |
390 | return 0; | |
391 | } | |
392 | ||
393 | #endif /* !PREFETCH_IOTLB */ | |
394 | ||
6c32df43 | 395 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
396 | { |
397 | return load_iotlb_entry(obj, e); | |
398 | } | |
a9dcad5e HD |
399 | |
400 | /** | |
401 | * flush_iotlb_page - Clear an iommu tlb entry | |
402 | * @obj: target iommu | |
403 | * @da: iommu device virtual address | |
404 | * | |
405 | * Clear an iommu tlb entry which includes 'da' address. | |
406 | **/ | |
6c32df43 | 407 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 408 | { |
a9dcad5e | 409 | int i; |
37c2836c | 410 | struct cr_regs cr; |
a9dcad5e | 411 | |
ebf7cda0 | 412 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 413 | |
37c2836c | 414 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
415 | u32 start; |
416 | size_t bytes; | |
417 | ||
a9dcad5e HD |
418 | if (!iotlb_cr_valid(&cr)) |
419 | continue; | |
420 | ||
421 | start = iotlb_cr_to_virt(&cr); | |
422 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
423 | ||
424 | if ((start <= da) && (da < start + bytes)) { | |
6135a891 | 425 | dev_dbg(obj->dev, "%s: %08x<=%08x(%zx)\n", |
a9dcad5e | 426 | __func__, start, da, bytes); |
0fa035e5 | 427 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 428 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 429 | break; |
a9dcad5e HD |
430 | } |
431 | } | |
ebf7cda0 | 432 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
433 | |
434 | if (i == obj->nr_tlb_entries) | |
435 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
436 | } | |
a9dcad5e HD |
437 | |
438 | /** | |
439 | * flush_iotlb_all - Clear all iommu tlb entries | |
440 | * @obj: target iommu | |
441 | **/ | |
6c32df43 | 442 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
443 | { |
444 | struct iotlb_lock l; | |
445 | ||
ebf7cda0 | 446 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
447 | |
448 | l.base = 0; | |
449 | l.vict = 0; | |
450 | iotlb_lock_set(obj, &l); | |
451 | ||
452 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
453 | ||
ebf7cda0 | 454 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 455 | } |
ddfa975a | 456 | |
a9dcad5e HD |
457 | /* |
458 | * H/W pagetable operations | |
459 | */ | |
bfee0cf0 JA |
460 | static void flush_iopte_range(struct device *dev, dma_addr_t dma, |
461 | unsigned long offset, int num_entries) | |
a9dcad5e | 462 | { |
bfee0cf0 | 463 | size_t size = num_entries * sizeof(u32); |
a9dcad5e | 464 | |
bfee0cf0 | 465 | dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE); |
a9dcad5e HD |
466 | } |
467 | ||
bfee0cf0 | 468 | static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid) |
a9dcad5e | 469 | { |
bfee0cf0 JA |
470 | dma_addr_t pt_dma; |
471 | ||
a9dcad5e | 472 | /* Note: freed iopte's must be clean ready for re-use */ |
bfee0cf0 JA |
473 | if (iopte) { |
474 | if (dma_valid) { | |
475 | pt_dma = virt_to_phys(iopte); | |
476 | dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE, | |
477 | DMA_TO_DEVICE); | |
478 | } | |
479 | ||
e28045ab | 480 | kmem_cache_free(iopte_cachep, iopte); |
bfee0cf0 | 481 | } |
a9dcad5e HD |
482 | } |
483 | ||
bfee0cf0 JA |
484 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, |
485 | dma_addr_t *pt_dma, u32 da) | |
a9dcad5e HD |
486 | { |
487 | u32 *iopte; | |
bfee0cf0 | 488 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
489 | |
490 | /* a table has already existed */ | |
491 | if (*iopgd) | |
492 | goto pte_ready; | |
493 | ||
494 | /* | |
495 | * do the allocation outside the page table lock | |
496 | */ | |
497 | spin_unlock(&obj->page_table_lock); | |
498 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
499 | spin_lock(&obj->page_table_lock); | |
500 | ||
501 | if (!*iopgd) { | |
502 | if (!iopte) | |
503 | return ERR_PTR(-ENOMEM); | |
504 | ||
bfee0cf0 JA |
505 | *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE, |
506 | DMA_TO_DEVICE); | |
507 | if (dma_mapping_error(obj->dev, *pt_dma)) { | |
508 | dev_err(obj->dev, "DMA map error for L2 table\n"); | |
509 | iopte_free(obj, iopte, false); | |
510 | return ERR_PTR(-ENOMEM); | |
511 | } | |
512 | ||
513 | /* | |
514 | * we rely on dma address and the physical address to be | |
515 | * the same for mapping the L2 table | |
516 | */ | |
517 | if (WARN_ON(*pt_dma != virt_to_phys(iopte))) { | |
518 | dev_err(obj->dev, "DMA translation error for L2 table\n"); | |
519 | dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE, | |
520 | DMA_TO_DEVICE); | |
521 | iopte_free(obj, iopte, false); | |
522 | return ERR_PTR(-ENOMEM); | |
523 | } | |
524 | ||
a9dcad5e | 525 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; |
a9dcad5e | 526 | |
bfee0cf0 | 527 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
528 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); |
529 | } else { | |
530 | /* We raced, free the reduniovant table */ | |
bfee0cf0 | 531 | iopte_free(obj, iopte, false); |
a9dcad5e HD |
532 | } |
533 | ||
534 | pte_ready: | |
535 | iopte = iopte_offset(iopgd, da); | |
04c532a1 | 536 | *pt_dma = iopgd_page_paddr(iopgd); |
a9dcad5e HD |
537 | dev_vdbg(obj->dev, |
538 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
539 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
540 | ||
541 | return iopte; | |
542 | } | |
543 | ||
6c32df43 | 544 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
545 | { |
546 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 547 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e | 548 | |
4abb7617 HD |
549 | if ((da | pa) & ~IOSECTION_MASK) { |
550 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
551 | __func__, da, pa, IOSECTION_SIZE); | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
a9dcad5e | 555 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
bfee0cf0 | 556 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
557 | return 0; |
558 | } | |
559 | ||
6c32df43 | 560 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
561 | { |
562 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 563 | unsigned long offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
564 | int i; |
565 | ||
4abb7617 HD |
566 | if ((da | pa) & ~IOSUPER_MASK) { |
567 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
568 | __func__, da, pa, IOSUPER_SIZE); | |
569 | return -EINVAL; | |
570 | } | |
571 | ||
a9dcad5e HD |
572 | for (i = 0; i < 16; i++) |
573 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
bfee0cf0 | 574 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 16); |
a9dcad5e HD |
575 | return 0; |
576 | } | |
577 | ||
6c32df43 | 578 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
579 | { |
580 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
581 | dma_addr_t pt_dma; |
582 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
583 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
584 | |
585 | if (IS_ERR(iopte)) | |
586 | return PTR_ERR(iopte); | |
587 | ||
588 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
bfee0cf0 | 589 | flush_iopte_range(obj->dev, pt_dma, offset, 1); |
a9dcad5e HD |
590 | |
591 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
592 | __func__, da, pa, iopte, *iopte); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
6c32df43 | 597 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
598 | { |
599 | u32 *iopgd = iopgd_offset(obj, da); | |
bfee0cf0 JA |
600 | dma_addr_t pt_dma; |
601 | u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da); | |
602 | unsigned long offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
603 | int i; |
604 | ||
4abb7617 HD |
605 | if ((da | pa) & ~IOLARGE_MASK) { |
606 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
607 | __func__, da, pa, IOLARGE_SIZE); | |
608 | return -EINVAL; | |
609 | } | |
610 | ||
a9dcad5e HD |
611 | if (IS_ERR(iopte)) |
612 | return PTR_ERR(iopte); | |
613 | ||
614 | for (i = 0; i < 16; i++) | |
615 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
bfee0cf0 | 616 | flush_iopte_range(obj->dev, pt_dma, offset, 16); |
a9dcad5e HD |
617 | return 0; |
618 | } | |
619 | ||
6c32df43 OBC |
620 | static int |
621 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 622 | { |
6c32df43 | 623 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
624 | u32 prot; |
625 | int err; | |
626 | ||
627 | if (!obj || !e) | |
628 | return -EINVAL; | |
629 | ||
630 | switch (e->pgsz) { | |
631 | case MMU_CAM_PGSZ_16M: | |
632 | fn = iopgd_alloc_super; | |
633 | break; | |
634 | case MMU_CAM_PGSZ_1M: | |
635 | fn = iopgd_alloc_section; | |
636 | break; | |
637 | case MMU_CAM_PGSZ_64K: | |
638 | fn = iopte_alloc_large; | |
639 | break; | |
640 | case MMU_CAM_PGSZ_4K: | |
641 | fn = iopte_alloc_page; | |
642 | break; | |
643 | default: | |
644 | fn = NULL; | |
a9dcad5e HD |
645 | break; |
646 | } | |
647 | ||
7c1ab600 SA |
648 | if (WARN_ON(!fn)) |
649 | return -EINVAL; | |
650 | ||
a9dcad5e HD |
651 | prot = get_iopte_attr(e); |
652 | ||
653 | spin_lock(&obj->page_table_lock); | |
654 | err = fn(obj, e->da, e->pa, prot); | |
655 | spin_unlock(&obj->page_table_lock); | |
656 | ||
657 | return err; | |
658 | } | |
659 | ||
660 | /** | |
6c32df43 | 661 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
662 | * @obj: target iommu |
663 | * @e: an iommu tlb entry info | |
664 | **/ | |
4899a563 SA |
665 | static int |
666 | omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e HD |
667 | { |
668 | int err; | |
669 | ||
670 | flush_iotlb_page(obj, e->da); | |
671 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 672 | if (!err) |
5da14a47 | 673 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
674 | return err; |
675 | } | |
a9dcad5e HD |
676 | |
677 | /** | |
678 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
679 | * @obj: target iommu | |
680 | * @da: iommu device virtual address | |
681 | * @ppgd: iommu pgd entry pointer to be returned | |
682 | * @ppte: iommu pte entry pointer to be returned | |
683 | **/ | |
e1f23813 OBC |
684 | static void |
685 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
686 | { |
687 | u32 *iopgd, *iopte = NULL; | |
688 | ||
689 | iopgd = iopgd_offset(obj, da); | |
690 | if (!*iopgd) | |
691 | goto out; | |
692 | ||
a1a54456 | 693 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
694 | iopte = iopte_offset(iopgd, da); |
695 | out: | |
696 | *ppgd = iopgd; | |
697 | *ppte = iopte; | |
698 | } | |
a9dcad5e | 699 | |
6c32df43 | 700 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
701 | { |
702 | size_t bytes; | |
703 | u32 *iopgd = iopgd_offset(obj, da); | |
704 | int nent = 1; | |
bfee0cf0 JA |
705 | dma_addr_t pt_dma; |
706 | unsigned long pd_offset = iopgd_index(da) * sizeof(da); | |
707 | unsigned long pt_offset = iopte_index(da) * sizeof(da); | |
a9dcad5e HD |
708 | |
709 | if (!*iopgd) | |
710 | return 0; | |
711 | ||
a1a54456 | 712 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
713 | int i; |
714 | u32 *iopte = iopte_offset(iopgd, da); | |
715 | ||
716 | bytes = IOPTE_SIZE; | |
717 | if (*iopte & IOPTE_LARGE) { | |
718 | nent *= 16; | |
719 | /* rewind to the 1st entry */ | |
c127c7dc | 720 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
721 | } |
722 | bytes *= nent; | |
723 | memset(iopte, 0, nent * sizeof(*iopte)); | |
04c532a1 | 724 | pt_dma = iopgd_page_paddr(iopgd); |
bfee0cf0 | 725 | flush_iopte_range(obj->dev, pt_dma, pt_offset, nent); |
a9dcad5e HD |
726 | |
727 | /* | |
728 | * do table walk to check if this table is necessary or not | |
729 | */ | |
730 | iopte = iopte_offset(iopgd, 0); | |
731 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
732 | if (iopte[i]) | |
733 | goto out; | |
734 | ||
bfee0cf0 | 735 | iopte_free(obj, iopte, true); |
a9dcad5e HD |
736 | nent = 1; /* for the next L1 entry */ |
737 | } else { | |
738 | bytes = IOPGD_SIZE; | |
dcc730dc | 739 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
740 | nent *= 16; |
741 | /* rewind to the 1st entry */ | |
8d33ea58 | 742 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
743 | } |
744 | bytes *= nent; | |
745 | } | |
746 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
bfee0cf0 | 747 | flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent); |
a9dcad5e HD |
748 | out: |
749 | return bytes; | |
750 | } | |
751 | ||
752 | /** | |
753 | * iopgtable_clear_entry - Remove an iommu pte entry | |
754 | * @obj: target iommu | |
755 | * @da: iommu device virtual address | |
756 | **/ | |
6c32df43 | 757 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
758 | { |
759 | size_t bytes; | |
760 | ||
761 | spin_lock(&obj->page_table_lock); | |
762 | ||
763 | bytes = iopgtable_clear_entry_core(obj, da); | |
764 | flush_iotlb_page(obj, da); | |
765 | ||
766 | spin_unlock(&obj->page_table_lock); | |
767 | ||
768 | return bytes; | |
769 | } | |
a9dcad5e | 770 | |
6c32df43 | 771 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e | 772 | { |
bfee0cf0 | 773 | unsigned long offset; |
a9dcad5e HD |
774 | int i; |
775 | ||
776 | spin_lock(&obj->page_table_lock); | |
777 | ||
778 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
779 | u32 da; | |
780 | u32 *iopgd; | |
781 | ||
782 | da = i << IOPGD_SHIFT; | |
783 | iopgd = iopgd_offset(obj, da); | |
bfee0cf0 | 784 | offset = iopgd_index(da) * sizeof(da); |
a9dcad5e HD |
785 | |
786 | if (!*iopgd) | |
787 | continue; | |
788 | ||
a1a54456 | 789 | if (iopgd_is_table(*iopgd)) |
bfee0cf0 | 790 | iopte_free(obj, iopte_offset(iopgd, 0), true); |
a9dcad5e HD |
791 | |
792 | *iopgd = 0; | |
bfee0cf0 | 793 | flush_iopte_range(obj->dev, obj->pd_dma, offset, 1); |
a9dcad5e HD |
794 | } |
795 | ||
796 | flush_iotlb_all(obj); | |
797 | ||
798 | spin_unlock(&obj->page_table_lock); | |
799 | } | |
800 | ||
801 | /* | |
802 | * Device IOMMU generic operations | |
803 | */ | |
804 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
805 | { | |
d594f1f3 | 806 | u32 da, errs; |
a9dcad5e | 807 | u32 *iopgd, *iopte; |
6c32df43 | 808 | struct omap_iommu *obj = data; |
e7f10f02 | 809 | struct iommu_domain *domain = obj->domain; |
8cf851e0 | 810 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
a9dcad5e | 811 | |
0d364288 | 812 | if (!omap_domain->dev) |
a9dcad5e HD |
813 | return IRQ_NONE; |
814 | ||
d594f1f3 | 815 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
816 | if (errs == 0) |
817 | return IRQ_HANDLED; | |
d594f1f3 DC |
818 | |
819 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 820 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
821 | return IRQ_HANDLED; |
822 | ||
159d3e35 | 823 | iommu_write_reg(obj, 0, MMU_IRQENABLE); |
37b29810 | 824 | |
a9dcad5e HD |
825 | iopgd = iopgd_offset(obj, da); |
826 | ||
a1a54456 | 827 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f | 828 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
5835b6a6 | 829 | obj->name, errs, da, iopgd, *iopgd); |
a9dcad5e HD |
830 | return IRQ_NONE; |
831 | } | |
832 | ||
833 | iopte = iopte_offset(iopgd, da); | |
834 | ||
b6c2e09f | 835 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
5835b6a6 | 836 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); |
a9dcad5e HD |
837 | |
838 | return IRQ_NONE; | |
839 | } | |
840 | ||
a9dcad5e | 841 | /** |
f626b52d | 842 | * omap_iommu_attach() - attach iommu device to an iommu domain |
ede1c2e7 | 843 | * @obj: target omap iommu device |
f626b52d | 844 | * @iopgd: page table |
a9dcad5e | 845 | **/ |
ede1c2e7 | 846 | static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd) |
a9dcad5e | 847 | { |
7ee08b9e | 848 | int err; |
a9dcad5e | 849 | |
f626b52d | 850 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 851 | |
bfee0cf0 JA |
852 | obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE, |
853 | DMA_TO_DEVICE); | |
854 | if (dma_mapping_error(obj->dev, obj->pd_dma)) { | |
855 | dev_err(obj->dev, "DMA map error for L1 table\n"); | |
856 | err = -ENOMEM; | |
857 | goto out_err; | |
858 | } | |
859 | ||
f626b52d OBC |
860 | obj->iopgd = iopgd; |
861 | err = iommu_enable(obj); | |
862 | if (err) | |
bfee0cf0 | 863 | goto out_err; |
f626b52d OBC |
864 | flush_iotlb_all(obj); |
865 | ||
f626b52d | 866 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
867 | |
868 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
ede1c2e7 JR |
869 | |
870 | return 0; | |
a9dcad5e | 871 | |
bfee0cf0 | 872 | out_err: |
f626b52d | 873 | spin_unlock(&obj->iommu_lock); |
ede1c2e7 JR |
874 | |
875 | return err; | |
a9dcad5e | 876 | } |
a9dcad5e HD |
877 | |
878 | /** | |
f626b52d | 879 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
880 | * @obj: target iommu |
881 | **/ | |
6c32df43 | 882 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 883 | { |
acf9d467 | 884 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
885 | return; |
886 | ||
f626b52d | 887 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 888 | |
bfee0cf0 JA |
889 | dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE, |
890 | DMA_TO_DEVICE); | |
bfee0cf0 | 891 | obj->pd_dma = 0; |
f626b52d | 892 | obj->iopgd = NULL; |
c3b44a06 | 893 | iommu_disable(obj); |
d594f1f3 | 894 | |
f626b52d | 895 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 896 | |
a9dcad5e | 897 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 898 | } |
d594f1f3 | 899 | |
c3b44a06 SA |
900 | static void omap_iommu_save_tlb_entries(struct omap_iommu *obj) |
901 | { | |
902 | struct iotlb_lock lock; | |
903 | struct cr_regs cr; | |
904 | struct cr_regs *tmp; | |
905 | int i; | |
906 | ||
907 | /* check if there are any locked tlbs to save */ | |
908 | iotlb_lock_get(obj, &lock); | |
909 | obj->num_cr_ctx = lock.base; | |
910 | if (!obj->num_cr_ctx) | |
911 | return; | |
912 | ||
913 | tmp = obj->cr_ctx; | |
914 | for_each_iotlb_cr(obj, obj->num_cr_ctx, i, cr) | |
915 | * tmp++ = cr; | |
916 | } | |
917 | ||
918 | static void omap_iommu_restore_tlb_entries(struct omap_iommu *obj) | |
919 | { | |
920 | struct iotlb_lock l; | |
921 | struct cr_regs *tmp; | |
922 | int i; | |
923 | ||
924 | /* no locked tlbs to restore */ | |
925 | if (!obj->num_cr_ctx) | |
926 | return; | |
927 | ||
928 | l.base = 0; | |
929 | tmp = obj->cr_ctx; | |
930 | for (i = 0; i < obj->num_cr_ctx; i++, tmp++) { | |
931 | l.vict = i; | |
932 | iotlb_lock_set(obj, &l); | |
933 | iotlb_load_cr(obj, tmp); | |
934 | } | |
935 | l.base = obj->num_cr_ctx; | |
936 | l.vict = i; | |
937 | iotlb_lock_set(obj, &l); | |
938 | } | |
939 | ||
d9c4d8a6 SA |
940 | /** |
941 | * omap_iommu_domain_deactivate - deactivate attached iommu devices | |
942 | * @domain: iommu domain attached to the target iommu device | |
943 | * | |
944 | * This API allows the client devices of IOMMU devices to suspend | |
945 | * the IOMMUs they control at runtime, after they are idled and | |
946 | * suspended all activity. System Suspend will leverage the PM | |
947 | * driver late callbacks. | |
948 | **/ | |
949 | int omap_iommu_domain_deactivate(struct iommu_domain *domain) | |
950 | { | |
951 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); | |
952 | struct omap_iommu_device *iommu; | |
953 | struct omap_iommu *oiommu; | |
954 | int i; | |
955 | ||
956 | if (!omap_domain->dev) | |
957 | return 0; | |
958 | ||
959 | iommu = omap_domain->iommus; | |
960 | iommu += (omap_domain->num_iommus - 1); | |
961 | for (i = 0; i < omap_domain->num_iommus; i++, iommu--) { | |
962 | oiommu = iommu->iommu_dev; | |
963 | pm_runtime_put_sync(oiommu->dev); | |
964 | } | |
965 | ||
966 | return 0; | |
967 | } | |
968 | EXPORT_SYMBOL_GPL(omap_iommu_domain_deactivate); | |
969 | ||
970 | /** | |
971 | * omap_iommu_domain_activate - activate attached iommu devices | |
972 | * @domain: iommu domain attached to the target iommu device | |
973 | * | |
974 | * This API allows the client devices of IOMMU devices to resume the | |
975 | * IOMMUs they control at runtime, before they can resume operations. | |
976 | * System Resume will leverage the PM driver late callbacks. | |
977 | **/ | |
978 | int omap_iommu_domain_activate(struct iommu_domain *domain) | |
979 | { | |
980 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); | |
981 | struct omap_iommu_device *iommu; | |
982 | struct omap_iommu *oiommu; | |
983 | int i; | |
984 | ||
985 | if (!omap_domain->dev) | |
986 | return 0; | |
987 | ||
988 | iommu = omap_domain->iommus; | |
989 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
990 | oiommu = iommu->iommu_dev; | |
991 | pm_runtime_get_sync(oiommu->dev); | |
992 | } | |
993 | ||
994 | return 0; | |
995 | } | |
996 | EXPORT_SYMBOL_GPL(omap_iommu_domain_activate); | |
997 | ||
db8918f6 SA |
998 | /** |
999 | * omap_iommu_runtime_suspend - disable an iommu device | |
1000 | * @dev: iommu device | |
1001 | * | |
1002 | * This function performs all that is necessary to disable an | |
1003 | * IOMMU device, either during final detachment from a client | |
1004 | * device, or during system/runtime suspend of the device. This | |
1005 | * includes programming all the appropriate IOMMU registers, and | |
1006 | * managing the associated omap_hwmod's state and the device's | |
c3b44a06 SA |
1007 | * reset line. This function also saves the context of any |
1008 | * locked TLBs if suspending. | |
db8918f6 | 1009 | **/ |
96088a20 | 1010 | static __maybe_unused int omap_iommu_runtime_suspend(struct device *dev) |
db8918f6 SA |
1011 | { |
1012 | struct platform_device *pdev = to_platform_device(dev); | |
1013 | struct iommu_platform_data *pdata = dev_get_platdata(dev); | |
1014 | struct omap_iommu *obj = to_iommu(dev); | |
1015 | int ret; | |
1016 | ||
c3b44a06 SA |
1017 | /* save the TLBs only during suspend, and not for power down */ |
1018 | if (obj->domain && obj->iopgd) | |
1019 | omap_iommu_save_tlb_entries(obj); | |
1020 | ||
db8918f6 SA |
1021 | omap2_iommu_disable(obj); |
1022 | ||
1023 | if (pdata && pdata->device_idle) | |
1024 | pdata->device_idle(pdev); | |
1025 | ||
1026 | if (pdata && pdata->assert_reset) | |
1027 | pdata->assert_reset(pdev, pdata->reset_name); | |
1028 | ||
1029 | if (pdata && pdata->set_pwrdm_constraint) { | |
1030 | ret = pdata->set_pwrdm_constraint(pdev, false, &obj->pwrst); | |
1031 | if (ret) { | |
1032 | dev_warn(obj->dev, "pwrdm_constraint failed to be reset, status = %d\n", | |
1033 | ret); | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * omap_iommu_runtime_resume - enable an iommu device | |
1042 | * @dev: iommu device | |
1043 | * | |
1044 | * This function performs all that is necessary to enable an | |
1045 | * IOMMU device, either during initial attachment to a client | |
1046 | * device, or during system/runtime resume of the device. This | |
1047 | * includes programming all the appropriate IOMMU registers, and | |
1048 | * managing the associated omap_hwmod's state and the device's | |
c3b44a06 SA |
1049 | * reset line. The function also restores any locked TLBs if |
1050 | * resuming after a suspend. | |
db8918f6 | 1051 | **/ |
96088a20 | 1052 | static __maybe_unused int omap_iommu_runtime_resume(struct device *dev) |
db8918f6 SA |
1053 | { |
1054 | struct platform_device *pdev = to_platform_device(dev); | |
1055 | struct iommu_platform_data *pdata = dev_get_platdata(dev); | |
1056 | struct omap_iommu *obj = to_iommu(dev); | |
1057 | int ret = 0; | |
1058 | ||
1059 | if (pdata && pdata->set_pwrdm_constraint) { | |
1060 | ret = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst); | |
1061 | if (ret) { | |
1062 | dev_warn(obj->dev, "pwrdm_constraint failed to be set, status = %d\n", | |
1063 | ret); | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | if (pdata && pdata->deassert_reset) { | |
1068 | ret = pdata->deassert_reset(pdev, pdata->reset_name); | |
1069 | if (ret) { | |
1070 | dev_err(dev, "deassert_reset failed: %d\n", ret); | |
1071 | return ret; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | if (pdata && pdata->device_enable) | |
1076 | pdata->device_enable(pdev); | |
1077 | ||
c3b44a06 SA |
1078 | /* restore the TLBs only during resume, and not for power up */ |
1079 | if (obj->domain) | |
1080 | omap_iommu_restore_tlb_entries(obj); | |
1081 | ||
db8918f6 SA |
1082 | ret = omap2_iommu_enable(obj); |
1083 | ||
1084 | return ret; | |
1085 | } | |
1086 | ||
c4206c4e | 1087 | /** |
30209b93 | 1088 | * omap_iommu_prepare - prepare() dev_pm_ops implementation |
c4206c4e SA |
1089 | * @dev: iommu device |
1090 | * | |
1091 | * This function performs the necessary checks to determine if the IOMMU | |
1092 | * device needs suspending or not. The function checks if the runtime_pm | |
1093 | * status of the device is suspended, and returns 1 in that case. This | |
1094 | * results in the PM core to skip invoking any of the Sleep PM callbacks | |
1095 | * (suspend, suspend_late, resume, resume_early etc). | |
1096 | */ | |
1097 | static int omap_iommu_prepare(struct device *dev) | |
1098 | { | |
1099 | if (pm_runtime_status_suspended(dev)) | |
1100 | return 1; | |
1101 | return 0; | |
1102 | } | |
1103 | ||
9d5018de SA |
1104 | static bool omap_iommu_can_register(struct platform_device *pdev) |
1105 | { | |
1106 | struct device_node *np = pdev->dev.of_node; | |
1107 | ||
1108 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
1109 | return true; | |
1110 | ||
1111 | /* | |
1112 | * restrict IOMMU core registration only for processor-port MDMA MMUs | |
1113 | * on DRA7 DSPs | |
1114 | */ | |
1115 | if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) || | |
1116 | (!strcmp(dev_name(&pdev->dev), "41501000.mmu"))) | |
1117 | return true; | |
1118 | ||
1119 | return false; | |
1120 | } | |
1121 | ||
3ca9299e SA |
1122 | static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev, |
1123 | struct omap_iommu *obj) | |
1124 | { | |
1125 | struct device_node *np = pdev->dev.of_node; | |
1126 | int ret; | |
1127 | ||
1128 | if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) | |
1129 | return 0; | |
1130 | ||
1131 | if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) { | |
1132 | dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n"); | |
1133 | return -EINVAL; | |
1134 | } | |
1135 | ||
1136 | obj->syscfg = | |
1137 | syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig"); | |
1138 | if (IS_ERR(obj->syscfg)) { | |
1139 | /* can fail with -EPROBE_DEFER */ | |
1140 | ret = PTR_ERR(obj->syscfg); | |
1141 | return ret; | |
1142 | } | |
1143 | ||
1144 | if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1, | |
1145 | &obj->id)) { | |
1146 | dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n"); | |
1147 | return -EINVAL; | |
1148 | } | |
1149 | ||
1150 | if (obj->id != 0 && obj->id != 1) { | |
1151 | dev_err(&pdev->dev, "invalid IOMMU instance id\n"); | |
1152 | return -EINVAL; | |
1153 | } | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
a9dcad5e HD |
1158 | /* |
1159 | * OMAP Device MMU(IOMMU) detection | |
1160 | */ | |
d34d6517 | 1161 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
1162 | { |
1163 | int err = -ENODEV; | |
a9dcad5e | 1164 | int irq; |
6c32df43 | 1165 | struct omap_iommu *obj; |
a9dcad5e | 1166 | struct resource *res; |
3c92748d | 1167 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 1168 | |
49a57ef7 SA |
1169 | if (!of) { |
1170 | pr_err("%s: only DT-based devices are supported\n", __func__); | |
1171 | return -ENODEV; | |
1172 | } | |
1173 | ||
f129b3df | 1174 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
1175 | if (!obj) |
1176 | return -ENOMEM; | |
1177 | ||
db8918f6 SA |
1178 | /* |
1179 | * self-manage the ordering dependencies between omap_device_enable/idle | |
1180 | * and omap_device_assert/deassert_hardreset API | |
1181 | */ | |
1182 | if (pdev->dev.pm_domain) { | |
1183 | dev_dbg(&pdev->dev, "device pm_domain is being reset\n"); | |
1184 | pdev->dev.pm_domain = NULL; | |
1185 | } | |
1186 | ||
49a57ef7 SA |
1187 | obj->name = dev_name(&pdev->dev); |
1188 | obj->nr_tlb_entries = 32; | |
1189 | err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries); | |
1190 | if (err && err != -EINVAL) | |
1191 | return err; | |
1192 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
1193 | return -EINVAL; | |
0c043164 | 1194 | if (of_property_read_bool(of, "ti,iommu-bus-err-back")) |
49a57ef7 | 1195 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; |
3c92748d | 1196 | |
a9dcad5e HD |
1197 | obj->dev = &pdev->dev; |
1198 | obj->ctx = (void *)obj + sizeof(*obj); | |
c3b44a06 SA |
1199 | obj->cr_ctx = devm_kzalloc(&pdev->dev, |
1200 | sizeof(*obj->cr_ctx) * obj->nr_tlb_entries, | |
1201 | GFP_KERNEL); | |
1202 | if (!obj->cr_ctx) | |
1203 | return -ENOMEM; | |
a9dcad5e | 1204 | |
f626b52d | 1205 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 1206 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
1207 | |
1208 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
1209 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
1210 | if (IS_ERR(obj->regbase)) | |
1211 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 1212 | |
3ca9299e SA |
1213 | err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj); |
1214 | if (err) | |
1215 | return err; | |
1216 | ||
a9dcad5e | 1217 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
1218 | if (irq < 0) |
1219 | return -ENODEV; | |
1220 | ||
1221 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
1222 | dev_name(obj->dev), obj); | |
a9dcad5e | 1223 | if (err < 0) |
f129b3df | 1224 | return err; |
a9dcad5e HD |
1225 | platform_set_drvdata(pdev, obj); |
1226 | ||
9d5018de SA |
1227 | if (omap_iommu_can_register(pdev)) { |
1228 | obj->group = iommu_group_alloc(); | |
1229 | if (IS_ERR(obj->group)) | |
1230 | return PTR_ERR(obj->group); | |
28ae1e3e | 1231 | |
9d5018de SA |
1232 | err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL, |
1233 | obj->name); | |
1234 | if (err) | |
1235 | goto out_group; | |
01611fe8 | 1236 | |
2d471b20 | 1237 | err = iommu_device_register(&obj->iommu, &omap_iommu_ops, &pdev->dev); |
9d5018de SA |
1238 | if (err) |
1239 | goto out_sysfs; | |
1240 | } | |
01611fe8 | 1241 | |
ebf7cda0 ORL |
1242 | pm_runtime_enable(obj->dev); |
1243 | ||
61c75352 SA |
1244 | omap_iommu_debugfs_add(obj); |
1245 | ||
a9dcad5e | 1246 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
28ae1e3e | 1247 | |
c822b37c JR |
1248 | /* Re-probe bus to probe device attached to this IOMMU */ |
1249 | bus_iommu_probe(&platform_bus_type); | |
604629bc | 1250 | |
a9dcad5e | 1251 | return 0; |
01611fe8 JR |
1252 | |
1253 | out_sysfs: | |
1254 | iommu_device_sysfs_remove(&obj->iommu); | |
28ae1e3e JR |
1255 | out_group: |
1256 | iommu_group_put(obj->group); | |
01611fe8 | 1257 | return err; |
a9dcad5e HD |
1258 | } |
1259 | ||
5930df68 | 1260 | static void omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 1261 | { |
6c32df43 | 1262 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 1263 | |
9d5018de SA |
1264 | if (obj->group) { |
1265 | iommu_group_put(obj->group); | |
1266 | obj->group = NULL; | |
28ae1e3e | 1267 | |
9d5018de SA |
1268 | iommu_device_sysfs_remove(&obj->iommu); |
1269 | iommu_device_unregister(&obj->iommu); | |
1270 | } | |
01611fe8 | 1271 | |
61c75352 | 1272 | omap_iommu_debugfs_remove(obj); |
a9dcad5e | 1273 | |
ebf7cda0 ORL |
1274 | pm_runtime_disable(obj->dev); |
1275 | ||
a9dcad5e | 1276 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
1277 | } |
1278 | ||
db8918f6 | 1279 | static const struct dev_pm_ops omap_iommu_pm_ops = { |
c4206c4e SA |
1280 | .prepare = omap_iommu_prepare, |
1281 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1282 | pm_runtime_force_resume) | |
db8918f6 SA |
1283 | SET_RUNTIME_PM_OPS(omap_iommu_runtime_suspend, |
1284 | omap_iommu_runtime_resume, NULL) | |
1285 | }; | |
1286 | ||
d943b0ff | 1287 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
1288 | { .compatible = "ti,omap2-iommu" }, |
1289 | { .compatible = "ti,omap4-iommu" }, | |
1290 | { .compatible = "ti,dra7-iommu" }, | |
3ca9299e | 1291 | { .compatible = "ti,dra7-dsp-iommu" }, |
3c92748d FV |
1292 | {}, |
1293 | }; | |
3c92748d | 1294 | |
a9dcad5e HD |
1295 | static struct platform_driver omap_iommu_driver = { |
1296 | .probe = omap_iommu_probe, | |
5930df68 | 1297 | .remove_new = omap_iommu_remove, |
a9dcad5e HD |
1298 | .driver = { |
1299 | .name = "omap-iommu", | |
db8918f6 | 1300 | .pm = &omap_iommu_pm_ops, |
3c92748d | 1301 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1302 | }, |
1303 | }; | |
1304 | ||
286f600b | 1305 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1306 | { |
1307 | memset(e, 0, sizeof(*e)); | |
1308 | ||
1309 | e->da = da; | |
1310 | e->pa = pa; | |
d760e3e0 | 1311 | e->valid = MMU_CAM_V; |
286f600b LP |
1312 | e->pgsz = pgsz; |
1313 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1314 | e->elsz = MMU_RAM_ELSZ_8; | |
1315 | e->mixed = 0; | |
ed1c7de2 TL |
1316 | |
1317 | return iopgsz_to_bytes(e->pgsz); | |
1318 | } | |
1319 | ||
f626b52d | 1320 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
781ca2de | 1321 | phys_addr_t pa, size_t bytes, int prot, gfp_t gfp) |
f626b52d | 1322 | { |
8cf851e0 | 1323 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1324 | struct device *dev = omap_domain->dev; |
1325 | struct omap_iommu_device *iommu; | |
1326 | struct omap_iommu *oiommu; | |
f626b52d OBC |
1327 | struct iotlb_entry e; |
1328 | int omap_pgsz; | |
9d5018de SA |
1329 | u32 ret = -EINVAL; |
1330 | int i; | |
f626b52d | 1331 | |
f626b52d OBC |
1332 | omap_pgsz = bytes_to_iopgsz(bytes); |
1333 | if (omap_pgsz < 0) { | |
6135a891 | 1334 | dev_err(dev, "invalid size to map: %zu\n", bytes); |
f626b52d OBC |
1335 | return -EINVAL; |
1336 | } | |
1337 | ||
6135a891 | 1338 | dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%zx\n", da, &pa, bytes); |
f626b52d | 1339 | |
286f600b | 1340 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1341 | |
9d5018de SA |
1342 | iommu = omap_domain->iommus; |
1343 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1344 | oiommu = iommu->iommu_dev; | |
1345 | ret = omap_iopgtable_store_entry(oiommu, &e); | |
1346 | if (ret) { | |
1347 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", | |
1348 | ret); | |
1349 | break; | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | if (ret) { | |
1354 | while (i--) { | |
1355 | iommu--; | |
1356 | oiommu = iommu->iommu_dev; | |
1357 | iopgtable_clear_entry(oiommu, da); | |
1358 | } | |
1359 | } | |
f626b52d | 1360 | |
b4550d41 | 1361 | return ret; |
f626b52d OBC |
1362 | } |
1363 | ||
5009065d | 1364 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
56f8af5e | 1365 | size_t size, struct iommu_iotlb_gather *gather) |
f626b52d | 1366 | { |
8cf851e0 | 1367 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1368 | struct device *dev = omap_domain->dev; |
1369 | struct omap_iommu_device *iommu; | |
1370 | struct omap_iommu *oiommu; | |
1371 | bool error = false; | |
1372 | size_t bytes = 0; | |
1373 | int i; | |
f626b52d | 1374 | |
6135a891 | 1375 | dev_dbg(dev, "unmapping da 0x%lx size %zu\n", da, size); |
f626b52d | 1376 | |
9d5018de SA |
1377 | iommu = omap_domain->iommus; |
1378 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++) { | |
1379 | oiommu = iommu->iommu_dev; | |
1380 | bytes = iopgtable_clear_entry(oiommu, da); | |
1381 | if (!bytes) | |
1382 | error = true; | |
1383 | } | |
1384 | ||
1385 | /* | |
1386 | * simplify return - we are only checking if any of the iommus | |
1387 | * reported an error, but not if all of them are unmapping the | |
1388 | * same number of entries. This should not occur due to the | |
1389 | * mirror programming. | |
1390 | */ | |
1391 | return error ? 0 : bytes; | |
1392 | } | |
1393 | ||
1394 | static int omap_iommu_count(struct device *dev) | |
1395 | { | |
97ea1202 | 1396 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
9d5018de SA |
1397 | int count = 0; |
1398 | ||
1399 | while (arch_data->iommu_dev) { | |
1400 | count++; | |
1401 | arch_data++; | |
1402 | } | |
1403 | ||
1404 | return count; | |
1405 | } | |
1406 | ||
1407 | /* caller should call cleanup if this function fails */ | |
1408 | static int omap_iommu_attach_init(struct device *dev, | |
1409 | struct omap_iommu_domain *odomain) | |
1410 | { | |
1411 | struct omap_iommu_device *iommu; | |
1412 | int i; | |
1413 | ||
1414 | odomain->num_iommus = omap_iommu_count(dev); | |
1415 | if (!odomain->num_iommus) | |
bd7ebb77 | 1416 | return -ENODEV; |
9d5018de SA |
1417 | |
1418 | odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu), | |
1419 | GFP_ATOMIC); | |
1420 | if (!odomain->iommus) | |
1421 | return -ENOMEM; | |
1422 | ||
1423 | iommu = odomain->iommus; | |
1424 | for (i = 0; i < odomain->num_iommus; i++, iommu++) { | |
1425 | iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC); | |
1426 | if (!iommu->pgtable) | |
1427 | return -ENOMEM; | |
1428 | ||
1429 | /* | |
1430 | * should never fail, but please keep this around to ensure | |
1431 | * we keep the hardware happy | |
1432 | */ | |
1433 | if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable, | |
1434 | IOPGD_TABLE_SIZE))) | |
1435 | return -EINVAL; | |
1436 | } | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain) | |
1442 | { | |
1443 | int i; | |
1444 | struct omap_iommu_device *iommu = odomain->iommus; | |
1445 | ||
1446 | for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++) | |
1447 | kfree(iommu->pgtable); | |
1448 | ||
1449 | kfree(odomain->iommus); | |
1450 | odomain->num_iommus = 0; | |
1451 | odomain->iommus = NULL; | |
f626b52d OBC |
1452 | } |
1453 | ||
1454 | static int | |
1455 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1456 | { | |
97ea1202 | 1457 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
8cf851e0 | 1458 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de | 1459 | struct omap_iommu_device *iommu; |
ede1c2e7 | 1460 | struct omap_iommu *oiommu; |
f626b52d | 1461 | int ret = 0; |
9d5018de | 1462 | int i; |
f626b52d | 1463 | |
ede1c2e7 | 1464 | if (!arch_data || !arch_data->iommu_dev) { |
e3f595b9 | 1465 | dev_err(dev, "device doesn't have an associated iommu\n"); |
bd7ebb77 | 1466 | return -ENODEV; |
e3f595b9 SA |
1467 | } |
1468 | ||
f626b52d OBC |
1469 | spin_lock(&omap_domain->lock); |
1470 | ||
0d364288 SA |
1471 | /* only a single client device can be attached to a domain */ |
1472 | if (omap_domain->dev) { | |
f626b52d | 1473 | dev_err(dev, "iommu domain is already attached\n"); |
f4a14773 | 1474 | ret = -EINVAL; |
f626b52d OBC |
1475 | goto out; |
1476 | } | |
1477 | ||
9d5018de | 1478 | ret = omap_iommu_attach_init(dev, omap_domain); |
ede1c2e7 | 1479 | if (ret) { |
9d5018de SA |
1480 | dev_err(dev, "failed to allocate required iommu data %d\n", |
1481 | ret); | |
1482 | goto init_fail; | |
1483 | } | |
1484 | ||
1485 | iommu = omap_domain->iommus; | |
1486 | for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) { | |
1487 | /* configure and enable the omap iommu */ | |
1488 | oiommu = arch_data->iommu_dev; | |
1489 | ret = omap_iommu_attach(oiommu, iommu->pgtable); | |
1490 | if (ret) { | |
1491 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1492 | goto attach_fail; | |
1493 | } | |
1494 | ||
1495 | oiommu->domain = domain; | |
1496 | iommu->iommu_dev = oiommu; | |
f626b52d OBC |
1497 | } |
1498 | ||
803b5277 | 1499 | omap_domain->dev = dev; |
f626b52d | 1500 | |
9d5018de SA |
1501 | goto out; |
1502 | ||
1503 | attach_fail: | |
1504 | while (i--) { | |
1505 | iommu--; | |
1506 | arch_data--; | |
1507 | oiommu = iommu->iommu_dev; | |
1508 | omap_iommu_detach(oiommu); | |
1509 | iommu->iommu_dev = NULL; | |
1510 | oiommu->domain = NULL; | |
1511 | } | |
1512 | init_fail: | |
1513 | omap_iommu_detach_fini(omap_domain); | |
f626b52d OBC |
1514 | out: |
1515 | spin_unlock(&omap_domain->lock); | |
1516 | return ret; | |
1517 | } | |
1518 | ||
803b5277 | 1519 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
5835b6a6 | 1520 | struct device *dev) |
f626b52d | 1521 | { |
97ea1202 | 1522 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
9d5018de SA |
1523 | struct omap_iommu_device *iommu = omap_domain->iommus; |
1524 | struct omap_iommu *oiommu; | |
1525 | int i; | |
f626b52d | 1526 | |
0d364288 SA |
1527 | if (!omap_domain->dev) { |
1528 | dev_err(dev, "domain has no attached device\n"); | |
1529 | return; | |
1530 | } | |
1531 | ||
f626b52d | 1532 | /* only a single device is supported per domain for now */ |
0d364288 SA |
1533 | if (omap_domain->dev != dev) { |
1534 | dev_err(dev, "invalid attached device\n"); | |
803b5277 | 1535 | return; |
f626b52d OBC |
1536 | } |
1537 | ||
9d5018de SA |
1538 | /* |
1539 | * cleanup in the reverse order of attachment - this addresses | |
1540 | * any h/w dependencies between multiple instances, if any | |
1541 | */ | |
1542 | iommu += (omap_domain->num_iommus - 1); | |
1543 | arch_data += (omap_domain->num_iommus - 1); | |
1544 | for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) { | |
1545 | oiommu = iommu->iommu_dev; | |
1546 | iopgtable_clear_entry_all(oiommu); | |
1547 | ||
1548 | omap_iommu_detach(oiommu); | |
1549 | iommu->iommu_dev = NULL; | |
1550 | oiommu->domain = NULL; | |
1551 | } | |
f626b52d | 1552 | |
9d5018de | 1553 | omap_iommu_detach_fini(omap_domain); |
f626b52d | 1554 | |
803b5277 ORL |
1555 | omap_domain->dev = NULL; |
1556 | } | |
f626b52d | 1557 | |
c1fe9119 | 1558 | static void omap_iommu_set_platform_dma(struct device *dev) |
803b5277 | 1559 | { |
c1fe9119 | 1560 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); |
8cf851e0 | 1561 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
803b5277 ORL |
1562 | |
1563 | spin_lock(&omap_domain->lock); | |
1564 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1565 | spin_unlock(&omap_domain->lock); |
1566 | } | |
1567 | ||
8cf851e0 | 1568 | static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) |
f626b52d OBC |
1569 | { |
1570 | struct omap_iommu_domain *omap_domain; | |
1571 | ||
8cf851e0 JR |
1572 | if (type != IOMMU_DOMAIN_UNMANAGED) |
1573 | return NULL; | |
1574 | ||
f626b52d | 1575 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); |
99ee98d6 | 1576 | if (!omap_domain) |
9d5018de | 1577 | return NULL; |
f626b52d | 1578 | |
f626b52d OBC |
1579 | spin_lock_init(&omap_domain->lock); |
1580 | ||
8cf851e0 JR |
1581 | omap_domain->domain.geometry.aperture_start = 0; |
1582 | omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1; | |
1583 | omap_domain->domain.geometry.force_aperture = true; | |
f626b52d | 1584 | |
8cf851e0 | 1585 | return &omap_domain->domain; |
f626b52d OBC |
1586 | } |
1587 | ||
8cf851e0 | 1588 | static void omap_iommu_domain_free(struct iommu_domain *domain) |
f626b52d | 1589 | { |
8cf851e0 | 1590 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
f626b52d | 1591 | |
803b5277 ORL |
1592 | /* |
1593 | * An iommu device is still attached | |
1594 | * (currently, only one device can be attached) ? | |
1595 | */ | |
0d364288 | 1596 | if (omap_domain->dev) |
803b5277 ORL |
1597 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); |
1598 | ||
f626b52d OBC |
1599 | kfree(omap_domain); |
1600 | } | |
1601 | ||
1602 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
5835b6a6 | 1603 | dma_addr_t da) |
f626b52d | 1604 | { |
8cf851e0 | 1605 | struct omap_iommu_domain *omap_domain = to_omap_domain(domain); |
9d5018de SA |
1606 | struct omap_iommu_device *iommu = omap_domain->iommus; |
1607 | struct omap_iommu *oiommu = iommu->iommu_dev; | |
f626b52d OBC |
1608 | struct device *dev = oiommu->dev; |
1609 | u32 *pgd, *pte; | |
1610 | phys_addr_t ret = 0; | |
1611 | ||
9d5018de SA |
1612 | /* |
1613 | * all the iommus within the domain will have identical programming, | |
1614 | * so perform the lookup using just the first iommu | |
1615 | */ | |
f626b52d OBC |
1616 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); |
1617 | ||
1618 | if (pte) { | |
1619 | if (iopte_is_small(*pte)) | |
1620 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1621 | else if (iopte_is_large(*pte)) | |
1622 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1623 | else | |
2abfcfbc | 1624 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
5835b6a6 | 1625 | (unsigned long long)da); |
f626b52d OBC |
1626 | } else { |
1627 | if (iopgd_is_section(*pgd)) | |
1628 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1629 | else if (iopgd_is_super(*pgd)) | |
1630 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1631 | else | |
2abfcfbc | 1632 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
5835b6a6 | 1633 | (unsigned long long)da); |
f626b52d OBC |
1634 | } |
1635 | ||
1636 | return ret; | |
1637 | } | |
1638 | ||
6785eb91 | 1639 | static struct iommu_device *omap_iommu_probe_device(struct device *dev) |
07a02030 | 1640 | { |
9d5018de | 1641 | struct omap_iommu_arch_data *arch_data, *tmp; |
6785eb91 | 1642 | struct platform_device *pdev; |
ede1c2e7 | 1643 | struct omap_iommu *oiommu; |
07a02030 | 1644 | struct device_node *np; |
9d5018de | 1645 | int num_iommus, i; |
07a02030 LP |
1646 | |
1647 | /* | |
97ea1202 | 1648 | * Allocate the per-device iommu structure for DT-based devices. |
07a02030 LP |
1649 | * |
1650 | * TODO: Simplify this when removing non-DT support completely from the | |
1651 | * IOMMU users. | |
1652 | */ | |
1653 | if (!dev->of_node) | |
6785eb91 | 1654 | return ERR_PTR(-ENODEV); |
07a02030 | 1655 | |
9d5018de SA |
1656 | /* |
1657 | * retrieve the count of IOMMU nodes using phandle size as element size | |
1658 | * since #iommu-cells = 0 for OMAP | |
1659 | */ | |
1660 | num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", | |
1661 | sizeof(phandle)); | |
1662 | if (num_iommus < 0) | |
71ff461c | 1663 | return ERR_PTR(-ENODEV); |
07a02030 | 1664 | |
6396bb22 | 1665 | arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); |
9d5018de | 1666 | if (!arch_data) |
6785eb91 | 1667 | return ERR_PTR(-ENOMEM); |
7d682774 | 1668 | |
9d5018de SA |
1669 | for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) { |
1670 | np = of_parse_phandle(dev->of_node, "iommus", i); | |
1671 | if (!np) { | |
1672 | kfree(arch_data); | |
6785eb91 | 1673 | return ERR_PTR(-EINVAL); |
9d5018de SA |
1674 | } |
1675 | ||
1676 | pdev = of_find_device_by_node(np); | |
604629bc | 1677 | if (!pdev) { |
9d5018de SA |
1678 | of_node_put(np); |
1679 | kfree(arch_data); | |
6785eb91 | 1680 | return ERR_PTR(-ENODEV); |
9d5018de SA |
1681 | } |
1682 | ||
1683 | oiommu = platform_get_drvdata(pdev); | |
1684 | if (!oiommu) { | |
1685 | of_node_put(np); | |
1686 | kfree(arch_data); | |
6785eb91 | 1687 | return ERR_PTR(-EINVAL); |
9d5018de SA |
1688 | } |
1689 | ||
1690 | tmp->iommu_dev = oiommu; | |
604629bc | 1691 | tmp->dev = &pdev->dev; |
ede1c2e7 | 1692 | |
07a02030 | 1693 | of_node_put(np); |
07a02030 LP |
1694 | } |
1695 | ||
97ea1202 | 1696 | dev_iommu_priv_set(dev, arch_data); |
6785eb91 | 1697 | |
9d5018de SA |
1698 | /* |
1699 | * use the first IOMMU alone for the sysfs device linking. | |
1700 | * TODO: Evaluate if a single iommu_group needs to be | |
1701 | * maintained for both IOMMUs | |
1702 | */ | |
1703 | oiommu = arch_data->iommu_dev; | |
28ae1e3e | 1704 | |
6785eb91 | 1705 | return &oiommu->iommu; |
07a02030 LP |
1706 | } |
1707 | ||
6785eb91 | 1708 | static void omap_iommu_release_device(struct device *dev) |
07a02030 | 1709 | { |
97ea1202 | 1710 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
07a02030 LP |
1711 | |
1712 | if (!dev->of_node || !arch_data) | |
1713 | return; | |
1714 | ||
97ea1202 | 1715 | dev_iommu_priv_set(dev, NULL); |
07a02030 | 1716 | kfree(arch_data); |
01611fe8 | 1717 | |
07a02030 LP |
1718 | } |
1719 | ||
28ae1e3e JR |
1720 | static struct iommu_group *omap_iommu_device_group(struct device *dev) |
1721 | { | |
97ea1202 | 1722 | struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); |
8faf5e5a | 1723 | struct iommu_group *group = ERR_PTR(-EINVAL); |
28ae1e3e | 1724 | |
46b14fc6 TK |
1725 | if (!arch_data) |
1726 | return ERR_PTR(-ENODEV); | |
1727 | ||
28ae1e3e | 1728 | if (arch_data->iommu_dev) |
b6d57f1d | 1729 | group = iommu_group_ref_get(arch_data->iommu_dev->group); |
28ae1e3e JR |
1730 | |
1731 | return group; | |
1732 | } | |
1733 | ||
b22f6434 | 1734 | static const struct iommu_ops omap_iommu_ops = { |
8cf851e0 | 1735 | .domain_alloc = omap_iommu_domain_alloc, |
6785eb91 JR |
1736 | .probe_device = omap_iommu_probe_device, |
1737 | .release_device = omap_iommu_release_device, | |
28ae1e3e | 1738 | .device_group = omap_iommu_device_group, |
c1fe9119 | 1739 | .set_platform_dma_ops = omap_iommu_set_platform_dma, |
66bc8cf3 | 1740 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
9a630a4b LB |
1741 | .default_domain_ops = &(const struct iommu_domain_ops) { |
1742 | .attach_dev = omap_iommu_attach_dev, | |
9a630a4b LB |
1743 | .map = omap_iommu_map, |
1744 | .unmap = omap_iommu_unmap, | |
1745 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1746 | .free = omap_iommu_domain_free, | |
1747 | } | |
f626b52d OBC |
1748 | }; |
1749 | ||
a9dcad5e HD |
1750 | static int __init omap_iommu_init(void) |
1751 | { | |
1752 | struct kmem_cache *p; | |
24ce0bab | 1753 | const slab_flags_t flags = SLAB_HWCACHE_ALIGN; |
a9dcad5e | 1754 | size_t align = 1 << 10; /* L2 pagetable alignement */ |
f938aab2 | 1755 | struct device_node *np; |
abaa7e5b | 1756 | int ret; |
f938aab2 TR |
1757 | |
1758 | np = of_find_matching_node(NULL, omap_iommu_of_match); | |
1759 | if (!np) | |
1760 | return 0; | |
1761 | ||
1762 | of_node_put(np); | |
a9dcad5e HD |
1763 | |
1764 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
bfee0cf0 | 1765 | NULL); |
a9dcad5e HD |
1766 | if (!p) |
1767 | return -ENOMEM; | |
1768 | iopte_cachep = p; | |
1769 | ||
61c75352 SA |
1770 | omap_iommu_debugfs_init(); |
1771 | ||
abaa7e5b SA |
1772 | ret = platform_driver_register(&omap_iommu_driver); |
1773 | if (ret) { | |
1774 | pr_err("%s: failed to register driver\n", __func__); | |
1775 | goto fail_driver; | |
1776 | } | |
1777 | ||
abaa7e5b SA |
1778 | return 0; |
1779 | ||
abaa7e5b SA |
1780 | fail_driver: |
1781 | kmem_cache_destroy(iopte_cachep); | |
1782 | return ret; | |
a9dcad5e | 1783 | } |
435792d9 | 1784 | subsys_initcall(omap_iommu_init); |
0cdbf727 | 1785 | /* must be ready before omap3isp is probed */ |