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4e0ee78f HD |
1 | /* |
2 | * OF helpers for IOMMU | |
3 | * | |
4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | */ | |
19 | ||
20 | #include <linux/export.h> | |
7eba1d51 | 21 | #include <linux/iommu.h> |
4e0ee78f HD |
22 | #include <linux/limits.h> |
23 | #include <linux/of.h> | |
cbff5634 | 24 | #include <linux/of_iommu.h> |
b996444c | 25 | #include <linux/of_pci.h> |
a42a7a1f | 26 | #include <linux/slab.h> |
4e0ee78f | 27 | |
1cd076bf WD |
28 | static const struct of_device_id __iommu_of_table_sentinel |
29 | __used __section(__iommu_of_table_end); | |
30 | ||
4e0ee78f HD |
31 | /** |
32 | * of_get_dma_window - Parse *dma-window property and returns 0 if found. | |
33 | * | |
34 | * @dn: device node | |
35 | * @prefix: prefix for property name if any | |
36 | * @index: index to start to parse | |
37 | * @busno: Returns busno if supported. Otherwise pass NULL | |
38 | * @addr: Returns address that DMA starts | |
39 | * @size: Returns the range that DMA can handle | |
40 | * | |
41 | * This supports different formats flexibly. "prefix" can be | |
42 | * configured if any. "busno" and "index" are optionally | |
43 | * specified. Set 0(or NULL) if not used. | |
44 | */ | |
45 | int of_get_dma_window(struct device_node *dn, const char *prefix, int index, | |
46 | unsigned long *busno, dma_addr_t *addr, size_t *size) | |
47 | { | |
48 | const __be32 *dma_window, *end; | |
49 | int bytes, cur_index = 0; | |
50 | char propname[NAME_MAX], addrname[NAME_MAX], sizename[NAME_MAX]; | |
51 | ||
52 | if (!dn || !addr || !size) | |
53 | return -EINVAL; | |
54 | ||
55 | if (!prefix) | |
56 | prefix = ""; | |
57 | ||
58 | snprintf(propname, sizeof(propname), "%sdma-window", prefix); | |
59 | snprintf(addrname, sizeof(addrname), "%s#dma-address-cells", prefix); | |
60 | snprintf(sizename, sizeof(sizename), "%s#dma-size-cells", prefix); | |
61 | ||
62 | dma_window = of_get_property(dn, propname, &bytes); | |
63 | if (!dma_window) | |
64 | return -ENODEV; | |
65 | end = dma_window + bytes / sizeof(*dma_window); | |
66 | ||
67 | while (dma_window < end) { | |
68 | u32 cells; | |
69 | const void *prop; | |
70 | ||
71 | /* busno is one cell if supported */ | |
72 | if (busno) | |
73 | *busno = be32_to_cpup(dma_window++); | |
74 | ||
75 | prop = of_get_property(dn, addrname, NULL); | |
76 | if (!prop) | |
77 | prop = of_get_property(dn, "#address-cells", NULL); | |
78 | ||
79 | cells = prop ? be32_to_cpup(prop) : of_n_addr_cells(dn); | |
80 | if (!cells) | |
81 | return -EINVAL; | |
82 | *addr = of_read_number(dma_window, cells); | |
83 | dma_window += cells; | |
84 | ||
85 | prop = of_get_property(dn, sizename, NULL); | |
86 | cells = prop ? be32_to_cpup(prop) : of_n_size_cells(dn); | |
87 | if (!cells) | |
88 | return -EINVAL; | |
89 | *size = of_read_number(dma_window, cells); | |
90 | dma_window += cells; | |
91 | ||
92 | if (cur_index++ == index) | |
93 | break; | |
94 | } | |
95 | return 0; | |
96 | } | |
97 | EXPORT_SYMBOL_GPL(of_get_dma_window); | |
1cd076bf | 98 | |
b996444c RM |
99 | static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data) |
100 | { | |
101 | struct of_phandle_args *iommu_spec = data; | |
102 | ||
103 | iommu_spec->args[0] = alias; | |
104 | return iommu_spec->np == pdev->bus->dev.of_node; | |
105 | } | |
106 | ||
107 | static const struct iommu_ops | |
108 | *of_pci_iommu_configure(struct pci_dev *pdev, struct device_node *bridge_np) | |
109 | { | |
110 | const struct iommu_ops *ops; | |
111 | struct of_phandle_args iommu_spec; | |
112 | ||
113 | /* | |
114 | * Start by tracing the RID alias down the PCI topology as | |
115 | * far as the host bridge whose OF node we have... | |
116 | * (we're not even attempting to handle multi-alias devices yet) | |
117 | */ | |
118 | iommu_spec.args_count = 1; | |
119 | iommu_spec.np = bridge_np; | |
120 | pci_for_each_dma_alias(pdev, __get_pci_rid, &iommu_spec); | |
121 | /* | |
122 | * ...then find out what that becomes once it escapes the PCI | |
123 | * bus into the system beyond, and which IOMMU it ends up at. | |
124 | */ | |
125 | iommu_spec.np = NULL; | |
126 | if (of_pci_map_rid(bridge_np, iommu_spec.args[0], "iommu-map", | |
127 | "iommu-map-mask", &iommu_spec.np, iommu_spec.args)) | |
128 | return NULL; | |
129 | ||
130 | ops = of_iommu_get_ops(iommu_spec.np); | |
57f98d2f RM |
131 | if (!ops || !ops->of_xlate || |
132 | iommu_fwspec_init(&pdev->dev, &iommu_spec.np->fwnode, ops) || | |
133 | ops->of_xlate(&pdev->dev, &iommu_spec)) | |
b996444c RM |
134 | ops = NULL; |
135 | ||
136 | of_node_put(iommu_spec.np); | |
137 | return ops; | |
138 | } | |
139 | ||
53c92d79 RM |
140 | const struct iommu_ops *of_iommu_configure(struct device *dev, |
141 | struct device_node *master_np) | |
7eba1d51 WD |
142 | { |
143 | struct of_phandle_args iommu_spec; | |
144 | struct device_node *np; | |
53c92d79 | 145 | const struct iommu_ops *ops = NULL; |
7eba1d51 WD |
146 | int idx = 0; |
147 | ||
7b0ce727 | 148 | if (dev_is_pci(dev)) |
b996444c | 149 | return of_pci_iommu_configure(to_pci_dev(dev), master_np); |
ed748621 | 150 | |
7eba1d51 WD |
151 | /* |
152 | * We don't currently walk up the tree looking for a parent IOMMU. | |
153 | * See the `Notes:' section of | |
154 | * Documentation/devicetree/bindings/iommu/iommu.txt | |
155 | */ | |
ed748621 | 156 | while (!of_parse_phandle_with_args(master_np, "iommus", |
7eba1d51 WD |
157 | "#iommu-cells", idx, |
158 | &iommu_spec)) { | |
159 | np = iommu_spec.np; | |
160 | ops = of_iommu_get_ops(np); | |
161 | ||
57f98d2f RM |
162 | if (!ops || !ops->of_xlate || |
163 | iommu_fwspec_init(dev, &np->fwnode, ops) || | |
164 | ops->of_xlate(dev, &iommu_spec)) | |
7eba1d51 WD |
165 | goto err_put_node; |
166 | ||
167 | of_node_put(np); | |
168 | idx++; | |
169 | } | |
170 | ||
171 | return ops; | |
172 | ||
173 | err_put_node: | |
174 | of_node_put(np); | |
175 | return NULL; | |
176 | } | |
177 | ||
bb8e15d6 | 178 | static int __init of_iommu_init(void) |
1cd076bf WD |
179 | { |
180 | struct device_node *np; | |
181 | const struct of_device_id *match, *matches = &__iommu_of_table; | |
182 | ||
183 | for_each_matching_node_and_match(np, matches, &match) { | |
184 | const of_iommu_init_fn init_fn = match->data; | |
185 | ||
186 | if (init_fn(np)) | |
187 | pr_err("Failed to initialise IOMMU %s\n", | |
188 | of_node_full_name(np)); | |
189 | } | |
bb8e15d6 KW |
190 | |
191 | return 0; | |
1cd076bf | 192 | } |
bb8e15d6 | 193 | postcore_initcall_sync(of_iommu_init); |