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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b17336c5 | 2 | /* |
d4cf5bbd PG |
3 | * IOMMU API for MTK architected m4u v1 implementations |
4 | * | |
b17336c5 HZ |
5 | * Copyright (c) 2015-2016 MediaTek Inc. |
6 | * Author: Honghui Zhang <honghui.zhang@mediatek.com> | |
7 | * | |
8 | * Based on driver/iommu/mtk_iommu.c | |
b17336c5 | 9 | */ |
b17336c5 HZ |
10 | #include <linux/bug.h> |
11 | #include <linux/clk.h> | |
12 | #include <linux/component.h> | |
13 | #include <linux/device.h> | |
745b6e74 | 14 | #include <linux/dma-mapping.h> |
b17336c5 HZ |
15 | #include <linux/err.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/iommu.h> | |
19 | #include <linux/iopoll.h> | |
b17336c5 | 20 | #include <linux/list.h> |
8de000cf | 21 | #include <linux/module.h> |
b17336c5 | 22 | #include <linux/of_address.h> |
b17336c5 HZ |
23 | #include <linux/of_irq.h> |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <asm/barrier.h> | |
29 | #include <asm/dma-iommu.h> | |
6a513de3 | 30 | #include <dt-bindings/memory/mtk-memory-port.h> |
b17336c5 HZ |
31 | #include <dt-bindings/memory/mt2701-larb-port.h> |
32 | #include <soc/mediatek/smi.h> | |
b17336c5 HZ |
33 | |
34 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
35 | ||
36 | #define F_ALL_INVLD 0x2 | |
37 | #define F_MMU_INV_RANGE 0x1 | |
38 | #define F_INVLD_EN0 BIT(0) | |
39 | #define F_INVLD_EN1 BIT(1) | |
40 | ||
41 | #define F_MMU_FAULT_VA_MSK 0xfffff000 | |
42 | #define MTK_PROTECT_PA_ALIGN 128 | |
43 | ||
44 | #define REG_MMU_CTRL_REG 0x210 | |
45 | #define F_MMU_CTRL_COHERENT_EN BIT(8) | |
46 | #define REG_MMU_IVRP_PADDR 0x214 | |
47 | #define REG_MMU_INT_CONTROL 0x220 | |
48 | #define F_INT_TRANSLATION_FAULT BIT(0) | |
49 | #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) | |
50 | #define F_INT_INVALID_PA_FAULT BIT(2) | |
51 | #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) | |
52 | #define F_INT_TABLE_WALK_FAULT BIT(4) | |
53 | #define F_INT_TLB_MISS_FAULT BIT(5) | |
54 | #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) | |
55 | #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) | |
56 | ||
57 | #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) | |
58 | #define F_INT_CLR_BIT BIT(12) | |
59 | ||
60 | #define REG_MMU_FAULT_ST 0x224 | |
61 | #define REG_MMU_FAULT_VA 0x228 | |
62 | #define REG_MMU_INVLD_PA 0x22C | |
63 | #define REG_MMU_INT_ID 0x388 | |
64 | #define REG_MMU_INVALIDATE 0x5c0 | |
65 | #define REG_MMU_INVLD_START_A 0x5c4 | |
66 | #define REG_MMU_INVLD_END_A 0x5c8 | |
67 | ||
68 | #define REG_MMU_INV_SEL 0x5d8 | |
69 | #define REG_MMU_STANDARD_AXI_MODE 0x5e8 | |
70 | ||
71 | #define REG_MMU_DCM 0x5f0 | |
72 | #define F_MMU_DCM_ON BIT(1) | |
73 | #define REG_MMU_CPE_DONE 0x60c | |
74 | #define F_DESC_VALID 0x2 | |
75 | #define F_DESC_NONSEC BIT(3) | |
76 | #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) | |
77 | #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) | |
78 | /* MTK generation one iommu HW only support 4K size mapping */ | |
79 | #define MT2701_IOMMU_PAGE_SHIFT 12 | |
80 | #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) | |
de78657e | 81 | #define MT2701_LARB_NR_MAX 3 |
b17336c5 HZ |
82 | |
83 | /* | |
84 | * MTK m4u support 4GB iova address space, and only support 4K page | |
85 | * mapping. So the pagetable size should be exactly as 4M. | |
86 | */ | |
87 | #define M2701_IOMMU_PGT_SIZE SZ_4M | |
88 | ||
ad9b10e5 | 89 | struct mtk_iommu_v1_suspend_reg { |
6a513de3 YW |
90 | u32 standard_axi_mode; |
91 | u32 dcm_dis; | |
92 | u32 ctrl_reg; | |
93 | u32 int_control0; | |
94 | }; | |
95 | ||
ad9b10e5 | 96 | struct mtk_iommu_v1_data { |
9485a04a YW |
97 | void __iomem *base; |
98 | int irq; | |
99 | struct device *dev; | |
100 | struct clk *bclk; | |
101 | phys_addr_t protect_base; /* protect memory base */ | |
ad9b10e5 | 102 | struct mtk_iommu_v1_domain *m4u_dom; |
9485a04a YW |
103 | |
104 | struct iommu_device iommu; | |
105 | struct dma_iommu_mapping *mapping; | |
106 | struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; | |
107 | ||
ad9b10e5 | 108 | struct mtk_iommu_v1_suspend_reg reg; |
9485a04a YW |
109 | }; |
110 | ||
ad9b10e5 | 111 | struct mtk_iommu_v1_domain { |
b17336c5 HZ |
112 | spinlock_t pgtlock; /* lock for page table */ |
113 | struct iommu_domain domain; | |
114 | u32 *pgt_va; | |
115 | dma_addr_t pgt_pa; | |
ad9b10e5 | 116 | struct mtk_iommu_v1_data *data; |
b17336c5 HZ |
117 | }; |
118 | ||
ad9b10e5 | 119 | static int mtk_iommu_v1_bind(struct device *dev) |
9485a04a | 120 | { |
ad9b10e5 | 121 | struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); |
9485a04a YW |
122 | |
123 | return component_bind_all(dev, &data->larb_imu); | |
124 | } | |
125 | ||
ad9b10e5 | 126 | static void mtk_iommu_v1_unbind(struct device *dev) |
9485a04a | 127 | { |
ad9b10e5 | 128 | struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); |
9485a04a YW |
129 | |
130 | component_unbind_all(dev, &data->larb_imu); | |
131 | } | |
132 | ||
ad9b10e5 | 133 | static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom) |
b17336c5 | 134 | { |
ad9b10e5 | 135 | return container_of(dom, struct mtk_iommu_v1_domain, domain); |
b17336c5 HZ |
136 | } |
137 | ||
138 | static const int mt2701_m4u_in_larb[] = { | |
139 | LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, | |
140 | LARB2_PORT_OFFSET, LARB3_PORT_OFFSET | |
141 | }; | |
142 | ||
143 | static inline int mt2701_m4u_to_larb(int id) | |
144 | { | |
145 | int i; | |
146 | ||
147 | for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) | |
148 | if ((id) >= mt2701_m4u_in_larb[i]) | |
149 | return i; | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static inline int mt2701_m4u_to_port(int id) | |
155 | { | |
156 | int larb = mt2701_m4u_to_larb(id); | |
157 | ||
158 | return id - mt2701_m4u_in_larb[larb]; | |
159 | } | |
160 | ||
ad9b10e5 | 161 | static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) |
b17336c5 HZ |
162 | { |
163 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
164 | data->base + REG_MMU_INV_SEL); | |
165 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); | |
166 | wmb(); /* Make sure the tlb flush all done */ | |
167 | } | |
168 | ||
ad9b10e5 YW |
169 | static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data, |
170 | unsigned long iova, size_t size) | |
b17336c5 HZ |
171 | { |
172 | int ret; | |
173 | u32 tmp; | |
174 | ||
175 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
176 | data->base + REG_MMU_INV_SEL); | |
177 | writel_relaxed(iova & F_MMU_FAULT_VA_MSK, | |
178 | data->base + REG_MMU_INVLD_START_A); | |
179 | writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, | |
180 | data->base + REG_MMU_INVLD_END_A); | |
181 | writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); | |
182 | ||
183 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, | |
184 | tmp, tmp != 0, 10, 100000); | |
185 | if (ret) { | |
186 | dev_warn(data->dev, | |
187 | "Partial TLB flush timed out, falling back to full flush\n"); | |
ad9b10e5 | 188 | mtk_iommu_v1_tlb_flush_all(data); |
b17336c5 HZ |
189 | } |
190 | /* Clear the CPE status */ | |
191 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
192 | } | |
193 | ||
ad9b10e5 | 194 | static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) |
b17336c5 | 195 | { |
ad9b10e5 YW |
196 | struct mtk_iommu_v1_data *data = dev_id; |
197 | struct mtk_iommu_v1_domain *dom = data->m4u_dom; | |
b17336c5 HZ |
198 | u32 int_state, regval, fault_iova, fault_pa; |
199 | unsigned int fault_larb, fault_port; | |
200 | ||
201 | /* Read error information from registers */ | |
202 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); | |
203 | fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); | |
204 | ||
205 | fault_iova &= F_MMU_FAULT_VA_MSK; | |
206 | fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); | |
207 | regval = readl_relaxed(data->base + REG_MMU_INT_ID); | |
208 | fault_larb = MT2701_M4U_TF_LARB(regval); | |
209 | fault_port = MT2701_M4U_TF_PORT(regval); | |
210 | ||
211 | /* | |
212 | * MTK v1 iommu HW could not determine whether the fault is read or | |
213 | * write fault, report as read fault. | |
214 | */ | |
215 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, | |
216 | IOMMU_FAULT_READ)) | |
217 | dev_err_ratelimited(data->dev, | |
218 | "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", | |
219 | int_state, fault_iova, fault_pa, | |
220 | fault_larb, fault_port); | |
221 | ||
222 | /* Interrupt clear */ | |
223 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); | |
224 | regval |= F_INT_CLR_BIT; | |
225 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); | |
226 | ||
ad9b10e5 | 227 | mtk_iommu_v1_tlb_flush_all(data); |
b17336c5 HZ |
228 | |
229 | return IRQ_HANDLED; | |
230 | } | |
231 | ||
ad9b10e5 YW |
232 | static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data, |
233 | struct device *dev, bool enable) | |
b17336c5 | 234 | { |
b17336c5 HZ |
235 | struct mtk_smi_larb_iommu *larb_mmu; |
236 | unsigned int larbid, portid; | |
a9bf2eec | 237 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
84672f19 | 238 | int i; |
b17336c5 | 239 | |
84672f19 RM |
240 | for (i = 0; i < fwspec->num_ids; ++i) { |
241 | larbid = mt2701_m4u_to_larb(fwspec->ids[i]); | |
242 | portid = mt2701_m4u_to_port(fwspec->ids[i]); | |
1ee9feb2 | 243 | larb_mmu = &data->larb_imu[larbid]; |
b17336c5 HZ |
244 | |
245 | dev_dbg(dev, "%s iommu port: %d\n", | |
246 | enable ? "enable" : "disable", portid); | |
247 | ||
248 | if (enable) | |
249 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
250 | else | |
251 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
252 | } | |
253 | } | |
254 | ||
ad9b10e5 | 255 | static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data) |
b17336c5 | 256 | { |
ad9b10e5 | 257 | struct mtk_iommu_v1_domain *dom = data->m4u_dom; |
b17336c5 HZ |
258 | |
259 | spin_lock_init(&dom->pgtlock); | |
260 | ||
750afb08 LC |
261 | dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, |
262 | &dom->pgt_pa, GFP_KERNEL); | |
b17336c5 HZ |
263 | if (!dom->pgt_va) |
264 | return -ENOMEM; | |
265 | ||
266 | writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); | |
267 | ||
268 | dom->data = data; | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
ad9b10e5 | 273 | static struct iommu_domain *mtk_iommu_v1_domain_alloc(unsigned type) |
b17336c5 | 274 | { |
ad9b10e5 | 275 | struct mtk_iommu_v1_domain *dom; |
b17336c5 HZ |
276 | |
277 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
278 | return NULL; | |
279 | ||
280 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
281 | if (!dom) | |
282 | return NULL; | |
283 | ||
284 | return &dom->domain; | |
285 | } | |
286 | ||
ad9b10e5 | 287 | static void mtk_iommu_v1_domain_free(struct iommu_domain *domain) |
b17336c5 | 288 | { |
ad9b10e5 YW |
289 | struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); |
290 | struct mtk_iommu_v1_data *data = dom->data; | |
b17336c5 HZ |
291 | |
292 | dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, | |
293 | dom->pgt_va, dom->pgt_pa); | |
294 | kfree(to_mtk_domain(domain)); | |
295 | } | |
296 | ||
ad9b10e5 | 297 | static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev) |
b17336c5 | 298 | { |
ad9b10e5 YW |
299 | struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); |
300 | struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); | |
8bbe13f5 | 301 | struct dma_iommu_mapping *mtk_mapping; |
b17336c5 HZ |
302 | int ret; |
303 | ||
8bbe13f5 | 304 | /* Only allow the domain created internally. */ |
58960172 | 305 | mtk_mapping = data->mapping; |
8bbe13f5 YW |
306 | if (mtk_mapping->domain != domain) |
307 | return 0; | |
b17336c5 | 308 | |
b17336c5 HZ |
309 | if (!data->m4u_dom) { |
310 | data->m4u_dom = dom; | |
ad9b10e5 | 311 | ret = mtk_iommu_v1_domain_finalise(data); |
b17336c5 HZ |
312 | if (ret) { |
313 | data->m4u_dom = NULL; | |
314 | return ret; | |
315 | } | |
316 | } | |
317 | ||
ad9b10e5 | 318 | mtk_iommu_v1_config(data, dev, true); |
b17336c5 HZ |
319 | return 0; |
320 | } | |
321 | ||
ad9b10e5 | 322 | static void mtk_iommu_v1_detach_device(struct iommu_domain *domain, struct device *dev) |
b17336c5 | 323 | { |
ad9b10e5 | 324 | struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); |
b17336c5 | 325 | |
ad9b10e5 | 326 | mtk_iommu_v1_config(data, dev, false); |
b17336c5 HZ |
327 | } |
328 | ||
ad9b10e5 | 329 | static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova, |
b577f7e6 RM |
330 | phys_addr_t paddr, size_t pgsize, size_t pgcount, |
331 | int prot, gfp_t gfp, size_t *mapped) | |
b17336c5 | 332 | { |
ad9b10e5 | 333 | struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); |
b17336c5 HZ |
334 | unsigned long flags; |
335 | unsigned int i; | |
336 | u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); | |
337 | u32 pabase = (u32)paddr; | |
b17336c5 HZ |
338 | |
339 | spin_lock_irqsave(&dom->pgtlock, flags); | |
b577f7e6 RM |
340 | for (i = 0; i < pgcount; i++) { |
341 | if (pgt_base_iova[i]) | |
b17336c5 | 342 | break; |
b17336c5 HZ |
343 | pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; |
344 | pabase += MT2701_IOMMU_PAGE_SIZE; | |
b17336c5 HZ |
345 | } |
346 | ||
347 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
348 | ||
b577f7e6 RM |
349 | *mapped = i * MT2701_IOMMU_PAGE_SIZE; |
350 | mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped); | |
b17336c5 | 351 | |
b577f7e6 | 352 | return i == pgcount ? 0 : -EEXIST; |
b17336c5 HZ |
353 | } |
354 | ||
ad9b10e5 | 355 | static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova, |
b577f7e6 RM |
356 | size_t pgsize, size_t pgcount, |
357 | struct iommu_iotlb_gather *gather) | |
b17336c5 | 358 | { |
ad9b10e5 | 359 | struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); |
b17336c5 HZ |
360 | unsigned long flags; |
361 | u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); | |
b577f7e6 | 362 | size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE; |
b17336c5 HZ |
363 | |
364 | spin_lock_irqsave(&dom->pgtlock, flags); | |
b577f7e6 | 365 | memset(pgt_base_iova, 0, pgcount * sizeof(u32)); |
b17336c5 HZ |
366 | spin_unlock_irqrestore(&dom->pgtlock, flags); |
367 | ||
ad9b10e5 | 368 | mtk_iommu_v1_tlb_flush_range(dom->data, iova, size); |
b17336c5 HZ |
369 | |
370 | return size; | |
371 | } | |
372 | ||
ad9b10e5 | 373 | static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) |
b17336c5 | 374 | { |
ad9b10e5 | 375 | struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); |
b17336c5 HZ |
376 | unsigned long flags; |
377 | phys_addr_t pa; | |
378 | ||
379 | spin_lock_irqsave(&dom->pgtlock, flags); | |
380 | pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); | |
381 | pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); | |
382 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
383 | ||
384 | return pa; | |
385 | } | |
386 | ||
ad9b10e5 | 387 | static const struct iommu_ops mtk_iommu_v1_ops; |
84672f19 | 388 | |
b17336c5 HZ |
389 | /* |
390 | * MTK generation one iommu HW only support one iommu domain, and all the client | |
391 | * sharing the same iova address space. | |
392 | */ | |
ad9b10e5 | 393 | static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_args *args) |
b17336c5 | 394 | { |
a9bf2eec | 395 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
ad9b10e5 | 396 | struct mtk_iommu_v1_data *data; |
b17336c5 HZ |
397 | struct platform_device *m4updev; |
398 | struct dma_iommu_mapping *mtk_mapping; | |
b17336c5 HZ |
399 | int ret; |
400 | ||
401 | if (args->args_count != 1) { | |
402 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
403 | args->args_count); | |
404 | return -EINVAL; | |
405 | } | |
406 | ||
a9bf2eec | 407 | if (!fwspec) { |
ad9b10e5 | 408 | ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops); |
84672f19 RM |
409 | if (ret) |
410 | return ret; | |
a9bf2eec | 411 | fwspec = dev_iommu_fwspec_get(dev); |
ad9b10e5 | 412 | } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) { |
84672f19 RM |
413 | return -EINVAL; |
414 | } | |
415 | ||
3524b559 | 416 | if (!dev_iommu_priv_get(dev)) { |
b17336c5 HZ |
417 | /* Get the m4u device */ |
418 | m4updev = of_find_device_by_node(args->np); | |
419 | if (WARN_ON(!m4updev)) | |
420 | return -EINVAL; | |
421 | ||
3524b559 | 422 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
b17336c5 HZ |
423 | } |
424 | ||
84672f19 RM |
425 | ret = iommu_fwspec_add_ids(dev, args->args, 1); |
426 | if (ret) | |
427 | return ret; | |
b17336c5 | 428 | |
3524b559 | 429 | data = dev_iommu_priv_get(dev); |
58960172 | 430 | mtk_mapping = data->mapping; |
b17336c5 HZ |
431 | if (!mtk_mapping) { |
432 | /* MTK iommu support 4GB iova address space. */ | |
433 | mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, | |
434 | 0, 1ULL << 32); | |
84672f19 RM |
435 | if (IS_ERR(mtk_mapping)) |
436 | return PTR_ERR(mtk_mapping); | |
437 | ||
58960172 | 438 | data->mapping = mtk_mapping; |
b17336c5 HZ |
439 | } |
440 | ||
b17336c5 | 441 | return 0; |
b17336c5 HZ |
442 | } |
443 | ||
ad9b10e5 | 444 | static int mtk_iommu_v1_def_domain_type(struct device *dev) |
8bbe13f5 YW |
445 | { |
446 | return IOMMU_DOMAIN_UNMANAGED; | |
447 | } | |
448 | ||
ad9b10e5 | 449 | static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) |
b17336c5 | 450 | { |
a9bf2eec | 451 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b17336c5 | 452 | struct of_phandle_args iommu_spec; |
ad9b10e5 | 453 | struct mtk_iommu_v1_data *data; |
635319a4 YW |
454 | int err, idx = 0, larbid, larbidx; |
455 | struct device_link *link; | |
456 | struct device *larbdev; | |
b17336c5 | 457 | |
822a2ed8 YW |
458 | /* |
459 | * In the deferred case, free the existed fwspec. | |
460 | * Always initialize the fwspec internally. | |
461 | */ | |
462 | if (fwspec) { | |
463 | iommu_fwspec_free(dev); | |
464 | fwspec = dev_iommu_fwspec_get(dev); | |
465 | } | |
466 | ||
f90a9a85 YW |
467 | while (!of_parse_phandle_with_args(dev->of_node, "iommus", |
468 | "#iommu-cells", | |
469 | idx, &iommu_spec)) { | |
b17336c5 | 470 | |
ad9b10e5 | 471 | err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); |
f90a9a85 YW |
472 | of_node_put(iommu_spec.np); |
473 | if (err) | |
474 | return ERR_PTR(err); | |
da5d2748 JR |
475 | |
476 | /* dev->iommu_fwspec might have changed */ | |
477 | fwspec = dev_iommu_fwspec_get(dev); | |
f90a9a85 | 478 | idx++; |
b17336c5 HZ |
479 | } |
480 | ||
ad9b10e5 | 481 | if (!fwspec || fwspec->ops != &mtk_iommu_v1_ops) |
57dbf81f | 482 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
b17336c5 | 483 | |
57dbf81f | 484 | data = dev_iommu_priv_get(dev); |
b17336c5 | 485 | |
635319a4 YW |
486 | /* Link the consumer device with the smi-larb device(supplier) */ |
487 | larbid = mt2701_m4u_to_larb(fwspec->ids[0]); | |
de78657e MC |
488 | if (larbid >= MT2701_LARB_NR_MAX) |
489 | return ERR_PTR(-EINVAL); | |
490 | ||
635319a4 YW |
491 | for (idx = 1; idx < fwspec->num_ids; idx++) { |
492 | larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); | |
493 | if (larbid != larbidx) { | |
494 | dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", | |
495 | larbid, larbidx); | |
496 | return ERR_PTR(-EINVAL); | |
497 | } | |
498 | } | |
499 | ||
500 | larbdev = data->larb_imu[larbid].dev; | |
de78657e MC |
501 | if (!larbdev) |
502 | return ERR_PTR(-EINVAL); | |
503 | ||
635319a4 YW |
504 | link = device_link_add(dev, larbdev, |
505 | DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); | |
506 | if (!link) | |
507 | dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); | |
508 | ||
57dbf81f JR |
509 | return &data->iommu; |
510 | } | |
f3e827d7 | 511 | |
ad9b10e5 | 512 | static void mtk_iommu_v1_probe_finalize(struct device *dev) |
57dbf81f JR |
513 | { |
514 | struct dma_iommu_mapping *mtk_mapping; | |
ad9b10e5 | 515 | struct mtk_iommu_v1_data *data; |
57dbf81f JR |
516 | int err; |
517 | ||
518 | data = dev_iommu_priv_get(dev); | |
58960172 | 519 | mtk_mapping = data->mapping; |
f3e827d7 | 520 | |
57dbf81f JR |
521 | err = arm_iommu_attach_device(dev, mtk_mapping); |
522 | if (err) | |
523 | dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); | |
b17336c5 HZ |
524 | } |
525 | ||
ad9b10e5 | 526 | static void mtk_iommu_v1_release_device(struct device *dev) |
b17336c5 | 527 | { |
a9bf2eec | 528 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
ad9b10e5 | 529 | struct mtk_iommu_v1_data *data; |
635319a4 YW |
530 | struct device *larbdev; |
531 | unsigned int larbid; | |
6f66ea09 | 532 | |
635319a4 YW |
533 | data = dev_iommu_priv_get(dev); |
534 | larbid = mt2701_m4u_to_larb(fwspec->ids[0]); | |
535 | larbdev = data->larb_imu[larbid].dev; | |
536 | device_link_remove(dev, larbdev); | |
b17336c5 HZ |
537 | } |
538 | ||
ad9b10e5 | 539 | static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) |
b17336c5 HZ |
540 | { |
541 | u32 regval; | |
542 | int ret; | |
543 | ||
544 | ret = clk_prepare_enable(data->bclk); | |
545 | if (ret) { | |
546 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
547 | return ret; | |
548 | } | |
549 | ||
550 | regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); | |
551 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); | |
552 | ||
553 | regval = F_INT_TRANSLATION_FAULT | | |
554 | F_INT_MAIN_MULTI_HIT_FAULT | | |
555 | F_INT_INVALID_PA_FAULT | | |
556 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
557 | F_INT_TABLE_WALK_FAULT | | |
558 | F_INT_TLB_MISS_FAULT | | |
559 | F_INT_PFH_DMA_FIFO_OVERFLOW | | |
560 | F_INT_MISS_DMA_FIFO_OVERFLOW; | |
561 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); | |
562 | ||
563 | /* protect memory,hw will write here while translation fault */ | |
564 | writel_relaxed(data->protect_base, | |
565 | data->base + REG_MMU_IVRP_PADDR); | |
566 | ||
567 | writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); | |
568 | ||
ad9b10e5 | 569 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0, |
b17336c5 HZ |
570 | dev_name(data->dev), (void *)data)) { |
571 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
572 | clk_disable_unprepare(data->bclk); | |
573 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
574 | return -ENODEV; | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
ad9b10e5 YW |
580 | static const struct iommu_ops mtk_iommu_v1_ops = { |
581 | .domain_alloc = mtk_iommu_v1_domain_alloc, | |
582 | .probe_device = mtk_iommu_v1_probe_device, | |
583 | .probe_finalize = mtk_iommu_v1_probe_finalize, | |
584 | .release_device = mtk_iommu_v1_release_device, | |
585 | .def_domain_type = mtk_iommu_v1_def_domain_type, | |
57dbf81f | 586 | .device_group = generic_device_group, |
b577f7e6 | 587 | .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE, |
8de000cf | 588 | .owner = THIS_MODULE, |
9a630a4b | 589 | .default_domain_ops = &(const struct iommu_domain_ops) { |
ad9b10e5 YW |
590 | .attach_dev = mtk_iommu_v1_attach_device, |
591 | .detach_dev = mtk_iommu_v1_detach_device, | |
b577f7e6 RM |
592 | .map_pages = mtk_iommu_v1_map, |
593 | .unmap_pages = mtk_iommu_v1_unmap, | |
ad9b10e5 YW |
594 | .iova_to_phys = mtk_iommu_v1_iova_to_phys, |
595 | .free = mtk_iommu_v1_domain_free, | |
9a630a4b | 596 | } |
b17336c5 HZ |
597 | }; |
598 | ||
ad9b10e5 | 599 | static const struct of_device_id mtk_iommu_v1_of_ids[] = { |
b17336c5 HZ |
600 | { .compatible = "mediatek,mt2701-m4u", }, |
601 | {} | |
602 | }; | |
603 | ||
ad9b10e5 YW |
604 | static const struct component_master_ops mtk_iommu_v1_com_ops = { |
605 | .bind = mtk_iommu_v1_bind, | |
606 | .unbind = mtk_iommu_v1_unbind, | |
b17336c5 HZ |
607 | }; |
608 | ||
ad9b10e5 | 609 | static int mtk_iommu_v1_probe(struct platform_device *pdev) |
b17336c5 | 610 | { |
b17336c5 | 611 | struct device *dev = &pdev->dev; |
ad9b10e5 | 612 | struct mtk_iommu_v1_data *data; |
b17336c5 HZ |
613 | struct resource *res; |
614 | struct component_match *match = NULL; | |
b17336c5 | 615 | void *protect; |
f90a9a85 | 616 | int larb_nr, ret, i; |
b17336c5 HZ |
617 | |
618 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
619 | if (!data) | |
620 | return -ENOMEM; | |
621 | ||
622 | data->dev = dev; | |
623 | ||
624 | /* Protect memory. HW will access here while translation fault.*/ | |
625 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, | |
626 | GFP_KERNEL | GFP_DMA); | |
627 | if (!protect) | |
628 | return -ENOMEM; | |
629 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
630 | ||
631 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
632 | data->base = devm_ioremap_resource(dev, res); | |
633 | if (IS_ERR(data->base)) | |
634 | return PTR_ERR(data->base); | |
635 | ||
636 | data->irq = platform_get_irq(pdev, 0); | |
637 | if (data->irq < 0) | |
638 | return data->irq; | |
639 | ||
640 | data->bclk = devm_clk_get(dev, "bclk"); | |
641 | if (IS_ERR(data->bclk)) | |
642 | return PTR_ERR(data->bclk); | |
643 | ||
f90a9a85 YW |
644 | larb_nr = of_count_phandle_with_args(dev->of_node, |
645 | "mediatek,larbs", NULL); | |
646 | if (larb_nr < 0) | |
647 | return larb_nr; | |
648 | ||
649 | for (i = 0; i < larb_nr; i++) { | |
650 | struct device_node *larbnode; | |
b17336c5 | 651 | struct platform_device *plarbdev; |
b17336c5 | 652 | |
f90a9a85 YW |
653 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); |
654 | if (!larbnode) | |
655 | return -EINVAL; | |
b17336c5 | 656 | |
f90a9a85 YW |
657 | if (!of_device_is_available(larbnode)) { |
658 | of_node_put(larbnode); | |
b17336c5 | 659 | continue; |
f90a9a85 | 660 | } |
b17336c5 | 661 | |
f90a9a85 | 662 | plarbdev = of_find_device_by_node(larbnode); |
b17336c5 | 663 | if (!plarbdev) { |
f90a9a85 | 664 | of_node_put(larbnode); |
2fb0feed | 665 | return -ENODEV; |
b17336c5 | 666 | } |
7d09aaf8 YW |
667 | if (!plarbdev->dev.driver) { |
668 | of_node_put(larbnode); | |
669 | return -EPROBE_DEFER; | |
670 | } | |
f90a9a85 | 671 | data->larb_imu[i].dev = &plarbdev->dev; |
b17336c5 | 672 | |
4811a485 YW |
673 | component_match_add_release(dev, &match, component_release_of, |
674 | component_compare_of, larbnode); | |
b17336c5 HZ |
675 | } |
676 | ||
b17336c5 HZ |
677 | platform_set_drvdata(pdev, data); |
678 | ||
ad9b10e5 | 679 | ret = mtk_iommu_v1_hw_init(data); |
b17336c5 HZ |
680 | if (ret) |
681 | return ret; | |
682 | ||
6f66ea09 JR |
683 | ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, |
684 | dev_name(&pdev->dev)); | |
685 | if (ret) | |
142e821f | 686 | goto out_clk_unprepare; |
6f66ea09 | 687 | |
ad9b10e5 | 688 | ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev); |
6f66ea09 | 689 | if (ret) |
ac304c07 | 690 | goto out_sysfs_remove; |
6f66ea09 | 691 | |
ad9b10e5 | 692 | ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match); |
ac304c07 | 693 | if (ret) |
7341c365 | 694 | goto out_dev_unreg; |
ac304c07 YW |
695 | return ret; |
696 | ||
ac304c07 YW |
697 | out_dev_unreg: |
698 | iommu_device_unregister(&data->iommu); | |
699 | out_sysfs_remove: | |
700 | iommu_device_sysfs_remove(&data->iommu); | |
142e821f CJ |
701 | out_clk_unprepare: |
702 | clk_disable_unprepare(data->bclk); | |
ac304c07 | 703 | return ret; |
b17336c5 HZ |
704 | } |
705 | ||
ad9b10e5 | 706 | static int mtk_iommu_v1_remove(struct platform_device *pdev) |
b17336c5 | 707 | { |
ad9b10e5 | 708 | struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev); |
b17336c5 | 709 | |
6f66ea09 JR |
710 | iommu_device_sysfs_remove(&data->iommu); |
711 | iommu_device_unregister(&data->iommu); | |
712 | ||
b17336c5 HZ |
713 | clk_disable_unprepare(data->bclk); |
714 | devm_free_irq(&pdev->dev, data->irq, data); | |
ad9b10e5 | 715 | component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops); |
b17336c5 HZ |
716 | return 0; |
717 | } | |
718 | ||
ad9b10e5 | 719 | static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev) |
b17336c5 | 720 | { |
ad9b10e5 YW |
721 | struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); |
722 | struct mtk_iommu_v1_suspend_reg *reg = &data->reg; | |
b17336c5 HZ |
723 | void __iomem *base = data->base; |
724 | ||
725 | reg->standard_axi_mode = readl_relaxed(base + | |
726 | REG_MMU_STANDARD_AXI_MODE); | |
727 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); | |
728 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
729 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); | |
730 | return 0; | |
731 | } | |
732 | ||
ad9b10e5 | 733 | static int __maybe_unused mtk_iommu_v1_resume(struct device *dev) |
b17336c5 | 734 | { |
ad9b10e5 YW |
735 | struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); |
736 | struct mtk_iommu_v1_suspend_reg *reg = &data->reg; | |
b17336c5 HZ |
737 | void __iomem *base = data->base; |
738 | ||
739 | writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); | |
740 | writel_relaxed(reg->standard_axi_mode, | |
741 | base + REG_MMU_STANDARD_AXI_MODE); | |
742 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); | |
743 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
744 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); | |
745 | writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); | |
746 | return 0; | |
747 | } | |
748 | ||
ad9b10e5 YW |
749 | static const struct dev_pm_ops mtk_iommu_v1_pm_ops = { |
750 | SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume) | |
b17336c5 HZ |
751 | }; |
752 | ||
ad9b10e5 YW |
753 | static struct platform_driver mtk_iommu_v1_driver = { |
754 | .probe = mtk_iommu_v1_probe, | |
755 | .remove = mtk_iommu_v1_remove, | |
b17336c5 | 756 | .driver = { |
395df08d | 757 | .name = "mtk-iommu-v1", |
ad9b10e5 YW |
758 | .of_match_table = mtk_iommu_v1_of_ids, |
759 | .pm = &mtk_iommu_v1_pm_ops, | |
b17336c5 HZ |
760 | } |
761 | }; | |
ad9b10e5 | 762 | module_platform_driver(mtk_iommu_v1_driver); |
b17336c5 | 763 | |
8de000cf YW |
764 | MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); |
765 | MODULE_LICENSE("GPL v2"); |