Commit | Line | Data |
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1802d0be | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
9ca340c9 HZ |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Honghui Zhang <honghui.zhang@mediatek.com> | |
9ca340c9 HZ |
5 | */ |
6 | ||
7 | #ifndef _MTK_IOMMU_H_ | |
8 | #define _MTK_IOMMU_H_ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/component.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/io.h> | |
b77cf11f | 14 | #include <linux/io-pgtable.h> |
9ca340c9 HZ |
15 | #include <linux/iommu.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <soc/mediatek/smi.h> | |
19 | ||
9ca340c9 HZ |
20 | struct mtk_iommu_suspend_reg { |
21 | u32 standard_axi_mode; | |
22 | u32 dcm_dis; | |
23 | u32 ctrl_reg; | |
24 | u32 int_control0; | |
25 | u32 int_main_control; | |
70ca608b | 26 | u32 ivrp_paddr; |
b9475b34 | 27 | u32 vld_pa_rng; |
9ca340c9 HZ |
28 | }; |
29 | ||
e6dec923 YW |
30 | enum mtk_iommu_plat { |
31 | M4U_MT2701, | |
32 | M4U_MT2712, | |
33 | M4U_MT8173, | |
907ba6a1 | 34 | M4U_MT8183, |
e6dec923 YW |
35 | }; |
36 | ||
cecdce9d YW |
37 | struct mtk_iommu_plat_data { |
38 | enum mtk_iommu_plat m4u_plat; | |
b4dad40e | 39 | bool has_4gb_mode; |
2aa4c259 YW |
40 | |
41 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
42 | bool has_bclk; | |
2b326d8b | 43 | bool has_vld_pa_rng; |
50822b0b | 44 | bool reset_axi; |
b3e5eee7 | 45 | unsigned char larbid_remap[MTK_LARB_NR_MAX]; |
cecdce9d YW |
46 | }; |
47 | ||
9ca340c9 HZ |
48 | struct mtk_iommu_domain; |
49 | ||
50 | struct mtk_iommu_data { | |
51 | void __iomem *base; | |
52 | int irq; | |
53 | struct device *dev; | |
54 | struct clk *bclk; | |
55 | phys_addr_t protect_base; /* protect memory base */ | |
56 | struct mtk_iommu_suspend_reg reg; | |
57 | struct mtk_iommu_domain *m4u_dom; | |
58 | struct iommu_group *m4u_group; | |
9ca340c9 | 59 | bool enable_4GB; |
98a8f63e | 60 | bool tlb_flush_active; |
b16c0170 JR |
61 | |
62 | struct iommu_device iommu; | |
cecdce9d | 63 | const struct mtk_iommu_plat_data *plat_data; |
7c3a2ec0 YW |
64 | |
65 | struct list_head list; | |
1ee9feb2 | 66 | struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; |
9ca340c9 HZ |
67 | }; |
68 | ||
9a8a5dcf | 69 | static inline int compare_of(struct device *dev, void *data) |
9ca340c9 HZ |
70 | { |
71 | return dev->of_node == data; | |
72 | } | |
73 | ||
00c7c81f RK |
74 | static inline void release_of(struct device *dev, void *data) |
75 | { | |
76 | of_node_put(data); | |
77 | } | |
78 | ||
9a8a5dcf | 79 | static inline int mtk_iommu_bind(struct device *dev) |
9ca340c9 HZ |
80 | { |
81 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
82 | ||
1ee9feb2 | 83 | return component_bind_all(dev, &data->larb_imu); |
9ca340c9 HZ |
84 | } |
85 | ||
9a8a5dcf | 86 | static inline void mtk_iommu_unbind(struct device *dev) |
9ca340c9 HZ |
87 | { |
88 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
89 | ||
1ee9feb2 | 90 | component_unbind_all(dev, &data->larb_imu); |
9ca340c9 HZ |
91 | } |
92 | ||
93 | #endif |