Commit | Line | Data |
---|---|---|
9ca340c9 HZ |
1 | /* |
2 | * Copyright (c) 2015-2016 MediaTek Inc. | |
3 | * Author: Honghui Zhang <honghui.zhang@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #ifndef _MTK_IOMMU_H_ | |
16 | #define _MTK_IOMMU_H_ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/component.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/io.h> | |
b77cf11f | 22 | #include <linux/io-pgtable.h> |
9ca340c9 HZ |
23 | #include <linux/iommu.h> |
24 | #include <linux/list.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <soc/mediatek/smi.h> | |
27 | ||
9ca340c9 HZ |
28 | struct mtk_iommu_suspend_reg { |
29 | u32 standard_axi_mode; | |
30 | u32 dcm_dis; | |
31 | u32 ctrl_reg; | |
32 | u32 int_control0; | |
33 | u32 int_main_control; | |
70ca608b | 34 | u32 ivrp_paddr; |
9ca340c9 HZ |
35 | }; |
36 | ||
e6dec923 YW |
37 | enum mtk_iommu_plat { |
38 | M4U_MT2701, | |
39 | M4U_MT2712, | |
40 | M4U_MT8173, | |
41 | }; | |
42 | ||
9ca340c9 HZ |
43 | struct mtk_iommu_domain; |
44 | ||
45 | struct mtk_iommu_data { | |
46 | void __iomem *base; | |
47 | int irq; | |
48 | struct device *dev; | |
49 | struct clk *bclk; | |
50 | phys_addr_t protect_base; /* protect memory base */ | |
51 | struct mtk_iommu_suspend_reg reg; | |
52 | struct mtk_iommu_domain *m4u_dom; | |
53 | struct iommu_group *m4u_group; | |
54 | struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */ | |
55 | bool enable_4GB; | |
98a8f63e | 56 | bool tlb_flush_active; |
b16c0170 JR |
57 | |
58 | struct iommu_device iommu; | |
e6dec923 | 59 | enum mtk_iommu_plat m4u_plat; |
7c3a2ec0 YW |
60 | |
61 | struct list_head list; | |
9ca340c9 HZ |
62 | }; |
63 | ||
9a8a5dcf | 64 | static inline int compare_of(struct device *dev, void *data) |
9ca340c9 HZ |
65 | { |
66 | return dev->of_node == data; | |
67 | } | |
68 | ||
00c7c81f RK |
69 | static inline void release_of(struct device *dev, void *data) |
70 | { | |
71 | of_node_put(data); | |
72 | } | |
73 | ||
9a8a5dcf | 74 | static inline int mtk_iommu_bind(struct device *dev) |
9ca340c9 HZ |
75 | { |
76 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
77 | ||
78 | return component_bind_all(dev, &data->smi_imu); | |
79 | } | |
80 | ||
9a8a5dcf | 81 | static inline void mtk_iommu_unbind(struct device *dev) |
9ca340c9 HZ |
82 | { |
83 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
84 | ||
85 | component_unbind_all(dev, &data->smi_imu); | |
86 | } | |
87 | ||
88 | #endif |