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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe | 5 | */ |
ef0f0986 | 6 | #include <linux/bitfield.h> |
0df4fabe YW |
7 | #include <linux/bug.h> |
8 | #include <linux/clk.h> | |
9 | #include <linux/component.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/dma-iommu.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/iommu.h> | |
16 | #include <linux/iopoll.h> | |
17 | #include <linux/list.h> | |
c2c59456 | 18 | #include <linux/mfd/syscon.h> |
0df4fabe YW |
19 | #include <linux/of_address.h> |
20 | #include <linux/of_iommu.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/platform_device.h> | |
baf94e6e | 24 | #include <linux/pm_runtime.h> |
c2c59456 | 25 | #include <linux/regmap.h> |
0df4fabe YW |
26 | #include <linux/slab.h> |
27 | #include <linux/spinlock.h> | |
c2c59456 | 28 | #include <linux/soc/mediatek/infracfg.h> |
0df4fabe | 29 | #include <asm/barrier.h> |
0df4fabe YW |
30 | #include <soc/mediatek/smi.h> |
31 | ||
9ca340c9 | 32 | #include "mtk_iommu.h" |
0df4fabe YW |
33 | |
34 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
907ba6a1 | 35 | #define MMU_PT_ADDR_MASK GENMASK(31, 7) |
0df4fabe YW |
36 | |
37 | #define REG_MMU_INVALIDATE 0x020 | |
38 | #define F_ALL_INVLD 0x2 | |
39 | #define F_MMU_INV_RANGE 0x1 | |
40 | ||
41 | #define REG_MMU_INVLD_START_A 0x024 | |
42 | #define REG_MMU_INVLD_END_A 0x028 | |
43 | ||
068c86e9 | 44 | #define REG_MMU_INV_SEL_GEN2 0x02c |
b053bc71 | 45 | #define REG_MMU_INV_SEL_GEN1 0x038 |
0df4fabe YW |
46 | #define F_INVLD_EN0 BIT(0) |
47 | #define F_INVLD_EN1 BIT(1) | |
48 | ||
75eed350 | 49 | #define REG_MMU_MISC_CTRL 0x048 |
4bb2bf4c CH |
50 | #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) |
51 | #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) | |
52 | ||
0df4fabe | 53 | #define REG_MMU_DCM_DIS 0x050 |
35c1b48d CH |
54 | #define REG_MMU_WR_LEN_CTRL 0x054 |
55 | #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) | |
0df4fabe YW |
56 | |
57 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 58 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 59 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 60 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
61 | |
62 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 63 | |
30e2fccf YW |
64 | #define REG_MMU_VLD_PA_RNG 0x118 |
65 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
66 | |
67 | #define REG_MMU_INT_CONTROL0 0x120 | |
68 | #define F_L2_MULIT_HIT_EN BIT(0) | |
69 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
70 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
71 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
72 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
73 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
74 | #define F_INT_CLR_BIT BIT(12) | |
75 | ||
76 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
77 | /* mmu0 | mmu1 */ |
78 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
79 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
80 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
81 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
82 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
83 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
84 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
85 | |
86 | #define REG_MMU_CPE_DONE 0x12C | |
87 | ||
88 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
89 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
90 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 91 | |
15a01f4c | 92 | #define REG_MMU0_FAULT_VA 0x13c |
ef0f0986 YW |
93 | #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) |
94 | #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) | |
95 | #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) | |
0df4fabe YW |
96 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
97 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
98 | ||
15a01f4c YW |
99 | #define REG_MMU0_INVLD_PA 0x140 |
100 | #define REG_MMU1_FAULT_VA 0x144 | |
101 | #define REG_MMU1_INVLD_PA 0x148 | |
102 | #define REG_MMU0_INT_ID 0x150 | |
103 | #define REG_MMU1_INT_ID 0x154 | |
37276e00 CH |
104 | #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
105 | #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) | |
15a01f4c YW |
106 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
107 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
0df4fabe | 108 | |
829316b3 | 109 | #define MTK_PROTECT_PA_ALIGN 256 |
0df4fabe | 110 | |
6b717796 CH |
111 | #define HAS_4GB_MODE BIT(0) |
112 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
113 | #define HAS_BCLK BIT(1) | |
114 | #define HAS_VLD_PA_RNG BIT(2) | |
115 | #define RESET_AXI BIT(3) | |
4bb2bf4c | 116 | #define OUT_ORDER_WR_EN BIT(4) |
37276e00 | 117 | #define HAS_SUB_COMM BIT(5) |
35c1b48d | 118 | #define WR_THROT_EN BIT(6) |
d1b5ef00 | 119 | #define HAS_LEGACY_IVRP_PADDR BIT(7) |
2f317da4 | 120 | #define IOVA_34_EN BIT(8) |
6b717796 CH |
121 | |
122 | #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ | |
123 | ((((pdata)->flags) & (_x)) == (_x)) | |
124 | ||
0df4fabe | 125 | struct mtk_iommu_domain { |
0df4fabe YW |
126 | struct io_pgtable_cfg cfg; |
127 | struct io_pgtable_ops *iop; | |
128 | ||
08500c43 | 129 | struct mtk_iommu_data *data; |
0df4fabe YW |
130 | struct iommu_domain domain; |
131 | }; | |
132 | ||
b65f5016 | 133 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 134 | |
7f37a91d YW |
135 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); |
136 | ||
bfed8731 YW |
137 | #define MTK_IOMMU_TLB_ADDR(iova) ({ \ |
138 | dma_addr_t _addr = iova; \ | |
139 | ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ | |
140 | }) | |
141 | ||
76ce6546 YW |
142 | /* |
143 | * In M4U 4GB mode, the physical address is remapped as below: | |
144 | * | |
145 | * CPU Physical address: | |
146 | * ==================== | |
147 | * | |
148 | * 0 1G 2G 3G 4G 5G | |
149 | * |---A---|---B---|---C---|---D---|---E---| | |
150 | * +--I/O--+------------Memory-------------+ | |
151 | * | |
152 | * IOMMU output physical address: | |
153 | * ============================= | |
154 | * | |
155 | * 4G 5G 6G 7G 8G | |
156 | * |---E---|---B---|---C---|---D---| | |
157 | * +------------Memory-------------+ | |
158 | * | |
159 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
160 | * bit32 of the CPU physical address always is needed to set, and for Region | |
161 | * 'E', the CPU physical address keep as is. | |
162 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
163 | */ | |
b4dad40e | 164 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 165 | |
7c3a2ec0 YW |
166 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
167 | ||
168 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
169 | ||
170 | /* | |
171 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
172 | * for the performance. | |
173 | * | |
174 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
175 | * iommu domain information is recorded. | |
176 | */ | |
177 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
178 | { | |
179 | struct mtk_iommu_data *data; | |
180 | ||
181 | for_each_m4u(data) | |
182 | return data; | |
183 | ||
184 | return NULL; | |
185 | } | |
186 | ||
0df4fabe YW |
187 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
188 | { | |
189 | return container_of(dom, struct mtk_iommu_domain, domain); | |
190 | } | |
191 | ||
0954d61a | 192 | static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) |
0df4fabe | 193 | { |
7c3a2ec0 | 194 | for_each_m4u(data) { |
c0b57581 YW |
195 | if (pm_runtime_get_if_in_use(data->dev) <= 0) |
196 | continue; | |
197 | ||
7c3a2ec0 | 198 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 199 | data->base + data->plat_data->inv_sel_reg); |
7c3a2ec0 YW |
200 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); |
201 | wmb(); /* Make sure the tlb flush all done */ | |
c0b57581 YW |
202 | |
203 | pm_runtime_put(data->dev); | |
7c3a2ec0 | 204 | } |
0df4fabe YW |
205 | } |
206 | ||
1f4fd624 | 207 | static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
0954d61a YW |
208 | size_t granule, |
209 | struct mtk_iommu_data *data) | |
0df4fabe | 210 | { |
c0b57581 | 211 | bool has_pm = !!data->dev->pm_domain; |
1f4fd624 YW |
212 | unsigned long flags; |
213 | int ret; | |
214 | u32 tmp; | |
0df4fabe | 215 | |
7c3a2ec0 | 216 | for_each_m4u(data) { |
c0b57581 YW |
217 | if (has_pm) { |
218 | if (pm_runtime_get_if_in_use(data->dev) <= 0) | |
219 | continue; | |
220 | } | |
221 | ||
1f4fd624 | 222 | spin_lock_irqsave(&data->tlb_lock, flags); |
7c3a2ec0 | 223 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 224 | data->base + data->plat_data->inv_sel_reg); |
0df4fabe | 225 | |
bfed8731 YW |
226 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), |
227 | data->base + REG_MMU_INVLD_START_A); | |
228 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), | |
7c3a2ec0 YW |
229 | data->base + REG_MMU_INVLD_END_A); |
230 | writel_relaxed(F_MMU_INV_RANGE, | |
231 | data->base + REG_MMU_INVALIDATE); | |
98a8f63e | 232 | |
1f4fd624 | 233 | /* tlb sync */ |
7c3a2ec0 | 234 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
c90ae4a6 | 235 | tmp, tmp != 0, 10, 1000); |
7c3a2ec0 YW |
236 | if (ret) { |
237 | dev_warn(data->dev, | |
238 | "Partial TLB flush timed out, falling back to full flush\n"); | |
0954d61a | 239 | mtk_iommu_tlb_flush_all(data); |
7c3a2ec0 YW |
240 | } |
241 | /* Clear the CPE status */ | |
242 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
1f4fd624 | 243 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
c0b57581 YW |
244 | |
245 | if (has_pm) | |
246 | pm_runtime_put(data->dev); | |
0df4fabe | 247 | } |
0df4fabe YW |
248 | } |
249 | ||
0df4fabe YW |
250 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
251 | { | |
252 | struct mtk_iommu_data *data = dev_id; | |
253 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
37276e00 | 254 | unsigned int fault_larb, fault_port, sub_comm = 0; |
ef0f0986 YW |
255 | u32 int_state, regval, va34_32, pa34_32; |
256 | u64 fault_iova, fault_pa; | |
0df4fabe YW |
257 | bool layer, write; |
258 | ||
259 | /* Read error info from registers */ | |
260 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
15a01f4c YW |
261 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
262 | regval = readl_relaxed(data->base + REG_MMU0_INT_ID); | |
263 | fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); | |
264 | fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); | |
265 | } else { | |
266 | regval = readl_relaxed(data->base + REG_MMU1_INT_ID); | |
267 | fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); | |
268 | fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); | |
269 | } | |
0df4fabe YW |
270 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
271 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
ef0f0986 YW |
272 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { |
273 | va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); | |
274 | pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); | |
275 | fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; | |
276 | fault_iova |= (u64)va34_32 << 32; | |
277 | fault_pa |= (u64)pa34_32 << 32; | |
278 | } | |
279 | ||
15a01f4c | 280 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
37276e00 CH |
281 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { |
282 | fault_larb = F_MMU_INT_ID_COMM_ID(regval); | |
283 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); | |
284 | } else { | |
285 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); | |
286 | } | |
287 | fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; | |
b3e5eee7 | 288 | |
0df4fabe YW |
289 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
290 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
291 | dev_err_ratelimited( | |
292 | data->dev, | |
ef0f0986 | 293 | "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n", |
0df4fabe YW |
294 | int_state, fault_iova, fault_pa, fault_larb, fault_port, |
295 | layer, write ? "write" : "read"); | |
296 | } | |
297 | ||
298 | /* Interrupt clear */ | |
299 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
300 | regval |= F_INT_CLR_BIT; | |
301 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
302 | ||
303 | mtk_iommu_tlb_flush_all(data); | |
304 | ||
305 | return IRQ_HANDLED; | |
306 | } | |
307 | ||
308 | static void mtk_iommu_config(struct mtk_iommu_data *data, | |
309 | struct device *dev, bool enable) | |
310 | { | |
0df4fabe YW |
311 | struct mtk_smi_larb_iommu *larb_mmu; |
312 | unsigned int larbid, portid; | |
a9bf2eec | 313 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
58f0d1d5 | 314 | int i; |
0df4fabe | 315 | |
58f0d1d5 RM |
316 | for (i = 0; i < fwspec->num_ids; ++i) { |
317 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
318 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
1ee9feb2 | 319 | larb_mmu = &data->larb_imu[larbid]; |
0df4fabe YW |
320 | |
321 | dev_dbg(dev, "%s iommu port: %d\n", | |
322 | enable ? "enable" : "disable", portid); | |
323 | ||
324 | if (enable) | |
325 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
326 | else | |
327 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
328 | } | |
329 | } | |
330 | ||
4f956c97 YW |
331 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, |
332 | struct mtk_iommu_data *data) | |
0df4fabe | 333 | { |
0df4fabe YW |
334 | dom->cfg = (struct io_pgtable_cfg) { |
335 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
336 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e | 337 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, |
0df4fabe | 338 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
2f317da4 | 339 | .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, |
0df4fabe YW |
340 | .iommu_dev = data->dev, |
341 | }; | |
342 | ||
9bdfe4c1 YW |
343 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) |
344 | dom->cfg.oas = data->enable_4GB ? 33 : 32; | |
345 | else | |
346 | dom->cfg.oas = 35; | |
347 | ||
0df4fabe YW |
348 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); |
349 | if (!dom->iop) { | |
350 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
351 | return -EINVAL; | |
352 | } | |
353 | ||
354 | /* Update our support page sizes bitmap */ | |
d16e0faa | 355 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
b7875eb9 YW |
356 | |
357 | dom->domain.geometry.aperture_start = 0; | |
358 | dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
359 | dom->domain.geometry.force_aperture = true; | |
0df4fabe YW |
360 | return 0; |
361 | } | |
362 | ||
363 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
364 | { | |
365 | struct mtk_iommu_domain *dom; | |
366 | ||
367 | if (type != IOMMU_DOMAIN_DMA) | |
368 | return NULL; | |
369 | ||
370 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
371 | if (!dom) | |
372 | return NULL; | |
373 | ||
4f956c97 YW |
374 | if (iommu_get_dma_cookie(&dom->domain)) { |
375 | kfree(dom); | |
376 | return NULL; | |
377 | } | |
0df4fabe | 378 | |
0df4fabe YW |
379 | return &dom->domain; |
380 | } | |
381 | ||
382 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
383 | { | |
384 | iommu_put_dma_cookie(domain); | |
385 | kfree(to_mtk_domain(domain)); | |
386 | } | |
387 | ||
388 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
389 | struct device *dev) | |
390 | { | |
3524b559 | 391 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 392 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
c0b57581 | 393 | struct device *m4udev = data->dev; |
7f37a91d | 394 | int ret; |
0df4fabe | 395 | |
4b00f5ac | 396 | if (!data) |
0df4fabe YW |
397 | return -ENODEV; |
398 | ||
4f956c97 YW |
399 | if (!dom->data) { |
400 | if (mtk_iommu_domain_finalise(dom, data)) | |
401 | return -ENODEV; | |
402 | dom->data = data; | |
403 | } | |
404 | ||
7f37a91d | 405 | if (!data->m4u_dom) { /* Initialize the M4U HW */ |
c0b57581 YW |
406 | ret = pm_runtime_resume_and_get(m4udev); |
407 | if (ret < 0) | |
408 | return ret; | |
409 | ||
7f37a91d | 410 | ret = mtk_iommu_hw_init(data); |
c0b57581 YW |
411 | if (ret) { |
412 | pm_runtime_put(m4udev); | |
7f37a91d | 413 | return ret; |
c0b57581 | 414 | } |
0df4fabe | 415 | data->m4u_dom = dom; |
d1e5f26f | 416 | writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
4b00f5ac | 417 | data->base + REG_MMU_PT_BASE_ADDR); |
c0b57581 YW |
418 | |
419 | pm_runtime_put(m4udev); | |
7c3a2ec0 YW |
420 | } |
421 | ||
4b00f5ac | 422 | mtk_iommu_config(data, dev, true); |
0df4fabe YW |
423 | return 0; |
424 | } | |
425 | ||
426 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
427 | struct device *dev) | |
428 | { | |
3524b559 | 429 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 430 | |
58f0d1d5 | 431 | if (!data) |
0df4fabe YW |
432 | return; |
433 | ||
0df4fabe YW |
434 | mtk_iommu_config(data, dev, false); |
435 | } | |
436 | ||
437 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
781ca2de | 438 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
0df4fabe YW |
439 | { |
440 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 441 | |
b4dad40e | 442 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
08500c43 | 443 | if (dom->data->enable_4GB) |
b4dad40e YW |
444 | paddr |= BIT_ULL(32); |
445 | ||
60829b4d | 446 | /* Synchronize with the tlb_lock */ |
f34ce7a7 | 447 | return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); |
0df4fabe YW |
448 | } |
449 | ||
450 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
56f8af5e WD |
451 | unsigned long iova, size_t size, |
452 | struct iommu_iotlb_gather *gather) | |
0df4fabe YW |
453 | { |
454 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
f21ae3b1 | 455 | unsigned long end = iova + size - 1; |
0df4fabe | 456 | |
f21ae3b1 YW |
457 | if (gather->start > iova) |
458 | gather->start = iova; | |
459 | if (gather->end < end) | |
460 | gather->end = end; | |
60829b4d | 461 | return dom->iop->unmap(dom->iop, iova, size, gather); |
0df4fabe YW |
462 | } |
463 | ||
56f8af5e WD |
464 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
465 | { | |
08500c43 YW |
466 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
467 | ||
468 | mtk_iommu_tlb_flush_all(dom->data); | |
56f8af5e WD |
469 | } |
470 | ||
471 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
472 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 473 | { |
08500c43 | 474 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
862c3715 | 475 | size_t length = gather->end - gather->start + 1; |
da3cc91b | 476 | |
1f4fd624 | 477 | mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, |
08500c43 | 478 | dom->data); |
4d689b61 RM |
479 | } |
480 | ||
20143451 YW |
481 | static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, |
482 | size_t size) | |
483 | { | |
08500c43 | 484 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
20143451 | 485 | |
08500c43 | 486 | mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); |
20143451 YW |
487 | } |
488 | ||
0df4fabe YW |
489 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
490 | dma_addr_t iova) | |
491 | { | |
492 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe YW |
493 | phys_addr_t pa; |
494 | ||
0df4fabe | 495 | pa = dom->iop->iova_to_phys(dom->iop, iova); |
08500c43 | 496 | if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
b4dad40e | 497 | pa &= ~BIT_ULL(32); |
30e2fccf | 498 | |
0df4fabe YW |
499 | return pa; |
500 | } | |
501 | ||
80e4592a | 502 | static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
0df4fabe | 503 | { |
a9bf2eec | 504 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 505 | struct mtk_iommu_data *data; |
0df4fabe | 506 | |
a9bf2eec | 507 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
80e4592a | 508 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
0df4fabe | 509 | |
3524b559 | 510 | data = dev_iommu_priv_get(dev); |
b16c0170 | 511 | |
80e4592a | 512 | return &data->iommu; |
0df4fabe YW |
513 | } |
514 | ||
80e4592a | 515 | static void mtk_iommu_release_device(struct device *dev) |
0df4fabe | 516 | { |
a9bf2eec | 517 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 518 | |
a9bf2eec | 519 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
520 | return; |
521 | ||
58f0d1d5 | 522 | iommu_fwspec_free(dev); |
0df4fabe YW |
523 | } |
524 | ||
525 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
526 | { | |
7c3a2ec0 | 527 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 528 | |
58f0d1d5 | 529 | if (!data) |
0df4fabe YW |
530 | return ERR_PTR(-ENODEV); |
531 | ||
532 | /* All the client devices are in the same m4u iommu-group */ | |
0df4fabe YW |
533 | if (!data->m4u_group) { |
534 | data->m4u_group = iommu_group_alloc(); | |
535 | if (IS_ERR(data->m4u_group)) | |
536 | dev_err(dev, "Failed to allocate M4U IOMMU group\n"); | |
3a8d40b6 RM |
537 | } else { |
538 | iommu_group_ref_get(data->m4u_group); | |
0df4fabe YW |
539 | } |
540 | return data->m4u_group; | |
541 | } | |
542 | ||
543 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
544 | { | |
0df4fabe YW |
545 | struct platform_device *m4updev; |
546 | ||
547 | if (args->args_count != 1) { | |
548 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
549 | args->args_count); | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
3524b559 | 553 | if (!dev_iommu_priv_get(dev)) { |
0df4fabe YW |
554 | /* Get the m4u device */ |
555 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
556 | if (WARN_ON(!m4updev)) |
557 | return -EINVAL; | |
558 | ||
3524b559 | 559 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
0df4fabe YW |
560 | } |
561 | ||
58f0d1d5 | 562 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
563 | } |
564 | ||
b65f5016 | 565 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe YW |
566 | .domain_alloc = mtk_iommu_domain_alloc, |
567 | .domain_free = mtk_iommu_domain_free, | |
568 | .attach_dev = mtk_iommu_attach_device, | |
569 | .detach_dev = mtk_iommu_detach_device, | |
570 | .map = mtk_iommu_map, | |
571 | .unmap = mtk_iommu_unmap, | |
56f8af5e | 572 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
4d689b61 | 573 | .iotlb_sync = mtk_iommu_iotlb_sync, |
20143451 | 574 | .iotlb_sync_map = mtk_iommu_sync_map, |
0df4fabe | 575 | .iova_to_phys = mtk_iommu_iova_to_phys, |
80e4592a JR |
576 | .probe_device = mtk_iommu_probe_device, |
577 | .release_device = mtk_iommu_release_device, | |
0df4fabe YW |
578 | .device_group = mtk_iommu_device_group, |
579 | .of_xlate = mtk_iommu_of_xlate, | |
580 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
581 | }; | |
582 | ||
583 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
584 | { | |
585 | u32 regval; | |
586 | int ret; | |
587 | ||
588 | ret = clk_prepare_enable(data->bclk); | |
589 | if (ret) { | |
590 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
591 | return ret; | |
592 | } | |
593 | ||
86444413 | 594 | if (data->plat_data->m4u_plat == M4U_MT8173) { |
acb3c92a YW |
595 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
596 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
86444413 CH |
597 | } else { |
598 | regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); | |
599 | regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; | |
600 | } | |
0df4fabe YW |
601 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
602 | ||
603 | regval = F_L2_MULIT_HIT_EN | | |
604 | F_TABLE_WALK_FAULT_INT_EN | | |
605 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
606 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
607 | F_PREFETCH_FIFO_ERR_INT_EN | | |
608 | F_MISS_FIFO_ERR_INT_EN; | |
609 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
610 | ||
611 | regval = F_INT_TRANSLATION_FAULT | | |
612 | F_INT_MAIN_MULTI_HIT_FAULT | | |
613 | F_INT_INVALID_PA_FAULT | | |
614 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
615 | F_INT_TLB_MISS_FAULT | | |
616 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
617 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
618 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
619 | ||
d1b5ef00 | 620 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) |
70ca608b YW |
621 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); |
622 | else | |
623 | regval = lower_32_bits(data->protect_base) | | |
624 | upper_32_bits(data->protect_base); | |
625 | writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); | |
626 | ||
6b717796 CH |
627 | if (data->enable_4GB && |
628 | MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { | |
30e2fccf YW |
629 | /* |
630 | * If 4GB mode is enabled, the validate PA range is from | |
631 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
632 | */ | |
633 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
634 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
635 | } | |
0df4fabe | 636 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
35c1b48d CH |
637 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { |
638 | /* write command throttling mode */ | |
639 | regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); | |
640 | regval &= ~F_MMU_WR_THROT_DIS_MASK; | |
641 | writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); | |
642 | } | |
e6dec923 | 643 | |
6b717796 | 644 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { |
75eed350 | 645 | /* The register is called STANDARD_AXI_MODE in this case */ |
4bb2bf4c CH |
646 | regval = 0; |
647 | } else { | |
648 | regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); | |
649 | regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; | |
650 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) | |
651 | regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; | |
75eed350 | 652 | } |
4bb2bf4c | 653 | writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
654 | |
655 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
656 | dev_name(data->dev), (void *)data)) { | |
657 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
658 | clk_disable_unprepare(data->bclk); | |
659 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
660 | return -ENODEV; | |
661 | } | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
0df4fabe YW |
666 | static const struct component_master_ops mtk_iommu_com_ops = { |
667 | .bind = mtk_iommu_bind, | |
668 | .unbind = mtk_iommu_unbind, | |
669 | }; | |
670 | ||
671 | static int mtk_iommu_probe(struct platform_device *pdev) | |
672 | { | |
673 | struct mtk_iommu_data *data; | |
674 | struct device *dev = &pdev->dev; | |
baf94e6e YW |
675 | struct device_node *larbnode, *smicomm_node; |
676 | struct platform_device *plarbdev; | |
677 | struct device_link *link; | |
0df4fabe | 678 | struct resource *res; |
b16c0170 | 679 | resource_size_t ioaddr; |
0df4fabe | 680 | struct component_match *match = NULL; |
c2c59456 | 681 | struct regmap *infracfg; |
0df4fabe | 682 | void *protect; |
0b6c0ad3 | 683 | int i, larb_nr, ret; |
c2c59456 MC |
684 | u32 val; |
685 | char *p; | |
0df4fabe YW |
686 | |
687 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
688 | if (!data) | |
689 | return -ENOMEM; | |
690 | data->dev = dev; | |
cecdce9d | 691 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
692 | |
693 | /* Protect memory. HW will access here while translation fault.*/ | |
694 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
695 | if (!protect) | |
696 | return -ENOMEM; | |
697 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
698 | ||
c2c59456 MC |
699 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { |
700 | switch (data->plat_data->m4u_plat) { | |
701 | case M4U_MT2712: | |
702 | p = "mediatek,mt2712-infracfg"; | |
703 | break; | |
704 | case M4U_MT8173: | |
705 | p = "mediatek,mt8173-infracfg"; | |
706 | break; | |
707 | default: | |
708 | p = NULL; | |
709 | } | |
710 | ||
711 | infracfg = syscon_regmap_lookup_by_compatible(p); | |
712 | ||
713 | if (IS_ERR(infracfg)) | |
714 | return PTR_ERR(infracfg); | |
715 | ||
716 | ret = regmap_read(infracfg, REG_INFRA_MISC, &val); | |
717 | if (ret) | |
718 | return ret; | |
719 | data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); | |
720 | } | |
01e23c93 | 721 | |
0df4fabe YW |
722 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
723 | data->base = devm_ioremap_resource(dev, res); | |
724 | if (IS_ERR(data->base)) | |
725 | return PTR_ERR(data->base); | |
b16c0170 | 726 | ioaddr = res->start; |
0df4fabe YW |
727 | |
728 | data->irq = platform_get_irq(pdev, 0); | |
729 | if (data->irq < 0) | |
730 | return data->irq; | |
731 | ||
6b717796 | 732 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { |
2aa4c259 YW |
733 | data->bclk = devm_clk_get(dev, "bclk"); |
734 | if (IS_ERR(data->bclk)) | |
735 | return PTR_ERR(data->bclk); | |
736 | } | |
0df4fabe YW |
737 | |
738 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
739 | "mediatek,larbs", NULL); | |
740 | if (larb_nr < 0) | |
741 | return larb_nr; | |
0df4fabe YW |
742 | |
743 | for (i = 0; i < larb_nr; i++) { | |
e6dec923 | 744 | u32 id; |
0df4fabe YW |
745 | |
746 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
747 | if (!larbnode) | |
748 | return -EINVAL; | |
749 | ||
1eb8e4e2 WY |
750 | if (!of_device_is_available(larbnode)) { |
751 | of_node_put(larbnode); | |
0df4fabe | 752 | continue; |
1eb8e4e2 | 753 | } |
0df4fabe | 754 | |
e6dec923 YW |
755 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
756 | if (ret)/* The id is consecutive if there is no this property */ | |
757 | id = i; | |
758 | ||
0df4fabe | 759 | plarbdev = of_find_device_by_node(larbnode); |
1eb8e4e2 WY |
760 | if (!plarbdev) { |
761 | of_node_put(larbnode); | |
e6dec923 | 762 | return -EPROBE_DEFER; |
1eb8e4e2 | 763 | } |
1ee9feb2 | 764 | data->larb_imu[id].dev = &plarbdev->dev; |
0df4fabe | 765 | |
00c7c81f RK |
766 | component_match_add_release(dev, &match, release_of, |
767 | compare_of, larbnode); | |
0df4fabe YW |
768 | } |
769 | ||
baf94e6e YW |
770 | /* Get smi-common dev from the last larb. */ |
771 | smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); | |
772 | if (!smicomm_node) | |
773 | return -EINVAL; | |
774 | ||
775 | plarbdev = of_find_device_by_node(smicomm_node); | |
776 | of_node_put(smicomm_node); | |
777 | data->smicomm_dev = &plarbdev->dev; | |
778 | ||
c0b57581 YW |
779 | pm_runtime_enable(dev); |
780 | ||
baf94e6e YW |
781 | link = device_link_add(data->smicomm_dev, dev, |
782 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); | |
783 | if (!link) { | |
784 | dev_err(dev, "Unable link %s.\n", dev_name(data->smicomm_dev)); | |
c0b57581 | 785 | goto out_runtime_disable; |
baf94e6e YW |
786 | } |
787 | ||
0df4fabe YW |
788 | platform_set_drvdata(pdev, data); |
789 | ||
b16c0170 JR |
790 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
791 | "mtk-iommu.%pa", &ioaddr); | |
792 | if (ret) | |
baf94e6e | 793 | goto out_link_remove; |
b16c0170 JR |
794 | |
795 | iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); | |
796 | iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); | |
797 | ||
798 | ret = iommu_device_register(&data->iommu); | |
799 | if (ret) | |
986d9ec5 | 800 | goto out_sysfs_remove; |
b16c0170 | 801 | |
da3cc91b | 802 | spin_lock_init(&data->tlb_lock); |
7c3a2ec0 YW |
803 | list_add_tail(&data->list, &m4ulist); |
804 | ||
986d9ec5 YW |
805 | if (!iommu_present(&platform_bus_type)) { |
806 | ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
807 | if (ret) | |
808 | goto out_list_del; | |
809 | } | |
0df4fabe | 810 | |
986d9ec5 YW |
811 | ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
812 | if (ret) | |
813 | goto out_bus_set_null; | |
814 | return ret; | |
815 | ||
816 | out_bus_set_null: | |
817 | bus_set_iommu(&platform_bus_type, NULL); | |
818 | out_list_del: | |
819 | list_del(&data->list); | |
820 | iommu_device_unregister(&data->iommu); | |
821 | out_sysfs_remove: | |
822 | iommu_device_sysfs_remove(&data->iommu); | |
baf94e6e YW |
823 | out_link_remove: |
824 | device_link_remove(data->smicomm_dev, dev); | |
c0b57581 YW |
825 | out_runtime_disable: |
826 | pm_runtime_disable(dev); | |
986d9ec5 | 827 | return ret; |
0df4fabe YW |
828 | } |
829 | ||
830 | static int mtk_iommu_remove(struct platform_device *pdev) | |
831 | { | |
832 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
833 | ||
b16c0170 JR |
834 | iommu_device_sysfs_remove(&data->iommu); |
835 | iommu_device_unregister(&data->iommu); | |
836 | ||
0df4fabe YW |
837 | if (iommu_present(&platform_bus_type)) |
838 | bus_set_iommu(&platform_bus_type, NULL); | |
839 | ||
0df4fabe | 840 | clk_disable_unprepare(data->bclk); |
baf94e6e | 841 | device_link_remove(data->smicomm_dev, &pdev->dev); |
c0b57581 | 842 | pm_runtime_disable(&pdev->dev); |
0df4fabe YW |
843 | devm_free_irq(&pdev->dev, data->irq, data); |
844 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
845 | return 0; | |
846 | } | |
847 | ||
34665c79 | 848 | static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) |
0df4fabe YW |
849 | { |
850 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
851 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
852 | void __iomem *base = data->base; | |
853 | ||
35c1b48d | 854 | reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 855 | reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
856 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
857 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
858 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
859 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 860 | reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); |
b9475b34 | 861 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
6254b64f | 862 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
863 | return 0; |
864 | } | |
865 | ||
34665c79 | 866 | static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) |
0df4fabe YW |
867 | { |
868 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
869 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
907ba6a1 | 870 | struct mtk_iommu_domain *m4u_dom = data->m4u_dom; |
0df4fabe | 871 | void __iomem *base = data->base; |
6254b64f | 872 | int ret; |
0df4fabe | 873 | |
c0b57581 YW |
874 | /* Avoid first resume to affect the default value of registers below. */ |
875 | if (!m4u_dom) | |
876 | return 0; | |
6254b64f YW |
877 | ret = clk_prepare_enable(data->bclk); |
878 | if (ret) { | |
879 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
880 | return ret; | |
881 | } | |
35c1b48d | 882 | writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 883 | writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
884 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
885 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
886 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
887 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 888 | writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); |
b9475b34 | 889 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
c0b57581 | 890 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); |
0df4fabe YW |
891 | return 0; |
892 | } | |
893 | ||
e6dec923 | 894 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
34665c79 YW |
895 | SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) |
896 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
897 | pm_runtime_force_resume) | |
0df4fabe YW |
898 | }; |
899 | ||
cecdce9d YW |
900 | static const struct mtk_iommu_plat_data mt2712_data = { |
901 | .m4u_plat = M4U_MT2712, | |
6b717796 | 902 | .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, |
b053bc71 | 903 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 904 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, |
cecdce9d YW |
905 | }; |
906 | ||
068c86e9 CH |
907 | static const struct mtk_iommu_plat_data mt6779_data = { |
908 | .m4u_plat = M4U_MT6779, | |
909 | .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, | |
910 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
911 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, | |
cecdce9d YW |
912 | }; |
913 | ||
3c213562 FP |
914 | static const struct mtk_iommu_plat_data mt8167_data = { |
915 | .m4u_plat = M4U_MT8167, | |
916 | .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, | |
917 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, | |
918 | .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ | |
919 | }; | |
920 | ||
cecdce9d YW |
921 | static const struct mtk_iommu_plat_data mt8173_data = { |
922 | .m4u_plat = M4U_MT8173, | |
d1b5ef00 FP |
923 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
924 | HAS_LEGACY_IVRP_PADDR, | |
b053bc71 | 925 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 926 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ |
cecdce9d YW |
927 | }; |
928 | ||
907ba6a1 YW |
929 | static const struct mtk_iommu_plat_data mt8183_data = { |
930 | .m4u_plat = M4U_MT8183, | |
6b717796 | 931 | .flags = RESET_AXI, |
b053bc71 | 932 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
37276e00 | 933 | .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, |
907ba6a1 YW |
934 | }; |
935 | ||
0df4fabe | 936 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d | 937 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
068c86e9 | 938 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
3c213562 | 939 | { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, |
cecdce9d | 940 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
907ba6a1 | 941 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
0df4fabe YW |
942 | {} |
943 | }; | |
944 | ||
945 | static struct platform_driver mtk_iommu_driver = { | |
946 | .probe = mtk_iommu_probe, | |
947 | .remove = mtk_iommu_remove, | |
948 | .driver = { | |
949 | .name = "mtk-iommu", | |
f53dd978 | 950 | .of_match_table = mtk_iommu_of_ids, |
0df4fabe YW |
951 | .pm = &mtk_iommu_pm_ops, |
952 | } | |
953 | }; | |
954 | ||
e6dec923 | 955 | static int __init mtk_iommu_init(void) |
0df4fabe YW |
956 | { |
957 | int ret; | |
0df4fabe YW |
958 | |
959 | ret = platform_driver_register(&mtk_iommu_driver); | |
e6dec923 YW |
960 | if (ret != 0) |
961 | pr_err("Failed to register MTK IOMMU driver\n"); | |
0df4fabe | 962 | |
e6dec923 | 963 | return ret; |
0df4fabe YW |
964 | } |
965 | ||
e6dec923 | 966 | subsys_initcall(mtk_iommu_init) |