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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe | 5 | */ |
ef0f0986 | 6 | #include <linux/bitfield.h> |
0df4fabe YW |
7 | #include <linux/bug.h> |
8 | #include <linux/clk.h> | |
9 | #include <linux/component.h> | |
10 | #include <linux/device.h> | |
803cf9e5 | 11 | #include <linux/dma-direct.h> |
0df4fabe YW |
12 | #include <linux/err.h> |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/iommu.h> | |
16 | #include <linux/iopoll.h> | |
6a513de3 | 17 | #include <linux/io-pgtable.h> |
0df4fabe | 18 | #include <linux/list.h> |
c2c59456 | 19 | #include <linux/mfd/syscon.h> |
18d8c74e | 20 | #include <linux/module.h> |
0df4fabe | 21 | #include <linux/of_address.h> |
0df4fabe YW |
22 | #include <linux/of_irq.h> |
23 | #include <linux/of_platform.h> | |
e7629070 | 24 | #include <linux/pci.h> |
0df4fabe | 25 | #include <linux/platform_device.h> |
baf94e6e | 26 | #include <linux/pm_runtime.h> |
c2c59456 | 27 | #include <linux/regmap.h> |
0df4fabe YW |
28 | #include <linux/slab.h> |
29 | #include <linux/spinlock.h> | |
c2c59456 | 30 | #include <linux/soc/mediatek/infracfg.h> |
0df4fabe | 31 | #include <asm/barrier.h> |
0df4fabe YW |
32 | #include <soc/mediatek/smi.h> |
33 | ||
6a513de3 | 34 | #include <dt-bindings/memory/mtk-memory-port.h> |
0df4fabe YW |
35 | |
36 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
37 | ||
38 | #define REG_MMU_INVALIDATE 0x020 | |
39 | #define F_ALL_INVLD 0x2 | |
40 | #define F_MMU_INV_RANGE 0x1 | |
41 | ||
42 | #define REG_MMU_INVLD_START_A 0x024 | |
43 | #define REG_MMU_INVLD_END_A 0x028 | |
44 | ||
068c86e9 | 45 | #define REG_MMU_INV_SEL_GEN2 0x02c |
b053bc71 | 46 | #define REG_MMU_INV_SEL_GEN1 0x038 |
0df4fabe YW |
47 | #define F_INVLD_EN0 BIT(0) |
48 | #define F_INVLD_EN1 BIT(1) | |
49 | ||
75eed350 | 50 | #define REG_MMU_MISC_CTRL 0x048 |
4bb2bf4c CH |
51 | #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) |
52 | #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) | |
53 | ||
0df4fabe | 54 | #define REG_MMU_DCM_DIS 0x050 |
9a87005e YW |
55 | #define F_MMU_DCM BIT(8) |
56 | ||
35c1b48d CH |
57 | #define REG_MMU_WR_LEN_CTRL 0x054 |
58 | #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) | |
0df4fabe YW |
59 | |
60 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 61 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 62 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 63 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
64 | |
65 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 66 | |
30e2fccf YW |
67 | #define REG_MMU_VLD_PA_RNG 0x118 |
68 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
69 | |
70 | #define REG_MMU_INT_CONTROL0 0x120 | |
71 | #define F_L2_MULIT_HIT_EN BIT(0) | |
72 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
73 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
74 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
75 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
76 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
77 | #define F_INT_CLR_BIT BIT(12) | |
78 | ||
79 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
80 | /* mmu0 | mmu1 */ |
81 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
82 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
83 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
84 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
85 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
86 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
87 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
88 | |
89 | #define REG_MMU_CPE_DONE 0x12C | |
90 | ||
91 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
92 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
93 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 94 | |
15a01f4c | 95 | #define REG_MMU0_FAULT_VA 0x13c |
ef0f0986 YW |
96 | #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) |
97 | #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) | |
98 | #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) | |
0df4fabe YW |
99 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
100 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
101 | ||
15a01f4c YW |
102 | #define REG_MMU0_INVLD_PA 0x140 |
103 | #define REG_MMU1_FAULT_VA 0x144 | |
104 | #define REG_MMU1_INVLD_PA 0x148 | |
105 | #define REG_MMU0_INT_ID 0x150 | |
106 | #define REG_MMU1_INT_ID 0x154 | |
37276e00 CH |
107 | #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
108 | #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) | |
9ec30c09 YW |
109 | #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) |
110 | #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) | |
65df7d82 | 111 | /* Macro for 5 bits length port ID field (default) */ |
15a01f4c YW |
112 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
113 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
65df7d82 FP |
114 | /* Macro for 6 bits length port ID field */ |
115 | #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) | |
116 | #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) | |
0df4fabe | 117 | |
829316b3 | 118 | #define MTK_PROTECT_PA_ALIGN 256 |
42d57fc5 | 119 | #define MTK_IOMMU_BANK_SZ 0x1000 |
0df4fabe | 120 | |
f9b8c9b2 YW |
121 | #define PERICFG_IOMMU_1 0x714 |
122 | ||
6b717796 CH |
123 | #define HAS_4GB_MODE BIT(0) |
124 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
125 | #define HAS_BCLK BIT(1) | |
126 | #define HAS_VLD_PA_RNG BIT(2) | |
127 | #define RESET_AXI BIT(3) | |
4bb2bf4c | 128 | #define OUT_ORDER_WR_EN BIT(4) |
9ec30c09 YW |
129 | #define HAS_SUB_COMM_2BITS BIT(5) |
130 | #define HAS_SUB_COMM_3BITS BIT(6) | |
131 | #define WR_THROT_EN BIT(7) | |
132 | #define HAS_LEGACY_IVRP_PADDR BIT(8) | |
133 | #define IOVA_34_EN BIT(9) | |
134 | #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ | |
135 | #define DCM_DISABLE BIT(11) | |
136 | #define STD_AXI_MODE BIT(12) /* For non MM iommu */ | |
8cd1e619 YW |
137 | /* 2 bits: iommu type */ |
138 | #define MTK_IOMMU_TYPE_MM (0x0 << 13) | |
139 | #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) | |
140 | #define MTK_IOMMU_TYPE_MASK (0x3 << 13) | |
6077c7e5 YW |
141 | /* PM and clock always on. e.g. infra iommu */ |
142 | #define PM_CLK_AO BIT(15) | |
e7629070 | 143 | #define IFA_IOMMU_PCIE_SUPPORT BIT(16) |
301c3ca1 | 144 | #define PGTABLE_PA_35_EN BIT(17) |
86580ec9 | 145 | #define TF_PORT_TO_ADDR_MT8173 BIT(18) |
65df7d82 | 146 | #define INT_ID_PORT_WIDTH_6 BIT(19) |
6b717796 | 147 | |
8cd1e619 YW |
148 | #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ |
149 | ((((pdata)->flags) & (mask)) == (_x)) | |
150 | ||
151 | #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) | |
152 | #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ | |
153 | MTK_IOMMU_TYPE_MASK) | |
6b717796 | 154 | |
d2e9a110 YW |
155 | #define MTK_INVALID_LARBID MTK_LARB_NR_MAX |
156 | ||
9485a04a YW |
157 | #define MTK_LARB_COM_MAX 8 |
158 | #define MTK_LARB_SUBCOM_MAX 8 | |
159 | ||
160 | #define MTK_IOMMU_GROUP_MAX 8 | |
99ca0228 | 161 | #define MTK_IOMMU_BANK_MAX 5 |
9485a04a YW |
162 | |
163 | enum mtk_iommu_plat { | |
164 | M4U_MT2712, | |
165 | M4U_MT6779, | |
717ec15e | 166 | M4U_MT6795, |
9485a04a YW |
167 | M4U_MT8167, |
168 | M4U_MT8173, | |
169 | M4U_MT8183, | |
e8d7ccaa | 170 | M4U_MT8186, |
9485a04a YW |
171 | M4U_MT8192, |
172 | M4U_MT8195, | |
3cd0e4a3 | 173 | M4U_MT8365, |
9485a04a YW |
174 | }; |
175 | ||
176 | struct mtk_iommu_iova_region { | |
177 | dma_addr_t iova_base; | |
178 | unsigned long long size; | |
179 | }; | |
180 | ||
6a513de3 YW |
181 | struct mtk_iommu_suspend_reg { |
182 | u32 misc_ctrl; | |
183 | u32 dcm_dis; | |
184 | u32 ctrl_reg; | |
6a513de3 YW |
185 | u32 vld_pa_rng; |
186 | u32 wr_len_ctrl; | |
d7127de1 YW |
187 | |
188 | u32 int_control[MTK_IOMMU_BANK_MAX]; | |
189 | u32 int_main_control[MTK_IOMMU_BANK_MAX]; | |
190 | u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; | |
6a513de3 YW |
191 | }; |
192 | ||
9485a04a YW |
193 | struct mtk_iommu_plat_data { |
194 | enum mtk_iommu_plat m4u_plat; | |
195 | u32 flags; | |
196 | u32 inv_sel_reg; | |
197 | ||
198 | char *pericfg_comp_str; | |
199 | struct list_head *hw_list; | |
200 | unsigned int iova_region_nr; | |
201 | const struct mtk_iommu_iova_region *iova_region; | |
99ca0228 YW |
202 | |
203 | u8 banks_num; | |
204 | bool banks_enable[MTK_IOMMU_BANK_MAX]; | |
57fb481f | 205 | unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; |
9485a04a YW |
206 | unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; |
207 | }; | |
208 | ||
99ca0228 | 209 | struct mtk_iommu_bank_data { |
9485a04a YW |
210 | void __iomem *base; |
211 | int irq; | |
99ca0228 YW |
212 | u8 id; |
213 | struct device *parent_dev; | |
214 | struct mtk_iommu_data *parent_data; | |
215 | spinlock_t tlb_lock; /* lock for tlb range flush */ | |
216 | struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ | |
217 | }; | |
218 | ||
219 | struct mtk_iommu_data { | |
9485a04a YW |
220 | struct device *dev; |
221 | struct clk *bclk; | |
222 | phys_addr_t protect_base; /* protect memory base */ | |
223 | struct mtk_iommu_suspend_reg reg; | |
9485a04a YW |
224 | struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; |
225 | bool enable_4GB; | |
9485a04a YW |
226 | |
227 | struct iommu_device iommu; | |
228 | const struct mtk_iommu_plat_data *plat_data; | |
229 | struct device *smicomm_dev; | |
230 | ||
99ca0228 | 231 | struct mtk_iommu_bank_data *bank; |
9485a04a | 232 | struct regmap *pericfg; |
9485a04a YW |
233 | struct mutex mutex; /* Protect m4u_group/m4u_dom above */ |
234 | ||
235 | /* | |
236 | * In the sharing pgtable case, list data->list to the global list like m4ulist. | |
237 | * In the non-sharing pgtable case, list data->list to the itself hw_list_head. | |
238 | */ | |
239 | struct list_head *hw_list; | |
240 | struct list_head hw_list_head; | |
241 | struct list_head list; | |
242 | struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; | |
243 | }; | |
244 | ||
0df4fabe | 245 | struct mtk_iommu_domain { |
0df4fabe YW |
246 | struct io_pgtable_cfg cfg; |
247 | struct io_pgtable_ops *iop; | |
248 | ||
99ca0228 | 249 | struct mtk_iommu_bank_data *bank; |
0df4fabe | 250 | struct iommu_domain domain; |
ddf67a87 YW |
251 | |
252 | struct mutex mutex; /* Protect "data" in this structure */ | |
0df4fabe YW |
253 | }; |
254 | ||
9485a04a YW |
255 | static int mtk_iommu_bind(struct device *dev) |
256 | { | |
257 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
258 | ||
259 | return component_bind_all(dev, &data->larb_imu); | |
260 | } | |
261 | ||
262 | static void mtk_iommu_unbind(struct device *dev) | |
263 | { | |
264 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
265 | ||
266 | component_unbind_all(dev, &data->larb_imu); | |
267 | } | |
268 | ||
b65f5016 | 269 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 270 | |
e24453e1 | 271 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); |
7f37a91d | 272 | |
bfed8731 YW |
273 | #define MTK_IOMMU_TLB_ADDR(iova) ({ \ |
274 | dma_addr_t _addr = iova; \ | |
275 | ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ | |
276 | }) | |
277 | ||
76ce6546 YW |
278 | /* |
279 | * In M4U 4GB mode, the physical address is remapped as below: | |
280 | * | |
281 | * CPU Physical address: | |
282 | * ==================== | |
283 | * | |
284 | * 0 1G 2G 3G 4G 5G | |
285 | * |---A---|---B---|---C---|---D---|---E---| | |
286 | * +--I/O--+------------Memory-------------+ | |
287 | * | |
288 | * IOMMU output physical address: | |
289 | * ============================= | |
290 | * | |
291 | * 4G 5G 6G 7G 8G | |
292 | * |---E---|---B---|---C---|---D---| | |
293 | * +------------Memory-------------+ | |
294 | * | |
295 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
296 | * bit32 of the CPU physical address always is needed to set, and for Region | |
297 | * 'E', the CPU physical address keep as is. | |
298 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
299 | */ | |
b4dad40e | 300 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 301 | |
7c3a2ec0 YW |
302 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
303 | ||
9e3a2a64 | 304 | #define for_each_m4u(data, head) list_for_each_entry(data, head, list) |
7c3a2ec0 | 305 | |
585e58f4 YW |
306 | static const struct mtk_iommu_iova_region single_domain[] = { |
307 | {.iova_base = 0, .size = SZ_4G}, | |
308 | }; | |
309 | ||
9e3489e0 | 310 | static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { |
129a3b88 | 311 | { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ |
9e3489e0 | 312 | #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) |
129a3b88 YW |
313 | { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ |
314 | { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ | |
315 | { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ | |
316 | ||
9e3489e0 YW |
317 | { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ |
318 | { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ | |
319 | #endif | |
320 | }; | |
321 | ||
9e3a2a64 YW |
322 | /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ |
323 | static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) | |
7c3a2ec0 | 324 | { |
9e3a2a64 | 325 | return list_first_entry(hwlist, struct mtk_iommu_data, list); |
7c3a2ec0 YW |
326 | } |
327 | ||
0df4fabe YW |
328 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
329 | { | |
330 | return container_of(dom, struct mtk_iommu_domain, domain); | |
331 | } | |
332 | ||
0954d61a | 333 | static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) |
0df4fabe | 334 | { |
99ca0228 YW |
335 | /* Tlb flush all always is in bank0. */ |
336 | struct mtk_iommu_bank_data *bank = &data->bank[0]; | |
337 | void __iomem *base = bank->base; | |
15672b6d | 338 | unsigned long flags; |
c0b57581 | 339 | |
99ca0228 | 340 | spin_lock_irqsave(&bank->tlb_lock, flags); |
887cf6a7 YW |
341 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); |
342 | writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); | |
17224e08 | 343 | wmb(); /* Make sure the tlb flush all done */ |
99ca0228 | 344 | spin_unlock_irqrestore(&bank->tlb_lock, flags); |
0df4fabe YW |
345 | } |
346 | ||
1f4fd624 | 347 | static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
99ca0228 | 348 | struct mtk_iommu_bank_data *bank) |
0df4fabe | 349 | { |
99ca0228 YW |
350 | struct list_head *head = bank->parent_data->hw_list; |
351 | struct mtk_iommu_bank_data *curbank; | |
352 | struct mtk_iommu_data *data; | |
6077c7e5 | 353 | bool check_pm_status; |
1f4fd624 | 354 | unsigned long flags; |
887cf6a7 | 355 | void __iomem *base; |
1f4fd624 YW |
356 | int ret; |
357 | u32 tmp; | |
0df4fabe | 358 | |
9e3a2a64 | 359 | for_each_m4u(data, head) { |
6077c7e5 YW |
360 | /* |
361 | * To avoid resume the iommu device frequently when the iommu device | |
362 | * is not active, it doesn't always call pm_runtime_get here, then tlb | |
363 | * flush depends on the tlb flush all in the runtime resume. | |
364 | * | |
365 | * There are 2 special cases: | |
366 | * | |
367 | * Case1: The iommu dev doesn't have power domain but has bclk. This case | |
368 | * should also avoid the tlb flush while the dev is not active to mute | |
369 | * the tlb timeout log. like mt8173. | |
370 | * | |
371 | * Case2: The power/clock of infra iommu is always on, and it doesn't | |
372 | * have the device link with the master devices. This case should avoid | |
373 | * the PM status check. | |
374 | */ | |
375 | check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); | |
376 | ||
377 | if (check_pm_status) { | |
378 | if (pm_runtime_get_if_in_use(data->dev) <= 0) | |
379 | continue; | |
380 | } | |
c0b57581 | 381 | |
99ca0228 YW |
382 | curbank = &data->bank[bank->id]; |
383 | base = curbank->base; | |
887cf6a7 | 384 | |
99ca0228 | 385 | spin_lock_irqsave(&curbank->tlb_lock, flags); |
7c3a2ec0 | 386 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
887cf6a7 | 387 | base + data->plat_data->inv_sel_reg); |
0df4fabe | 388 | |
887cf6a7 | 389 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); |
bfed8731 | 390 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), |
887cf6a7 YW |
391 | base + REG_MMU_INVLD_END_A); |
392 | writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); | |
98a8f63e | 393 | |
1f4fd624 | 394 | /* tlb sync */ |
887cf6a7 | 395 | ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, |
c90ae4a6 | 396 | tmp, tmp != 0, 10, 1000); |
15672b6d YW |
397 | |
398 | /* Clear the CPE status */ | |
887cf6a7 | 399 | writel_relaxed(0, base + REG_MMU_CPE_DONE); |
99ca0228 | 400 | spin_unlock_irqrestore(&curbank->tlb_lock, flags); |
15672b6d | 401 | |
7c3a2ec0 YW |
402 | if (ret) { |
403 | dev_warn(data->dev, | |
404 | "Partial TLB flush timed out, falling back to full flush\n"); | |
0954d61a | 405 | mtk_iommu_tlb_flush_all(data); |
7c3a2ec0 | 406 | } |
c0b57581 | 407 | |
6077c7e5 YW |
408 | if (check_pm_status) |
409 | pm_runtime_put(data->dev); | |
0df4fabe | 410 | } |
0df4fabe YW |
411 | } |
412 | ||
0df4fabe YW |
413 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
414 | { | |
99ca0228 YW |
415 | struct mtk_iommu_bank_data *bank = dev_id; |
416 | struct mtk_iommu_data *data = bank->parent_data; | |
417 | struct mtk_iommu_domain *dom = bank->m4u_dom; | |
d2e9a110 | 418 | unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; |
ef0f0986 | 419 | u32 int_state, regval, va34_32, pa34_32; |
887cf6a7 | 420 | const struct mtk_iommu_plat_data *plat_data = data->plat_data; |
99ca0228 | 421 | void __iomem *base = bank->base; |
ef0f0986 | 422 | u64 fault_iova, fault_pa; |
0df4fabe YW |
423 | bool layer, write; |
424 | ||
425 | /* Read error info from registers */ | |
887cf6a7 | 426 | int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); |
15a01f4c | 427 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
887cf6a7 YW |
428 | regval = readl_relaxed(base + REG_MMU0_INT_ID); |
429 | fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); | |
430 | fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); | |
15a01f4c | 431 | } else { |
887cf6a7 YW |
432 | regval = readl_relaxed(base + REG_MMU1_INT_ID); |
433 | fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); | |
434 | fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); | |
15a01f4c | 435 | } |
0df4fabe YW |
436 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
437 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
887cf6a7 | 438 | if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { |
ef0f0986 | 439 | va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); |
ef0f0986 YW |
440 | fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; |
441 | fault_iova |= (u64)va34_32 << 32; | |
ef0f0986 | 442 | } |
82e51771 YW |
443 | pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); |
444 | fault_pa |= (u64)pa34_32 << 32; | |
ef0f0986 | 445 | |
887cf6a7 | 446 | if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { |
887cf6a7 | 447 | if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { |
d2e9a110 YW |
448 | fault_larb = F_MMU_INT_ID_COMM_ID(regval); |
449 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); | |
65df7d82 | 450 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
887cf6a7 | 451 | } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { |
d2e9a110 YW |
452 | fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); |
453 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); | |
65df7d82 FP |
454 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
455 | } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { | |
456 | fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval); | |
457 | fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval); | |
d2e9a110 | 458 | } else { |
65df7d82 | 459 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
d2e9a110 YW |
460 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); |
461 | } | |
462 | fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; | |
37276e00 | 463 | } |
b3e5eee7 | 464 | |
00ef8885 | 465 | if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, |
0df4fabe YW |
466 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { |
467 | dev_err_ratelimited( | |
99ca0228 | 468 | bank->parent_dev, |
f9b8c9b2 YW |
469 | "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", |
470 | int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, | |
0df4fabe YW |
471 | layer, write ? "write" : "read"); |
472 | } | |
473 | ||
474 | /* Interrupt clear */ | |
887cf6a7 | 475 | regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); |
0df4fabe | 476 | regval |= F_INT_CLR_BIT; |
887cf6a7 | 477 | writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); |
0df4fabe YW |
478 | |
479 | mtk_iommu_tlb_flush_all(data); | |
480 | ||
481 | return IRQ_HANDLED; | |
482 | } | |
483 | ||
57fb481f YW |
484 | static unsigned int mtk_iommu_get_bank_id(struct device *dev, |
485 | const struct mtk_iommu_plat_data *plat_data) | |
486 | { | |
487 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); | |
488 | unsigned int i, portmsk = 0, bankid = 0; | |
489 | ||
490 | if (plat_data->banks_num == 1) | |
491 | return bankid; | |
492 | ||
493 | for (i = 0; i < fwspec->num_ids; i++) | |
494 | portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); | |
495 | ||
496 | for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { | |
497 | if (!plat_data->banks_enable[i]) | |
498 | continue; | |
499 | ||
500 | if (portmsk & plat_data->banks_portmsk[i]) { | |
501 | bankid = i; | |
502 | break; | |
503 | } | |
504 | } | |
505 | return bankid; /* default is 0 */ | |
506 | } | |
507 | ||
d72e0ff5 YW |
508 | static int mtk_iommu_get_iova_region_id(struct device *dev, |
509 | const struct mtk_iommu_plat_data *plat_data) | |
803cf9e5 YW |
510 | { |
511 | const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; | |
512 | const struct bus_dma_region *dma_rgn = dev->dma_range_map; | |
513 | int i, candidate = -1; | |
514 | dma_addr_t dma_end; | |
515 | ||
516 | if (!dma_rgn || plat_data->iova_region_nr == 1) | |
517 | return 0; | |
518 | ||
519 | dma_end = dma_rgn->dma_start + dma_rgn->size - 1; | |
520 | for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { | |
521 | /* Best fit. */ | |
522 | if (dma_rgn->dma_start == rgn->iova_base && | |
523 | dma_end == rgn->iova_base + rgn->size - 1) | |
524 | return i; | |
525 | /* ok if it is inside this region. */ | |
526 | if (dma_rgn->dma_start >= rgn->iova_base && | |
527 | dma_end < rgn->iova_base + rgn->size) | |
528 | candidate = i; | |
529 | } | |
530 | ||
531 | if (candidate >= 0) | |
532 | return candidate; | |
533 | dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", | |
534 | &dma_rgn->dma_start, dma_rgn->size); | |
535 | return -EINVAL; | |
536 | } | |
537 | ||
f9b8c9b2 | 538 | static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, |
d72e0ff5 | 539 | bool enable, unsigned int regionid) |
0df4fabe | 540 | { |
0df4fabe YW |
541 | struct mtk_smi_larb_iommu *larb_mmu; |
542 | unsigned int larbid, portid; | |
a9bf2eec | 543 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
8d2c749e | 544 | const struct mtk_iommu_iova_region *region; |
f9b8c9b2 YW |
545 | u32 peri_mmuen, peri_mmuen_msk; |
546 | int i, ret = 0; | |
0df4fabe | 547 | |
58f0d1d5 RM |
548 | for (i = 0; i < fwspec->num_ids; ++i) { |
549 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
550 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
8d2c749e | 551 | |
d2e9a110 YW |
552 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { |
553 | larb_mmu = &data->larb_imu[larbid]; | |
0df4fabe | 554 | |
d72e0ff5 | 555 | region = data->plat_data->iova_region + regionid; |
d2e9a110 | 556 | larb_mmu->bank[portid] = upper_32_bits(region->iova_base); |
8d2c749e | 557 | |
d72e0ff5 | 558 | dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", |
d2e9a110 | 559 | enable ? "enable" : "disable", dev_name(larb_mmu->dev), |
d72e0ff5 | 560 | portid, regionid, larb_mmu->bank[portid]); |
0df4fabe | 561 | |
d2e9a110 YW |
562 | if (enable) |
563 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
564 | else | |
565 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
f9b8c9b2 YW |
566 | } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { |
567 | peri_mmuen_msk = BIT(portid); | |
e7629070 YW |
568 | /* PCI dev has only one output id, enable the next writing bit for PCIe */ |
569 | if (dev_is_pci(dev)) | |
570 | peri_mmuen_msk |= BIT(portid + 1); | |
f9b8c9b2 | 571 | |
e7629070 | 572 | peri_mmuen = enable ? peri_mmuen_msk : 0; |
f9b8c9b2 YW |
573 | ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, |
574 | peri_mmuen_msk, peri_mmuen); | |
575 | if (ret) | |
576 | dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", | |
577 | enable ? "enable" : "disable", | |
578 | dev_name(data->dev), peri_mmuen_msk, ret); | |
d2e9a110 | 579 | } |
0df4fabe | 580 | } |
f9b8c9b2 | 581 | return ret; |
0df4fabe YW |
582 | } |
583 | ||
4f956c97 | 584 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, |
c3045f39 | 585 | struct mtk_iommu_data *data, |
d72e0ff5 | 586 | unsigned int region_id) |
0df4fabe | 587 | { |
c3045f39 | 588 | const struct mtk_iommu_iova_region *region; |
99ca0228 YW |
589 | struct mtk_iommu_domain *m4u_dom; |
590 | ||
591 | /* Always use bank0 in sharing pgtable case */ | |
592 | m4u_dom = data->bank[0].m4u_dom; | |
593 | if (m4u_dom) { | |
594 | dom->iop = m4u_dom->iop; | |
595 | dom->cfg = m4u_dom->cfg; | |
596 | dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; | |
c3045f39 YW |
597 | goto update_iova_region; |
598 | } | |
599 | ||
0df4fabe YW |
600 | dom->cfg = (struct io_pgtable_cfg) { |
601 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
602 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e | 603 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, |
0df4fabe | 604 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
2f317da4 | 605 | .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, |
0df4fabe YW |
606 | .iommu_dev = data->dev, |
607 | }; | |
608 | ||
301c3ca1 YW |
609 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) |
610 | dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; | |
611 | ||
9bdfe4c1 YW |
612 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) |
613 | dom->cfg.oas = data->enable_4GB ? 33 : 32; | |
614 | else | |
615 | dom->cfg.oas = 35; | |
616 | ||
0df4fabe YW |
617 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); |
618 | if (!dom->iop) { | |
619 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
bd7ebb77 | 620 | return -ENOMEM; |
0df4fabe YW |
621 | } |
622 | ||
623 | /* Update our support page sizes bitmap */ | |
d16e0faa | 624 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
b7875eb9 | 625 | |
c3045f39 YW |
626 | update_iova_region: |
627 | /* Update the iova region for this domain */ | |
d72e0ff5 | 628 | region = data->plat_data->iova_region + region_id; |
c3045f39 YW |
629 | dom->domain.geometry.aperture_start = region->iova_base; |
630 | dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; | |
b7875eb9 | 631 | dom->domain.geometry.force_aperture = true; |
0df4fabe YW |
632 | return 0; |
633 | } | |
634 | ||
635 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
636 | { | |
637 | struct mtk_iommu_domain *dom; | |
638 | ||
32e1cccf | 639 | if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) |
0df4fabe YW |
640 | return NULL; |
641 | ||
642 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
643 | if (!dom) | |
644 | return NULL; | |
ddf67a87 | 645 | mutex_init(&dom->mutex); |
0df4fabe | 646 | |
0df4fabe YW |
647 | return &dom->domain; |
648 | } | |
649 | ||
650 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
651 | { | |
0df4fabe YW |
652 | kfree(to_mtk_domain(domain)); |
653 | } | |
654 | ||
655 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
656 | struct device *dev) | |
657 | { | |
645b87c1 | 658 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; |
0df4fabe | 659 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
9e3a2a64 | 660 | struct list_head *hw_list = data->hw_list; |
c0b57581 | 661 | struct device *m4udev = data->dev; |
99ca0228 | 662 | struct mtk_iommu_bank_data *bank; |
57fb481f | 663 | unsigned int bankid; |
d72e0ff5 | 664 | int ret, region_id; |
0df4fabe | 665 | |
d72e0ff5 YW |
666 | region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); |
667 | if (region_id < 0) | |
668 | return region_id; | |
803cf9e5 | 669 | |
57fb481f | 670 | bankid = mtk_iommu_get_bank_id(dev, data->plat_data); |
ddf67a87 | 671 | mutex_lock(&dom->mutex); |
99ca0228 | 672 | if (!dom->bank) { |
645b87c1 | 673 | /* Data is in the frstdata in sharing pgtable case. */ |
9e3a2a64 | 674 | frstdata = mtk_iommu_get_frst_data(hw_list); |
645b87c1 | 675 | |
d72e0ff5 | 676 | ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); |
ddf67a87 YW |
677 | if (ret) { |
678 | mutex_unlock(&dom->mutex); | |
04cee82e | 679 | return ret; |
ddf67a87 | 680 | } |
99ca0228 | 681 | dom->bank = &data->bank[bankid]; |
4f956c97 | 682 | } |
ddf67a87 | 683 | mutex_unlock(&dom->mutex); |
4f956c97 | 684 | |
0e5a3f2e | 685 | mutex_lock(&data->mutex); |
99ca0228 | 686 | bank = &data->bank[bankid]; |
e24453e1 | 687 | if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ |
c0b57581 | 688 | ret = pm_runtime_resume_and_get(m4udev); |
e24453e1 YW |
689 | if (ret < 0) { |
690 | dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); | |
0e5a3f2e | 691 | goto err_unlock; |
e24453e1 | 692 | } |
c0b57581 | 693 | |
e24453e1 | 694 | ret = mtk_iommu_hw_init(data, bankid); |
c0b57581 YW |
695 | if (ret) { |
696 | pm_runtime_put(m4udev); | |
0e5a3f2e | 697 | goto err_unlock; |
c0b57581 | 698 | } |
99ca0228 | 699 | bank->m4u_dom = dom; |
301c3ca1 | 700 | writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); |
c0b57581 YW |
701 | |
702 | pm_runtime_put(m4udev); | |
7c3a2ec0 | 703 | } |
0e5a3f2e | 704 | mutex_unlock(&data->mutex); |
7c3a2ec0 | 705 | |
d72e0ff5 | 706 | return mtk_iommu_config(data, dev, true, region_id); |
0e5a3f2e YW |
707 | |
708 | err_unlock: | |
709 | mutex_unlock(&data->mutex); | |
710 | return ret; | |
0df4fabe YW |
711 | } |
712 | ||
713 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
714 | struct device *dev) | |
715 | { | |
3524b559 | 716 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 717 | |
8d2c749e | 718 | mtk_iommu_config(data, dev, false, 0); |
0df4fabe YW |
719 | } |
720 | ||
721 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
85637380 RM |
722 | phys_addr_t paddr, size_t pgsize, size_t pgcount, |
723 | int prot, gfp_t gfp, size_t *mapped) | |
0df4fabe YW |
724 | { |
725 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 726 | |
b4dad40e | 727 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
99ca0228 | 728 | if (dom->bank->parent_data->enable_4GB) |
b4dad40e YW |
729 | paddr |= BIT_ULL(32); |
730 | ||
60829b4d | 731 | /* Synchronize with the tlb_lock */ |
85637380 | 732 | return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); |
0df4fabe YW |
733 | } |
734 | ||
735 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
85637380 | 736 | unsigned long iova, size_t pgsize, size_t pgcount, |
56f8af5e | 737 | struct iommu_iotlb_gather *gather) |
0df4fabe YW |
738 | { |
739 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 740 | |
85637380 RM |
741 | iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount); |
742 | return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); | |
0df4fabe YW |
743 | } |
744 | ||
56f8af5e WD |
745 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
746 | { | |
08500c43 YW |
747 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
748 | ||
99ca0228 | 749 | mtk_iommu_tlb_flush_all(dom->bank->parent_data); |
56f8af5e WD |
750 | } |
751 | ||
752 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
753 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 754 | { |
08500c43 | 755 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
862c3715 | 756 | size_t length = gather->end - gather->start + 1; |
da3cc91b | 757 | |
99ca0228 | 758 | mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); |
4d689b61 RM |
759 | } |
760 | ||
20143451 YW |
761 | static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, |
762 | size_t size) | |
763 | { | |
08500c43 | 764 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
20143451 | 765 | |
99ca0228 | 766 | mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); |
20143451 YW |
767 | } |
768 | ||
0df4fabe YW |
769 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
770 | dma_addr_t iova) | |
771 | { | |
772 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe YW |
773 | phys_addr_t pa; |
774 | ||
0df4fabe | 775 | pa = dom->iop->iova_to_phys(dom->iop, iova); |
f13efafc | 776 | if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && |
99ca0228 | 777 | dom->bank->parent_data->enable_4GB && |
f13efafc | 778 | pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
b4dad40e | 779 | pa &= ~BIT_ULL(32); |
30e2fccf | 780 | |
0df4fabe YW |
781 | return pa; |
782 | } | |
783 | ||
80e4592a | 784 | static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
0df4fabe | 785 | { |
a9bf2eec | 786 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 787 | struct mtk_iommu_data *data; |
635319a4 YW |
788 | struct device_link *link; |
789 | struct device *larbdev; | |
790 | unsigned int larbid, larbidx, i; | |
0df4fabe | 791 | |
a9bf2eec | 792 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
80e4592a | 793 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
0df4fabe | 794 | |
3524b559 | 795 | data = dev_iommu_priv_get(dev); |
b16c0170 | 796 | |
d2e9a110 YW |
797 | if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) |
798 | return &data->iommu; | |
799 | ||
635319a4 YW |
800 | /* |
801 | * Link the consumer device with the smi-larb device(supplier). | |
802 | * The device that connects with each a larb is a independent HW. | |
803 | * All the ports in each a device should be in the same larbs. | |
804 | */ | |
805 | larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); | |
de78657e MC |
806 | if (larbid >= MTK_LARB_NR_MAX) |
807 | return ERR_PTR(-EINVAL); | |
808 | ||
635319a4 YW |
809 | for (i = 1; i < fwspec->num_ids; i++) { |
810 | larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
811 | if (larbid != larbidx) { | |
812 | dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", | |
813 | larbid, larbidx); | |
814 | return ERR_PTR(-EINVAL); | |
815 | } | |
816 | } | |
817 | larbdev = data->larb_imu[larbid].dev; | |
de78657e MC |
818 | if (!larbdev) |
819 | return ERR_PTR(-EINVAL); | |
820 | ||
635319a4 YW |
821 | link = device_link_add(dev, larbdev, |
822 | DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); | |
823 | if (!link) | |
824 | dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); | |
80e4592a | 825 | return &data->iommu; |
0df4fabe YW |
826 | } |
827 | ||
80e4592a | 828 | static void mtk_iommu_release_device(struct device *dev) |
0df4fabe | 829 | { |
a9bf2eec | 830 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
635319a4 YW |
831 | struct mtk_iommu_data *data; |
832 | struct device *larbdev; | |
833 | unsigned int larbid; | |
b16c0170 | 834 | |
635319a4 | 835 | data = dev_iommu_priv_get(dev); |
d2e9a110 YW |
836 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { |
837 | larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); | |
838 | larbdev = data->larb_imu[larbid].dev; | |
839 | device_link_remove(dev, larbdev); | |
840 | } | |
0df4fabe YW |
841 | } |
842 | ||
57fb481f YW |
843 | static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) |
844 | { | |
845 | unsigned int bankid; | |
846 | ||
847 | /* | |
848 | * If the bank function is enabled, each bank is a iommu group/domain. | |
849 | * Otherwise, each iova region is a iommu group/domain. | |
850 | */ | |
851 | bankid = mtk_iommu_get_bank_id(dev, plat_data); | |
852 | if (bankid) | |
853 | return bankid; | |
854 | ||
855 | return mtk_iommu_get_iova_region_id(dev, plat_data); | |
856 | } | |
857 | ||
0df4fabe YW |
858 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) |
859 | { | |
9e3a2a64 YW |
860 | struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; |
861 | struct list_head *hw_list = c_data->hw_list; | |
c3045f39 | 862 | struct iommu_group *group; |
57fb481f | 863 | int groupid; |
0df4fabe | 864 | |
9e3a2a64 | 865 | data = mtk_iommu_get_frst_data(hw_list); |
58f0d1d5 | 866 | if (!data) |
0df4fabe YW |
867 | return ERR_PTR(-ENODEV); |
868 | ||
57fb481f YW |
869 | groupid = mtk_iommu_get_group_id(dev, data->plat_data); |
870 | if (groupid < 0) | |
871 | return ERR_PTR(groupid); | |
803cf9e5 | 872 | |
0e5a3f2e | 873 | mutex_lock(&data->mutex); |
57fb481f | 874 | group = data->m4u_group[groupid]; |
c3045f39 YW |
875 | if (!group) { |
876 | group = iommu_group_alloc(); | |
877 | if (!IS_ERR(group)) | |
57fb481f | 878 | data->m4u_group[groupid] = group; |
3a8d40b6 | 879 | } else { |
c3045f39 | 880 | iommu_group_ref_get(group); |
0df4fabe | 881 | } |
0e5a3f2e | 882 | mutex_unlock(&data->mutex); |
c3045f39 | 883 | return group; |
0df4fabe YW |
884 | } |
885 | ||
886 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
887 | { | |
0df4fabe YW |
888 | struct platform_device *m4updev; |
889 | ||
890 | if (args->args_count != 1) { | |
891 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
892 | args->args_count); | |
893 | return -EINVAL; | |
894 | } | |
895 | ||
3524b559 | 896 | if (!dev_iommu_priv_get(dev)) { |
0df4fabe YW |
897 | /* Get the m4u device */ |
898 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
899 | if (WARN_ON(!m4updev)) |
900 | return -EINVAL; | |
901 | ||
3524b559 | 902 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
0df4fabe YW |
903 | } |
904 | ||
58f0d1d5 | 905 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
906 | } |
907 | ||
ab1d5281 YW |
908 | static void mtk_iommu_get_resv_regions(struct device *dev, |
909 | struct list_head *head) | |
910 | { | |
911 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); | |
d72e0ff5 | 912 | unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; |
ab1d5281 YW |
913 | const struct mtk_iommu_iova_region *resv, *curdom; |
914 | struct iommu_resv_region *region; | |
915 | int prot = IOMMU_WRITE | IOMMU_READ; | |
916 | ||
d72e0ff5 | 917 | if ((int)regionid < 0) |
ab1d5281 | 918 | return; |
d72e0ff5 | 919 | curdom = data->plat_data->iova_region + regionid; |
ab1d5281 YW |
920 | for (i = 0; i < data->plat_data->iova_region_nr; i++) { |
921 | resv = data->plat_data->iova_region + i; | |
922 | ||
923 | /* Only reserve when the region is inside the current domain */ | |
924 | if (resv->iova_base <= curdom->iova_base || | |
925 | resv->iova_base + resv->size >= curdom->iova_base + curdom->size) | |
926 | continue; | |
927 | ||
928 | region = iommu_alloc_resv_region(resv->iova_base, resv->size, | |
0251d010 LB |
929 | prot, IOMMU_RESV_RESERVED, |
930 | GFP_KERNEL); | |
ab1d5281 YW |
931 | if (!region) |
932 | return; | |
933 | ||
934 | list_add_tail(®ion->list, head); | |
935 | } | |
936 | } | |
937 | ||
b65f5016 | 938 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe | 939 | .domain_alloc = mtk_iommu_domain_alloc, |
80e4592a JR |
940 | .probe_device = mtk_iommu_probe_device, |
941 | .release_device = mtk_iommu_release_device, | |
0df4fabe YW |
942 | .device_group = mtk_iommu_device_group, |
943 | .of_xlate = mtk_iommu_of_xlate, | |
ab1d5281 | 944 | .get_resv_regions = mtk_iommu_get_resv_regions, |
0df4fabe | 945 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, |
18d8c74e | 946 | .owner = THIS_MODULE, |
9a630a4b LB |
947 | .default_domain_ops = &(const struct iommu_domain_ops) { |
948 | .attach_dev = mtk_iommu_attach_device, | |
949 | .detach_dev = mtk_iommu_detach_device, | |
85637380 RM |
950 | .map_pages = mtk_iommu_map, |
951 | .unmap_pages = mtk_iommu_unmap, | |
9a630a4b LB |
952 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
953 | .iotlb_sync = mtk_iommu_iotlb_sync, | |
954 | .iotlb_sync_map = mtk_iommu_sync_map, | |
955 | .iova_to_phys = mtk_iommu_iova_to_phys, | |
956 | .free = mtk_iommu_domain_free, | |
957 | } | |
0df4fabe YW |
958 | }; |
959 | ||
e24453e1 | 960 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) |
0df4fabe | 961 | { |
e24453e1 | 962 | const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; |
99ca0228 | 963 | const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; |
0df4fabe | 964 | u32 regval; |
0df4fabe | 965 | |
e24453e1 YW |
966 | /* |
967 | * Global control settings are in bank0. May re-init these global registers | |
968 | * since no sure if there is bank0 consumers. | |
969 | */ | |
86580ec9 | 970 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { |
acb3c92a YW |
971 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
972 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
86444413 | 973 | } else { |
99ca0228 | 974 | regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); |
86444413 CH |
975 | regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; |
976 | } | |
99ca0228 | 977 | writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); |
0df4fabe | 978 | |
6b717796 CH |
979 | if (data->enable_4GB && |
980 | MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { | |
30e2fccf YW |
981 | /* |
982 | * If 4GB mode is enabled, the validate PA range is from | |
983 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
984 | */ | |
985 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
99ca0228 | 986 | writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); |
30e2fccf | 987 | } |
9a87005e | 988 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) |
99ca0228 | 989 | writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); |
9a87005e | 990 | else |
99ca0228 | 991 | writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); |
9a87005e | 992 | |
35c1b48d CH |
993 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { |
994 | /* write command throttling mode */ | |
99ca0228 | 995 | regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); |
35c1b48d | 996 | regval &= ~F_MMU_WR_THROT_DIS_MASK; |
99ca0228 | 997 | writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); |
35c1b48d | 998 | } |
e6dec923 | 999 | |
6b717796 | 1000 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { |
75eed350 | 1001 | /* The register is called STANDARD_AXI_MODE in this case */ |
4bb2bf4c CH |
1002 | regval = 0; |
1003 | } else { | |
99ca0228 | 1004 | regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); |
d265a4ad YW |
1005 | if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) |
1006 | regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; | |
4bb2bf4c CH |
1007 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) |
1008 | regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; | |
75eed350 | 1009 | } |
99ca0228 | 1010 | writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); |
0df4fabe | 1011 | |
e24453e1 | 1012 | /* Independent settings for each bank */ |
634f57df YW |
1013 | regval = F_L2_MULIT_HIT_EN | |
1014 | F_TABLE_WALK_FAULT_INT_EN | | |
1015 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
1016 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
1017 | F_PREFETCH_FIFO_ERR_INT_EN | | |
1018 | F_MISS_FIFO_ERR_INT_EN; | |
e24453e1 | 1019 | writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); |
634f57df YW |
1020 | |
1021 | regval = F_INT_TRANSLATION_FAULT | | |
1022 | F_INT_MAIN_MULTI_HIT_FAULT | | |
1023 | F_INT_INVALID_PA_FAULT | | |
1024 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
1025 | F_INT_TLB_MISS_FAULT | | |
1026 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
1027 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
e24453e1 | 1028 | writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); |
634f57df YW |
1029 | |
1030 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) | |
1031 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); | |
1032 | else | |
1033 | regval = lower_32_bits(data->protect_base) | | |
1034 | upper_32_bits(data->protect_base); | |
e24453e1 | 1035 | writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); |
634f57df | 1036 | |
e24453e1 YW |
1037 | if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, |
1038 | dev_name(bankx->parent_dev), (void *)bankx)) { | |
1039 | writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); | |
1040 | dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); | |
0df4fabe YW |
1041 | return -ENODEV; |
1042 | } | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
0df4fabe YW |
1047 | static const struct component_master_ops mtk_iommu_com_ops = { |
1048 | .bind = mtk_iommu_bind, | |
1049 | .unbind = mtk_iommu_unbind, | |
1050 | }; | |
1051 | ||
d2e9a110 YW |
1052 | static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, |
1053 | struct mtk_iommu_data *data) | |
1054 | { | |
6cde583d | 1055 | struct device_node *larbnode, *frst_avail_smicomm_node = NULL; |
dcb40e9f | 1056 | struct platform_device *plarbdev, *pcommdev; |
d2e9a110 YW |
1057 | struct device_link *link; |
1058 | int i, larb_nr, ret; | |
1059 | ||
1060 | larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); | |
1061 | if (larb_nr < 0) | |
1062 | return larb_nr; | |
ef693a84 GR |
1063 | if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX) |
1064 | return -EINVAL; | |
d2e9a110 YW |
1065 | |
1066 | for (i = 0; i < larb_nr; i++) { | |
6cde583d | 1067 | struct device_node *smicomm_node, *smi_subcomm_node; |
d2e9a110 YW |
1068 | u32 id; |
1069 | ||
1070 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
26593928 YW |
1071 | if (!larbnode) { |
1072 | ret = -EINVAL; | |
1073 | goto err_larbdev_put; | |
1074 | } | |
d2e9a110 YW |
1075 | |
1076 | if (!of_device_is_available(larbnode)) { | |
1077 | of_node_put(larbnode); | |
1078 | continue; | |
1079 | } | |
1080 | ||
1081 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); | |
1082 | if (ret)/* The id is consecutive if there is no this property */ | |
1083 | id = i; | |
ef693a84 GR |
1084 | if (id >= MTK_LARB_NR_MAX) { |
1085 | of_node_put(larbnode); | |
1086 | ret = -EINVAL; | |
1087 | goto err_larbdev_put; | |
1088 | } | |
d2e9a110 YW |
1089 | |
1090 | plarbdev = of_find_device_by_node(larbnode); | |
b5765a1b | 1091 | of_node_put(larbnode); |
d2e9a110 | 1092 | if (!plarbdev) { |
26593928 YW |
1093 | ret = -ENODEV; |
1094 | goto err_larbdev_put; | |
d2e9a110 | 1095 | } |
ef693a84 GR |
1096 | if (data->larb_imu[id].dev) { |
1097 | platform_device_put(plarbdev); | |
1098 | ret = -EEXIST; | |
1099 | goto err_larbdev_put; | |
d2e9a110 YW |
1100 | } |
1101 | data->larb_imu[id].dev = &plarbdev->dev; | |
1102 | ||
d2e9a110 | 1103 | if (!plarbdev->dev.driver) { |
26593928 YW |
1104 | ret = -EPROBE_DEFER; |
1105 | goto err_larbdev_put; | |
d2e9a110 | 1106 | } |
d2e9a110 | 1107 | |
6cde583d YW |
1108 | /* Get smi-(sub)-common dev from the last larb. */ |
1109 | smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); | |
1110 | if (!smi_subcomm_node) { | |
1111 | ret = -EINVAL; | |
1112 | goto err_larbdev_put; | |
1113 | } | |
1114 | ||
1115 | /* | |
1116 | * It may have two level smi-common. the node is smi-sub-common if it | |
1117 | * has a new mediatek,smi property. otherwise it is smi-commmon. | |
1118 | */ | |
1119 | smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); | |
1120 | if (smicomm_node) | |
1121 | of_node_put(smi_subcomm_node); | |
1122 | else | |
1123 | smicomm_node = smi_subcomm_node; | |
1124 | ||
1125 | /* | |
1126 | * All the larbs that connect to one IOMMU must connect with the same | |
1127 | * smi-common. | |
1128 | */ | |
1129 | if (!frst_avail_smicomm_node) { | |
1130 | frst_avail_smicomm_node = smicomm_node; | |
1131 | } else if (frst_avail_smicomm_node != smicomm_node) { | |
1132 | dev_err(dev, "mediatek,smi property is not right @larb%d.", id); | |
1133 | of_node_put(smicomm_node); | |
1134 | ret = -EINVAL; | |
1135 | goto err_larbdev_put; | |
1136 | } else { | |
1137 | of_node_put(smicomm_node); | |
1138 | } | |
1139 | ||
b5765a1b | 1140 | component_match_add(dev, match, component_compare_dev, &plarbdev->dev); |
dcb40e9f | 1141 | platform_device_put(plarbdev); |
d2e9a110 YW |
1142 | } |
1143 | ||
6cde583d | 1144 | if (!frst_avail_smicomm_node) |
d2e9a110 YW |
1145 | return -EINVAL; |
1146 | ||
6cde583d YW |
1147 | pcommdev = of_find_device_by_node(frst_avail_smicomm_node); |
1148 | of_node_put(frst_avail_smicomm_node); | |
dcb40e9f YW |
1149 | if (!pcommdev) |
1150 | return -ENODEV; | |
1151 | data->smicomm_dev = &pcommdev->dev; | |
d2e9a110 YW |
1152 | |
1153 | link = device_link_add(data->smicomm_dev, dev, | |
1154 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); | |
dcb40e9f | 1155 | platform_device_put(pcommdev); |
d2e9a110 YW |
1156 | if (!link) { |
1157 | dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); | |
1158 | return -EINVAL; | |
1159 | } | |
1160 | return 0; | |
26593928 YW |
1161 | |
1162 | err_larbdev_put: | |
462e768b | 1163 | for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) { |
26593928 YW |
1164 | if (!data->larb_imu[i].dev) |
1165 | continue; | |
1166 | put_device(data->larb_imu[i].dev); | |
1167 | } | |
1168 | return ret; | |
d2e9a110 YW |
1169 | } |
1170 | ||
0df4fabe YW |
1171 | static int mtk_iommu_probe(struct platform_device *pdev) |
1172 | { | |
1173 | struct mtk_iommu_data *data; | |
1174 | struct device *dev = &pdev->dev; | |
1175 | struct resource *res; | |
b16c0170 | 1176 | resource_size_t ioaddr; |
0df4fabe | 1177 | struct component_match *match = NULL; |
c2c59456 | 1178 | struct regmap *infracfg; |
0df4fabe | 1179 | void *protect; |
42d57fc5 | 1180 | int ret, banks_num, i = 0; |
c2c59456 MC |
1181 | u32 val; |
1182 | char *p; | |
99ca0228 YW |
1183 | struct mtk_iommu_bank_data *bank; |
1184 | void __iomem *base; | |
0df4fabe YW |
1185 | |
1186 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
1187 | if (!data) | |
1188 | return -ENOMEM; | |
1189 | data->dev = dev; | |
cecdce9d | 1190 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
1191 | |
1192 | /* Protect memory. HW will access here while translation fault.*/ | |
1193 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
1194 | if (!protect) | |
1195 | return -ENOMEM; | |
1196 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
1197 | ||
c2c59456 | 1198 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { |
7d748ffd ADR |
1199 | infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); |
1200 | if (IS_ERR(infracfg)) { | |
1201 | /* | |
1202 | * Legacy devicetrees will not specify a phandle to | |
1203 | * mediatek,infracfg: in that case, we use the older | |
1204 | * way to retrieve a syscon to infra. | |
1205 | * | |
1206 | * This is for retrocompatibility purposes only, hence | |
1207 | * no more compatibles shall be added to this. | |
1208 | */ | |
1209 | switch (data->plat_data->m4u_plat) { | |
1210 | case M4U_MT2712: | |
1211 | p = "mediatek,mt2712-infracfg"; | |
1212 | break; | |
1213 | case M4U_MT8173: | |
1214 | p = "mediatek,mt8173-infracfg"; | |
1215 | break; | |
1216 | default: | |
1217 | p = NULL; | |
1218 | } | |
1219 | ||
1220 | infracfg = syscon_regmap_lookup_by_compatible(p); | |
1221 | if (IS_ERR(infracfg)) | |
1222 | return PTR_ERR(infracfg); | |
c2c59456 MC |
1223 | } |
1224 | ||
c2c59456 MC |
1225 | ret = regmap_read(infracfg, REG_INFRA_MISC, &val); |
1226 | if (ret) | |
1227 | return ret; | |
1228 | data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); | |
1229 | } | |
01e23c93 | 1230 | |
42d57fc5 | 1231 | banks_num = data->plat_data->banks_num; |
0df4fabe | 1232 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
73b6924c YY |
1233 | if (!res) |
1234 | return -EINVAL; | |
42d57fc5 YW |
1235 | if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { |
1236 | dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); | |
1237 | return -EINVAL; | |
1238 | } | |
99ca0228 YW |
1239 | base = devm_ioremap_resource(dev, res); |
1240 | if (IS_ERR(base)) | |
1241 | return PTR_ERR(base); | |
b16c0170 | 1242 | ioaddr = res->start; |
0df4fabe | 1243 | |
99ca0228 YW |
1244 | data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); |
1245 | if (!data->bank) | |
1246 | return -ENOMEM; | |
1247 | ||
42d57fc5 YW |
1248 | do { |
1249 | if (!data->plat_data->banks_enable[i]) | |
1250 | continue; | |
1251 | bank = &data->bank[i]; | |
1252 | bank->id = i; | |
1253 | bank->base = base + i * MTK_IOMMU_BANK_SZ; | |
1254 | bank->m4u_dom = NULL; | |
1255 | ||
1256 | bank->irq = platform_get_irq(pdev, i); | |
1257 | if (bank->irq < 0) | |
1258 | return bank->irq; | |
1259 | bank->parent_dev = dev; | |
1260 | bank->parent_data = data; | |
1261 | spin_lock_init(&bank->tlb_lock); | |
1262 | } while (++i < banks_num); | |
0df4fabe | 1263 | |
6b717796 | 1264 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { |
2aa4c259 YW |
1265 | data->bclk = devm_clk_get(dev, "bclk"); |
1266 | if (IS_ERR(data->bclk)) | |
1267 | return PTR_ERR(data->bclk); | |
1268 | } | |
0df4fabe | 1269 | |
c0b57581 YW |
1270 | pm_runtime_enable(dev); |
1271 | ||
d2e9a110 YW |
1272 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { |
1273 | ret = mtk_iommu_mm_dts_parse(dev, &match, data); | |
1274 | if (ret) { | |
3168010d | 1275 | dev_err_probe(dev, ret, "mm dts parse fail\n"); |
d2e9a110 YW |
1276 | goto out_runtime_disable; |
1277 | } | |
21fd9be4 ADR |
1278 | } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { |
1279 | p = data->plat_data->pericfg_comp_str; | |
1280 | data->pericfg = syscon_regmap_lookup_by_compatible(p); | |
1281 | if (IS_ERR(data->pericfg)) { | |
1282 | ret = PTR_ERR(data->pericfg); | |
f9b8c9b2 YW |
1283 | goto out_runtime_disable; |
1284 | } | |
baf94e6e YW |
1285 | } |
1286 | ||
0df4fabe | 1287 | platform_set_drvdata(pdev, data); |
0e5a3f2e | 1288 | mutex_init(&data->mutex); |
0df4fabe | 1289 | |
b16c0170 JR |
1290 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
1291 | "mtk-iommu.%pa", &ioaddr); | |
1292 | if (ret) | |
baf94e6e | 1293 | goto out_link_remove; |
b16c0170 | 1294 | |
2d471b20 | 1295 | ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); |
b16c0170 | 1296 | if (ret) |
986d9ec5 | 1297 | goto out_sysfs_remove; |
b16c0170 | 1298 | |
9e3a2a64 YW |
1299 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { |
1300 | list_add_tail(&data->list, data->plat_data->hw_list); | |
1301 | data->hw_list = data->plat_data->hw_list; | |
1302 | } else { | |
1303 | INIT_LIST_HEAD(&data->hw_list_head); | |
1304 | list_add_tail(&data->list, &data->hw_list_head); | |
1305 | data->hw_list = &data->hw_list_head; | |
1306 | } | |
7c3a2ec0 | 1307 | |
d2e9a110 YW |
1308 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { |
1309 | ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); | |
1310 | if (ret) | |
7341c365 | 1311 | goto out_list_del; |
d2e9a110 | 1312 | } |
986d9ec5 YW |
1313 | return ret; |
1314 | ||
986d9ec5 YW |
1315 | out_list_del: |
1316 | list_del(&data->list); | |
1317 | iommu_device_unregister(&data->iommu); | |
1318 | out_sysfs_remove: | |
1319 | iommu_device_sysfs_remove(&data->iommu); | |
baf94e6e | 1320 | out_link_remove: |
d2e9a110 YW |
1321 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) |
1322 | device_link_remove(data->smicomm_dev, dev); | |
c0b57581 YW |
1323 | out_runtime_disable: |
1324 | pm_runtime_disable(dev); | |
986d9ec5 | 1325 | return ret; |
0df4fabe YW |
1326 | } |
1327 | ||
1328 | static int mtk_iommu_remove(struct platform_device *pdev) | |
1329 | { | |
1330 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
42d57fc5 YW |
1331 | struct mtk_iommu_bank_data *bank; |
1332 | int i; | |
0df4fabe | 1333 | |
b16c0170 JR |
1334 | iommu_device_sysfs_remove(&data->iommu); |
1335 | iommu_device_unregister(&data->iommu); | |
1336 | ||
ee55f75e | 1337 | list_del(&data->list); |
0df4fabe | 1338 | |
d2e9a110 YW |
1339 | if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { |
1340 | device_link_remove(data->smicomm_dev, &pdev->dev); | |
1341 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
1342 | } | |
c0b57581 | 1343 | pm_runtime_disable(&pdev->dev); |
42d57fc5 YW |
1344 | for (i = 0; i < data->plat_data->banks_num; i++) { |
1345 | bank = &data->bank[i]; | |
1346 | if (!bank->m4u_dom) | |
1347 | continue; | |
1348 | devm_free_irq(&pdev->dev, bank->irq, bank); | |
1349 | } | |
0df4fabe YW |
1350 | return 0; |
1351 | } | |
1352 | ||
34665c79 | 1353 | static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) |
0df4fabe YW |
1354 | { |
1355 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
1356 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
d7127de1 YW |
1357 | void __iomem *base; |
1358 | int i = 0; | |
0df4fabe | 1359 | |
d7127de1 | 1360 | base = data->bank[i].base; |
35c1b48d | 1361 | reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 1362 | reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
1363 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
1364 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
b9475b34 | 1365 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
d7127de1 YW |
1366 | do { |
1367 | if (!data->plat_data->banks_enable[i]) | |
1368 | continue; | |
1369 | base = data->bank[i].base; | |
1370 | reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
1371 | reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
1372 | reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); | |
1373 | } while (++i < data->plat_data->banks_num); | |
6254b64f | 1374 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
1375 | return 0; |
1376 | } | |
1377 | ||
34665c79 | 1378 | static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) |
0df4fabe YW |
1379 | { |
1380 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
1381 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
d7127de1 YW |
1382 | struct mtk_iommu_domain *m4u_dom; |
1383 | void __iomem *base; | |
1384 | int ret, i = 0; | |
0df4fabe | 1385 | |
6254b64f YW |
1386 | ret = clk_prepare_enable(data->bclk); |
1387 | if (ret) { | |
1388 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
1389 | return ret; | |
1390 | } | |
b34ea31f DH |
1391 | |
1392 | /* | |
1393 | * Uppon first resume, only enable the clk and return, since the values of the | |
1394 | * registers are not yet set. | |
1395 | */ | |
d7127de1 | 1396 | if (!reg->wr_len_ctrl) |
b34ea31f DH |
1397 | return 0; |
1398 | ||
d7127de1 | 1399 | base = data->bank[i].base; |
35c1b48d | 1400 | writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 1401 | writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
1402 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
1403 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
b9475b34 | 1404 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
d7127de1 YW |
1405 | do { |
1406 | m4u_dom = data->bank[i].m4u_dom; | |
1407 | if (!data->plat_data->banks_enable[i] || !m4u_dom) | |
1408 | continue; | |
1409 | base = data->bank[i].base; | |
1410 | writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); | |
1411 | writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); | |
1412 | writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); | |
301c3ca1 | 1413 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); |
d7127de1 | 1414 | } while (++i < data->plat_data->banks_num); |
4f23f6d4 YW |
1415 | |
1416 | /* | |
1417 | * Users may allocate dma buffer before they call pm_runtime_get, | |
1418 | * in which case it will lack the necessary tlb flush. | |
1419 | * Thus, make sure to update the tlb after each PM resume. | |
1420 | */ | |
1421 | mtk_iommu_tlb_flush_all(data); | |
0df4fabe YW |
1422 | return 0; |
1423 | } | |
1424 | ||
e6dec923 | 1425 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
34665c79 YW |
1426 | SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) |
1427 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1428 | pm_runtime_force_resume) | |
0df4fabe YW |
1429 | }; |
1430 | ||
cecdce9d YW |
1431 | static const struct mtk_iommu_plat_data mt2712_data = { |
1432 | .m4u_plat = M4U_MT2712, | |
d2e9a110 YW |
1433 | .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | |
1434 | MTK_IOMMU_TYPE_MM, | |
9e3a2a64 | 1435 | .hw_list = &m4ulist, |
b053bc71 | 1436 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
585e58f4 | 1437 | .iova_region = single_domain, |
99ca0228 YW |
1438 | .banks_num = 1, |
1439 | .banks_enable = {true}, | |
585e58f4 | 1440 | .iova_region_nr = ARRAY_SIZE(single_domain), |
37276e00 | 1441 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, |
cecdce9d YW |
1442 | }; |
1443 | ||
068c86e9 CH |
1444 | static const struct mtk_iommu_plat_data mt6779_data = { |
1445 | .m4u_plat = M4U_MT6779, | |
d2e9a110 | 1446 | .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | |
301c3ca1 | 1447 | MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, |
068c86e9 | 1448 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, |
99ca0228 YW |
1449 | .banks_num = 1, |
1450 | .banks_enable = {true}, | |
585e58f4 YW |
1451 | .iova_region = single_domain, |
1452 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
068c86e9 | 1453 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, |
cecdce9d YW |
1454 | }; |
1455 | ||
717ec15e ADR |
1456 | static const struct mtk_iommu_plat_data mt6795_data = { |
1457 | .m4u_plat = M4U_MT6795, | |
1458 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | | |
1459 | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | | |
1460 | TF_PORT_TO_ADDR_MT8173, | |
1461 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, | |
1462 | .banks_num = 1, | |
1463 | .banks_enable = {true}, | |
1464 | .iova_region = single_domain, | |
1465 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
1466 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ | |
1467 | }; | |
1468 | ||
3c213562 FP |
1469 | static const struct mtk_iommu_plat_data mt8167_data = { |
1470 | .m4u_plat = M4U_MT8167, | |
d2e9a110 | 1471 | .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, |
3c213562 | 1472 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
99ca0228 YW |
1473 | .banks_num = 1, |
1474 | .banks_enable = {true}, | |
585e58f4 YW |
1475 | .iova_region = single_domain, |
1476 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
3c213562 FP |
1477 | .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ |
1478 | }; | |
1479 | ||
cecdce9d YW |
1480 | static const struct mtk_iommu_plat_data mt8173_data = { |
1481 | .m4u_plat = M4U_MT8173, | |
d1b5ef00 | 1482 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
86580ec9 ADR |
1483 | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | |
1484 | TF_PORT_TO_ADDR_MT8173, | |
b053bc71 | 1485 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
99ca0228 YW |
1486 | .banks_num = 1, |
1487 | .banks_enable = {true}, | |
585e58f4 YW |
1488 | .iova_region = single_domain, |
1489 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
37276e00 | 1490 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ |
cecdce9d YW |
1491 | }; |
1492 | ||
907ba6a1 YW |
1493 | static const struct mtk_iommu_plat_data mt8183_data = { |
1494 | .m4u_plat = M4U_MT8183, | |
d2e9a110 | 1495 | .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, |
b053bc71 | 1496 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
99ca0228 YW |
1497 | .banks_num = 1, |
1498 | .banks_enable = {true}, | |
585e58f4 YW |
1499 | .iova_region = single_domain, |
1500 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
37276e00 | 1501 | .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, |
907ba6a1 YW |
1502 | }; |
1503 | ||
e8d7ccaa YW |
1504 | static const struct mtk_iommu_plat_data mt8186_data_mm = { |
1505 | .m4u_plat = M4U_MT8186, | |
1506 | .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | | |
1507 | WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, | |
1508 | .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, | |
1509 | {MTK_INVALID_LARBID, 14, 16}, | |
1510 | {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, | |
1511 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
1512 | .banks_num = 1, | |
1513 | .banks_enable = {true}, | |
1514 | .iova_region = mt8192_multi_dom, | |
1515 | .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), | |
1516 | }; | |
1517 | ||
9e3489e0 YW |
1518 | static const struct mtk_iommu_plat_data mt8192_data = { |
1519 | .m4u_plat = M4U_MT8192, | |
9ec30c09 | 1520 | .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | |
d2e9a110 | 1521 | WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, |
9e3489e0 | 1522 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, |
99ca0228 YW |
1523 | .banks_num = 1, |
1524 | .banks_enable = {true}, | |
9e3489e0 YW |
1525 | .iova_region = mt8192_multi_dom, |
1526 | .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), | |
1527 | .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, | |
1528 | {0, 14, 16}, {0, 13, 18, 17}}, | |
1529 | }; | |
1530 | ||
ef68a193 YW |
1531 | static const struct mtk_iommu_plat_data mt8195_data_infra = { |
1532 | .m4u_plat = M4U_MT8195, | |
1533 | .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | | |
1534 | MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, | |
1535 | .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", | |
1536 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
7597e3c5 YW |
1537 | .banks_num = 5, |
1538 | .banks_enable = {true, false, false, false, true}, | |
1539 | .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ | |
1540 | [4] = GENMASK(31, 20), /* USB */ | |
1541 | }, | |
ef68a193 YW |
1542 | .iova_region = single_domain, |
1543 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
1544 | }; | |
1545 | ||
1546 | static const struct mtk_iommu_plat_data mt8195_data_vdo = { | |
1547 | .m4u_plat = M4U_MT8195, | |
1548 | .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | | |
1549 | WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, | |
1550 | .hw_list = &m4ulist, | |
1551 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
99ca0228 YW |
1552 | .banks_num = 1, |
1553 | .banks_enable = {true}, | |
ef68a193 YW |
1554 | .iova_region = mt8192_multi_dom, |
1555 | .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), | |
1556 | .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, | |
1557 | {13, 17, 15/* 17b */, 25}, {5}}, | |
1558 | }; | |
1559 | ||
1560 | static const struct mtk_iommu_plat_data mt8195_data_vpp = { | |
1561 | .m4u_plat = M4U_MT8195, | |
1562 | .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | | |
1563 | WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, | |
1564 | .hw_list = &m4ulist, | |
1565 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
99ca0228 YW |
1566 | .banks_num = 1, |
1567 | .banks_enable = {true}, | |
ef68a193 YW |
1568 | .iova_region = mt8192_multi_dom, |
1569 | .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), | |
1570 | .larbid_remap = {{1}, {3}, | |
1571 | {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, | |
1572 | {8}, {20}, {12}, | |
1573 | /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ | |
1574 | {14, 16, 29, 26, 30, 31, 18}, | |
1575 | {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, | |
1576 | }; | |
1577 | ||
3cd0e4a3 FP |
1578 | static const struct mtk_iommu_plat_data mt8365_data = { |
1579 | .m4u_plat = M4U_MT8365, | |
1580 | .flags = RESET_AXI | INT_ID_PORT_WIDTH_6, | |
1581 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, | |
1582 | .banks_num = 1, | |
1583 | .banks_enable = {true}, | |
1584 | .iova_region = single_domain, | |
1585 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
1586 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ | |
1587 | }; | |
1588 | ||
0df4fabe | 1589 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d | 1590 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
068c86e9 | 1591 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
717ec15e | 1592 | { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, |
3c213562 | 1593 | { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, |
cecdce9d | 1594 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
907ba6a1 | 1595 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
e8d7ccaa | 1596 | { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ |
9e3489e0 | 1597 | { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, |
ef68a193 YW |
1598 | { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, |
1599 | { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, | |
1600 | { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, | |
3cd0e4a3 | 1601 | { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, |
0df4fabe YW |
1602 | {} |
1603 | }; | |
1604 | ||
1605 | static struct platform_driver mtk_iommu_driver = { | |
1606 | .probe = mtk_iommu_probe, | |
1607 | .remove = mtk_iommu_remove, | |
1608 | .driver = { | |
1609 | .name = "mtk-iommu", | |
f53dd978 | 1610 | .of_match_table = mtk_iommu_of_ids, |
0df4fabe YW |
1611 | .pm = &mtk_iommu_pm_ops, |
1612 | } | |
1613 | }; | |
18d8c74e | 1614 | module_platform_driver(mtk_iommu_driver); |
0df4fabe | 1615 | |
18d8c74e YW |
1616 | MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); |
1617 | MODULE_LICENSE("GPL v2"); |