[linux-2.6-block.git] / drivers / iommu / msm_iommu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
 */

#ifndef MSM_IOMMU_H
#define MSM_IOMMU_H

#include <linux/interrupt.h>
#include <linux/iommu.h>
#include <linux/clk.h>

/* Sharability attributes of MSM IOMMU mappings */
#define MSM_IOMMU_ATTR_NON_SH		0x0
#define MSM_IOMMU_ATTR_SH		0x4

/* Cacheability attributes of MSM IOMMU mappings */
#define MSM_IOMMU_ATTR_NONCACHED	0x0
#define MSM_IOMMU_ATTR_CACHED_WB_WA	0x1
#define MSM_IOMMU_ATTR_CACHED_WB_NWA	0x2
#define MSM_IOMMU_ATTR_CACHED_WT	0x3

/* Mask for the cache policy attribute */
#define MSM_IOMMU_CP_MASK		0x03

/* Maximum number of Machine IDs that we are allowing to be mapped to the same
 * context bank. The number of MIDs mapped to the same CB does not affect
 * performance, but there is a practical limit on how many distinct MIDs may
 * be present. These mappings are typically determined at design time and are
 * not expected to change at run time.
 */
#define MAX_NUM_MIDS	32

/* Maximum number of context banks that can be present in IOMMU */
#define IOMMU_MAX_CBS	128

/**
 * struct msm_iommu_dev - a single IOMMU hardware instance
 * ncb		Number of context banks present on this IOMMU HW instance
 * dev:		IOMMU device
 * irq:		Interrupt number
 * clk:		The bus clock for this IOMMU hardware instance
 * pclk:	The clock for the IOMMU bus interconnect
 * dev_node:	list head in qcom_iommu_device_list
 * dom_node:	list head for domain
 * ctx_list:	list of 'struct msm_iommu_ctx_dev'
 * context_map: Bitmap to track allocated context banks
 */
struct msm_iommu_dev {
	void __iomem *base;
	int ncb;
	struct device *dev;
	int irq;
	struct clk *clk;
	struct clk *pclk;
	struct list_head dev_node;
	struct list_head dom_node;
	struct list_head ctx_list;
	DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);

	struct iommu_device iommu;
};

/**
 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
 * of_node	node ptr of client device
 * num		Index of this context bank within the hardware
 * mids		List of Machine IDs that are to be mapped into this context
 *		bank, terminated by -1. The MID is a set of signals on the
 *		AXI bus that identifies the function associated with a specific
 *		memory request. (See ARM spec).
 * num_mids	Total number of mids
 * node		list head in ctx_list
 */
struct msm_iommu_ctx_dev {
	struct device_node *of_node;
	int num;
	int mids[MAX_NUM_MIDS];
	int num_mids;
	struct list_head list;
};

/*
 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
 * interrupt is not supported in the API yet, but this will print an error
 * message and dump useful IOMMU registers.
 */
irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);

#endif
Commit	Line	Data
08dbd0f8	1	/* SPDX-License-Identifier: GPL-2.0-only */
41f3f513	2	/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0720d1f0 SM	3	*/
	4
	5	#ifndef MSM_IOMMU_H
	6	#define MSM_IOMMU_H
	7
	8	#include <linux/interrupt.h>
42df43b3	9	#include <linux/iommu.h>
41f3f513	10	#include <linux/clk.h>
0720d1f0	11
08bd6839 SM	12	/* Sharability attributes of MSM IOMMU mappings */
	13	#define MSM_IOMMU_ATTR_NON_SH 0x0
	14	#define MSM_IOMMU_ATTR_SH 0x4
	15
	16	/* Cacheability attributes of MSM IOMMU mappings */
	17	#define MSM_IOMMU_ATTR_NONCACHED 0x0
	18	#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
	19	#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
	20	#define MSM_IOMMU_ATTR_CACHED_WT 0x3
	21
	22	/* Mask for the cache policy attribute */
	23	#define MSM_IOMMU_CP_MASK 0x03
	24
0720d1f0 SM	25	/* Maximum number of Machine IDs that we are allowing to be mapped to the same
	26	* context bank. The number of MIDs mapped to the same CB does not affect
	27	* performance, but there is a practical limit on how many distinct MIDs may
	28	* be present. These mappings are typically determined at design time and are
	29	* not expected to change at run time.
	30	*/
23513c3b	31	#define MAX_NUM_MIDS 32
0720d1f0	32
109bd48e S	33	/* Maximum number of context banks that can be present in IOMMU */
	34	#define IOMMU_MAX_CBS 128
	35
0720d1f0 SM	36	/**
0720d1f0 SM	37	* struct msm_iommu_dev - a single IOMMU hardware instance
a43d8c10	38	* ncb Number of context banks present on this IOMMU HW instance
109bd48e S	39	* dev: IOMMU device
	40	* irq: Interrupt number
	41	* clk: The bus clock for this IOMMU hardware instance
	42	* pclk: The clock for the IOMMU bus interconnect
	43	* dev_node: list head in qcom_iommu_device_list
	44	* dom_node: list head for domain
	45	* ctx_list: list of 'struct msm_iommu_ctx_dev'
	46	* context_map: Bitmap to track allocated context banks
0720d1f0 SM	47	*/
0720d1f0 SM	48	struct msm_iommu_dev {
109bd48e	49	void __iomem *base;
a43d8c10	50	int ncb;
109bd48e S	51	struct device *dev;
	52	int irq;
	53	struct clk *clk;
	54	struct clk *pclk;
	55	struct list_head dev_node;
	56	struct list_head dom_node;
	57	struct list_head ctx_list;
	58	DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
42df43b3 JR	59
42df43b3 JR	60	struct iommu_device iommu;
0720d1f0 SM	61	};
	62
	63	/**
	64	* struct msm_iommu_ctx_dev - an IOMMU context bank instance
109bd48e	65	* of_node node ptr of client device
0720d1f0 SM	66	* num Index of this context bank within the hardware
	67	* mids List of Machine IDs that are to be mapped into this context
	68	* bank, terminated by -1. The MID is a set of signals on the
	69	* AXI bus that identifies the function associated with a specific
	70	* memory request. (See ARM spec).
109bd48e S	71	* num_mids Total number of mids
109bd48e S	72	* node list head in ctx_list
0720d1f0 SM	73	*/
0720d1f0 SM	74	struct msm_iommu_ctx_dev {
109bd48e	75	struct device_node *of_node;
0720d1f0 SM	76	int num;
0720d1f0 SM	77	int mids[MAX_NUM_MIDS];
109bd48e S	78	int num_mids;
109bd48e S	79	struct list_head list;
0720d1f0 SM	80	};
0720d1f0 SM	81
0720d1f0 SM	82	/*
	83	* Interrupt handler for the IOMMU context fault interrupt. Hooking the
	84	* interrupt is not supported in the API yet, but this will print an error
	85	* message and dump useful IOMMU registers.
	86	*/
	87	irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
	88
	89	#endif