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57d3f11c | 1 | // SPDX-License-Identifier: GPL-2.0 |
d25a2a16 | 2 | /* |
8128ac3b PG |
3 | * IOMMU API for Renesas VMSA-compatible IPMMU |
4 | * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
d25a2a16 | 5 | * |
17fe1618 | 6 | * Copyright (C) 2014-2020 Renesas Electronics Corporation |
d25a2a16 LP |
7 | */ |
8 | ||
dbb70692 | 9 | #include <linux/bitmap.h> |
d25a2a16 | 10 | #include <linux/delay.h> |
3ae47292 | 11 | #include <linux/dma-iommu.h> |
d25a2a16 LP |
12 | #include <linux/dma-mapping.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/export.h> | |
8128ac3b | 15 | #include <linux/init.h> |
d25a2a16 LP |
16 | #include <linux/interrupt.h> |
17 | #include <linux/io.h> | |
b77cf11f | 18 | #include <linux/io-pgtable.h> |
d25a2a16 | 19 | #include <linux/iommu.h> |
275f5053 | 20 | #include <linux/of.h> |
33f3ac9b | 21 | #include <linux/of_device.h> |
cda52fcd | 22 | #include <linux/of_iommu.h> |
7b2d5961 | 23 | #include <linux/of_platform.h> |
d25a2a16 LP |
24 | #include <linux/platform_device.h> |
25 | #include <linux/sizes.h> | |
26 | #include <linux/slab.h> | |
58b8e8bf | 27 | #include <linux/sys_soc.h> |
d25a2a16 | 28 | |
3ae47292 | 29 | #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) |
d25a2a16 LP |
30 | #include <asm/dma-iommu.h> |
31 | #include <asm/pgalloc.h> | |
49c875f0 RM |
32 | #else |
33 | #define arm_iommu_create_mapping(...) NULL | |
34 | #define arm_iommu_attach_device(...) -ENODEV | |
35 | #define arm_iommu_release_mapping(...) do {} while (0) | |
36 | #define arm_iommu_detach_device(...) do {} while (0) | |
3ae47292 | 37 | #endif |
d25a2a16 | 38 | |
da38e9ec GU |
39 | #define IPMMU_CTX_MAX 8U |
40 | #define IPMMU_CTX_INVALID -1 | |
41 | ||
42 | #define IPMMU_UTLB_MAX 48U | |
dbb70692 | 43 | |
33f3ac9b MD |
44 | struct ipmmu_features { |
45 | bool use_ns_alias_offset; | |
fd5140e2 | 46 | bool has_cache_leaf_nodes; |
5fd16341 | 47 | unsigned int number_of_contexts; |
b7f3f047 | 48 | unsigned int num_utlbs; |
f5c85891 | 49 | bool setup_imbuscr; |
c295f504 | 50 | bool twobit_imttbcr_sl0; |
2ae86955 | 51 | bool reserved_context; |
3623002f | 52 | bool cache_snoop; |
3dc28d9f YS |
53 | unsigned int ctx_offset_base; |
54 | unsigned int ctx_offset_stride; | |
1289f7f1 | 55 | unsigned int utlb_offset_base; |
33f3ac9b MD |
56 | }; |
57 | ||
d25a2a16 LP |
58 | struct ipmmu_vmsa_device { |
59 | struct device *dev; | |
60 | void __iomem *base; | |
01da21e5 | 61 | struct iommu_device iommu; |
fd5140e2 | 62 | struct ipmmu_vmsa_device *root; |
33f3ac9b | 63 | const struct ipmmu_features *features; |
5fd16341 | 64 | unsigned int num_ctx; |
dbb70692 MD |
65 | spinlock_t lock; /* Protects ctx and domains[] */ |
66 | DECLARE_BITMAP(ctx, IPMMU_CTX_MAX); | |
67 | struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; | |
da38e9ec | 68 | s8 utlb_ctx[IPMMU_UTLB_MAX]; |
d25a2a16 | 69 | |
b354c73e | 70 | struct iommu_group *group; |
d25a2a16 LP |
71 | struct dma_iommu_mapping *mapping; |
72 | }; | |
73 | ||
74 | struct ipmmu_vmsa_domain { | |
75 | struct ipmmu_vmsa_device *mmu; | |
5914c5fd | 76 | struct iommu_domain io_domain; |
d25a2a16 | 77 | |
f20ed39f LP |
78 | struct io_pgtable_cfg cfg; |
79 | struct io_pgtable_ops *iop; | |
80 | ||
d25a2a16 | 81 | unsigned int context_id; |
46583e8c | 82 | struct mutex mutex; /* Protects mappings */ |
d25a2a16 LP |
83 | }; |
84 | ||
5914c5fd JR |
85 | static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) |
86 | { | |
87 | return container_of(dom, struct ipmmu_vmsa_domain, io_domain); | |
88 | } | |
89 | ||
e4efe4a9 | 90 | static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) |
0fbc8b04 | 91 | { |
be568d6d | 92 | return dev_iommu_priv_get(dev); |
0fbc8b04 MD |
93 | } |
94 | ||
d25a2a16 LP |
95 | #define TLB_LOOP_TIMEOUT 100 /* 100us */ |
96 | ||
97 | /* ----------------------------------------------------------------------------- | |
98 | * Registers Definition | |
99 | */ | |
100 | ||
275f5053 LP |
101 | #define IM_NS_ALIAS_OFFSET 0x800 |
102 | ||
df9828aa YS |
103 | /* MMU "context" registers */ |
104 | #define IMCTR 0x0000 /* R-Car Gen2/3 */ | |
105 | #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */ | |
106 | #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ | |
107 | #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ | |
108 | ||
109 | #define IMTTBCR 0x0008 /* R-Car Gen2/3 */ | |
110 | #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */ | |
3623002f | 111 | #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */ |
3623002f | 112 | #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */ |
3623002f | 113 | #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */ |
5ca54fdc | 114 | #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */ |
df9828aa | 115 | #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */ |
d25a2a16 | 116 | |
df9828aa YS |
117 | #define IMBUSCR 0x000c /* R-Car Gen2 only */ |
118 | #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */ | |
119 | #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */ | |
d25a2a16 | 120 | |
df9828aa YS |
121 | #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */ |
122 | #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */ | |
d25a2a16 | 123 | |
df9828aa YS |
124 | #define IMSTR 0x0020 /* R-Car Gen2/3 */ |
125 | #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */ | |
126 | #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */ | |
127 | #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */ | |
128 | #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */ | |
d25a2a16 | 129 | |
df9828aa | 130 | #define IMMAIR0 0x0028 /* R-Car Gen2/3 */ |
d25a2a16 | 131 | |
df9828aa YS |
132 | #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */ |
133 | #define IMEUAR 0x0034 /* R-Car Gen3 only */ | |
d25a2a16 | 134 | |
df9828aa | 135 | /* uTLB registers */ |
ddbbddd7 | 136 | #define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n)) |
df9828aa YS |
137 | #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */ |
138 | #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */ | |
139 | #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */ | |
140 | #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */ | |
141 | #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */ | |
d25a2a16 | 142 | |
ddbbddd7 | 143 | #define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n)) |
df9828aa YS |
144 | #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */ |
145 | #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */ | |
d25a2a16 | 146 | |
fd5140e2 MD |
147 | /* ----------------------------------------------------------------------------- |
148 | * Root device handling | |
149 | */ | |
150 | ||
151 | static struct platform_driver ipmmu_driver; | |
152 | ||
153 | static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) | |
154 | { | |
155 | return mmu->root == mmu; | |
156 | } | |
157 | ||
158 | static int __ipmmu_check_device(struct device *dev, void *data) | |
159 | { | |
160 | struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); | |
161 | struct ipmmu_vmsa_device **rootp = data; | |
162 | ||
163 | if (ipmmu_is_root(mmu)) | |
164 | *rootp = mmu; | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static struct ipmmu_vmsa_device *ipmmu_find_root(void) | |
170 | { | |
171 | struct ipmmu_vmsa_device *root = NULL; | |
172 | ||
173 | return driver_for_each_device(&ipmmu_driver.driver, NULL, &root, | |
174 | __ipmmu_check_device) == 0 ? root : NULL; | |
175 | } | |
176 | ||
d25a2a16 LP |
177 | /* ----------------------------------------------------------------------------- |
178 | * Read/Write Access | |
179 | */ | |
180 | ||
181 | static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) | |
182 | { | |
183 | return ioread32(mmu->base + offset); | |
184 | } | |
185 | ||
186 | static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, | |
187 | u32 data) | |
188 | { | |
189 | iowrite32(data, mmu->base + offset); | |
190 | } | |
191 | ||
16d9454f YS |
192 | static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu, |
193 | unsigned int context_id, unsigned int reg) | |
194 | { | |
3dc28d9f YS |
195 | return mmu->features->ctx_offset_base + |
196 | context_id * mmu->features->ctx_offset_stride + reg; | |
16d9454f YS |
197 | } |
198 | ||
199 | static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu, | |
200 | unsigned int context_id, unsigned int reg) | |
201 | { | |
202 | return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg)); | |
203 | } | |
204 | ||
205 | static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu, | |
206 | unsigned int context_id, unsigned int reg, u32 data) | |
207 | { | |
208 | ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data); | |
209 | } | |
210 | ||
d574893a MD |
211 | static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain, |
212 | unsigned int reg) | |
d25a2a16 | 213 | { |
16d9454f | 214 | return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); |
d25a2a16 LP |
215 | } |
216 | ||
d574893a MD |
217 | static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain, |
218 | unsigned int reg, u32 data) | |
d25a2a16 | 219 | { |
16d9454f | 220 | ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); |
d25a2a16 LP |
221 | } |
222 | ||
d574893a MD |
223 | static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain, |
224 | unsigned int reg, u32 data) | |
225 | { | |
226 | if (domain->mmu != domain->mmu->root) | |
16d9454f | 227 | ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); |
d574893a | 228 | |
16d9454f | 229 | ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); |
d574893a MD |
230 | } |
231 | ||
3667c997 YS |
232 | static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg) |
233 | { | |
1289f7f1 | 234 | return mmu->features->utlb_offset_base + reg; |
3667c997 YS |
235 | } |
236 | ||
237 | static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu, | |
238 | unsigned int utlb, u32 data) | |
239 | { | |
240 | ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data); | |
241 | } | |
d574893a | 242 | |
3667c997 YS |
243 | static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu, |
244 | unsigned int utlb, u32 data) | |
245 | { | |
246 | ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data); | |
d574893a MD |
247 | } |
248 | ||
d25a2a16 LP |
249 | /* ----------------------------------------------------------------------------- |
250 | * TLB and microTLB Management | |
251 | */ | |
252 | ||
253 | /* Wait for any pending TLB invalidations to complete */ | |
254 | static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain) | |
255 | { | |
256 | unsigned int count = 0; | |
257 | ||
d574893a | 258 | while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) { |
d25a2a16 LP |
259 | cpu_relax(); |
260 | if (++count == TLB_LOOP_TIMEOUT) { | |
261 | dev_err_ratelimited(domain->mmu->dev, | |
262 | "TLB sync timed out -- MMU may be deadlocked\n"); | |
263 | return; | |
264 | } | |
265 | udelay(1); | |
266 | } | |
267 | } | |
268 | ||
269 | static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain) | |
270 | { | |
271 | u32 reg; | |
272 | ||
d574893a | 273 | reg = ipmmu_ctx_read_root(domain, IMCTR); |
d25a2a16 | 274 | reg |= IMCTR_FLUSH; |
d574893a | 275 | ipmmu_ctx_write_all(domain, IMCTR, reg); |
d25a2a16 LP |
276 | |
277 | ipmmu_tlb_sync(domain); | |
278 | } | |
279 | ||
280 | /* | |
281 | * Enable MMU translation for the microTLB. | |
282 | */ | |
283 | static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain, | |
192d2045 | 284 | unsigned int utlb) |
d25a2a16 LP |
285 | { |
286 | struct ipmmu_vmsa_device *mmu = domain->mmu; | |
287 | ||
192d2045 LP |
288 | /* |
289 | * TODO: Reference-count the microTLB as several bus masters can be | |
290 | * connected to the same microTLB. | |
291 | */ | |
292 | ||
d25a2a16 | 293 | /* TODO: What should we set the ASID to ? */ |
3667c997 | 294 | ipmmu_imuasid_write(mmu, utlb, 0); |
d25a2a16 | 295 | /* TODO: Do we need to flush the microTLB ? */ |
3667c997 YS |
296 | ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | |
297 | IMUCTR_FLUSH | IMUCTR_MMUEN); | |
da38e9ec | 298 | mmu->utlb_ctx[utlb] = domain->context_id; |
d25a2a16 LP |
299 | } |
300 | ||
301 | /* | |
302 | * Disable MMU translation for the microTLB. | |
303 | */ | |
304 | static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain, | |
192d2045 | 305 | unsigned int utlb) |
d25a2a16 LP |
306 | { |
307 | struct ipmmu_vmsa_device *mmu = domain->mmu; | |
308 | ||
3667c997 | 309 | ipmmu_imuctr_write(mmu, utlb, 0); |
da38e9ec | 310 | mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; |
d25a2a16 LP |
311 | } |
312 | ||
f20ed39f | 313 | static void ipmmu_tlb_flush_all(void *cookie) |
d25a2a16 | 314 | { |
f20ed39f LP |
315 | struct ipmmu_vmsa_domain *domain = cookie; |
316 | ||
317 | ipmmu_tlb_invalidate(domain); | |
318 | } | |
319 | ||
05aed941 WD |
320 | static void ipmmu_tlb_flush(unsigned long iova, size_t size, |
321 | size_t granule, void *cookie) | |
f20ed39f | 322 | { |
05aed941 | 323 | ipmmu_tlb_flush_all(cookie); |
f20ed39f LP |
324 | } |
325 | ||
298f7889 | 326 | static const struct iommu_flush_ops ipmmu_flush_ops = { |
f20ed39f | 327 | .tlb_flush_all = ipmmu_tlb_flush_all, |
05aed941 WD |
328 | .tlb_flush_walk = ipmmu_tlb_flush, |
329 | .tlb_flush_leaf = ipmmu_tlb_flush, | |
f20ed39f LP |
330 | }; |
331 | ||
d25a2a16 LP |
332 | /* ----------------------------------------------------------------------------- |
333 | * Domain/Context Management | |
334 | */ | |
335 | ||
dbb70692 MD |
336 | static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu, |
337 | struct ipmmu_vmsa_domain *domain) | |
338 | { | |
339 | unsigned long flags; | |
340 | int ret; | |
341 | ||
342 | spin_lock_irqsave(&mmu->lock, flags); | |
343 | ||
5fd16341 MD |
344 | ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); |
345 | if (ret != mmu->num_ctx) { | |
dbb70692 MD |
346 | mmu->domains[ret] = domain; |
347 | set_bit(ret, mmu->ctx); | |
5fd16341 MD |
348 | } else |
349 | ret = -EBUSY; | |
dbb70692 MD |
350 | |
351 | spin_unlock_irqrestore(&mmu->lock, flags); | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
a175a67d OT |
356 | static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, |
357 | unsigned int context_id) | |
358 | { | |
359 | unsigned long flags; | |
360 | ||
361 | spin_lock_irqsave(&mmu->lock, flags); | |
362 | ||
363 | clear_bit(context_id, mmu->ctx); | |
364 | mmu->domains[context_id] = NULL; | |
365 | ||
366 | spin_unlock_irqrestore(&mmu->lock, flags); | |
367 | } | |
368 | ||
892db541 | 369 | static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) |
d25a2a16 | 370 | { |
f64232ee | 371 | u64 ttbr; |
c295f504 | 372 | u32 tmp; |
a175a67d | 373 | |
d25a2a16 | 374 | /* TTBR0 */ |
d1e5f26f | 375 | ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; |
d574893a MD |
376 | ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); |
377 | ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); | |
d25a2a16 LP |
378 | |
379 | /* | |
380 | * TTBCR | |
3623002f HNP |
381 | * We use long descriptors and allocate the whole 32-bit VA space to |
382 | * TTBR0. | |
d25a2a16 | 383 | */ |
c295f504 MD |
384 | if (domain->mmu->features->twobit_imttbcr_sl0) |
385 | tmp = IMTTBCR_SL0_TWOBIT_LVL_1; | |
386 | else | |
387 | tmp = IMTTBCR_SL0_LVL_1; | |
388 | ||
3623002f HNP |
389 | if (domain->mmu->features->cache_snoop) |
390 | tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA | | |
391 | IMTTBCR_IRGN0_WB_WA; | |
392 | ||
393 | ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp); | |
d25a2a16 | 394 | |
f20ed39f | 395 | /* MAIR0 */ |
d574893a | 396 | ipmmu_ctx_write_root(domain, IMMAIR0, |
205577ab | 397 | domain->cfg.arm_lpae_s1_cfg.mair); |
d25a2a16 LP |
398 | |
399 | /* IMBUSCR */ | |
f5c85891 MD |
400 | if (domain->mmu->features->setup_imbuscr) |
401 | ipmmu_ctx_write_root(domain, IMBUSCR, | |
402 | ipmmu_ctx_read_root(domain, IMBUSCR) & | |
403 | ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK)); | |
d25a2a16 LP |
404 | |
405 | /* | |
406 | * IMSTR | |
407 | * Clear all interrupt flags. | |
408 | */ | |
d574893a | 409 | ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR)); |
d25a2a16 LP |
410 | |
411 | /* | |
412 | * IMCTR | |
413 | * Enable the MMU and interrupt generation. The long-descriptor | |
414 | * translation table format doesn't use TEX remapping. Don't enable AF | |
415 | * software management as we have no use for it. Flush the TLB as | |
416 | * required when modifying the context registers. | |
417 | */ | |
d574893a MD |
418 | ipmmu_ctx_write_all(domain, IMCTR, |
419 | IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN); | |
892db541 GU |
420 | } |
421 | ||
422 | static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) | |
423 | { | |
424 | int ret; | |
425 | ||
426 | /* | |
427 | * Allocate the page table operations. | |
428 | * | |
429 | * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory | |
430 | * access, Long-descriptor format" that the NStable bit being set in a | |
431 | * table descriptor will result in the NStable and NS bits of all child | |
432 | * entries being ignored and considered as being set. The IPMMU seems | |
433 | * not to comply with this, as it generates a secure access page fault | |
434 | * if any of the NStable and NS bits isn't set when running in | |
435 | * non-secure mode. | |
436 | */ | |
437 | domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; | |
438 | domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; | |
439 | domain->cfg.ias = 32; | |
440 | domain->cfg.oas = 40; | |
298f7889 | 441 | domain->cfg.tlb = &ipmmu_flush_ops; |
892db541 GU |
442 | domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); |
443 | domain->io_domain.geometry.force_aperture = true; | |
444 | /* | |
445 | * TODO: Add support for coherent walk through CCI with DVM and remove | |
446 | * cache handling. For now, delegate it to the io-pgtable code. | |
447 | */ | |
3430abd6 | 448 | domain->cfg.coherent_walk = false; |
892db541 GU |
449 | domain->cfg.iommu_dev = domain->mmu->root->dev; |
450 | ||
451 | /* | |
452 | * Find an unused context. | |
453 | */ | |
454 | ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); | |
455 | if (ret < 0) | |
456 | return ret; | |
457 | ||
458 | domain->context_id = ret; | |
459 | ||
460 | domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, | |
461 | domain); | |
462 | if (!domain->iop) { | |
463 | ipmmu_domain_free_context(domain->mmu->root, | |
464 | domain->context_id); | |
465 | return -EINVAL; | |
466 | } | |
d25a2a16 | 467 | |
892db541 | 468 | ipmmu_domain_setup_context(domain); |
d25a2a16 LP |
469 | return 0; |
470 | } | |
471 | ||
472 | static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) | |
473 | { | |
e5b78f2e GU |
474 | if (!domain->mmu) |
475 | return; | |
476 | ||
d25a2a16 LP |
477 | /* |
478 | * Disable the context. Flush the TLB as required when modifying the | |
479 | * context registers. | |
480 | * | |
481 | * TODO: Is TLB flush really needed ? | |
482 | */ | |
d574893a | 483 | ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH); |
d25a2a16 | 484 | ipmmu_tlb_sync(domain); |
fd5140e2 | 485 | ipmmu_domain_free_context(domain->mmu->root, domain->context_id); |
d25a2a16 LP |
486 | } |
487 | ||
488 | /* ----------------------------------------------------------------------------- | |
489 | * Fault Handling | |
490 | */ | |
491 | ||
492 | static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain) | |
493 | { | |
494 | const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF; | |
495 | struct ipmmu_vmsa_device *mmu = domain->mmu; | |
82576aa8 | 496 | unsigned long iova; |
d25a2a16 | 497 | u32 status; |
d25a2a16 | 498 | |
d574893a | 499 | status = ipmmu_ctx_read_root(domain, IMSTR); |
d25a2a16 LP |
500 | if (!(status & err_mask)) |
501 | return IRQ_NONE; | |
502 | ||
82576aa8 GU |
503 | iova = ipmmu_ctx_read_root(domain, IMELAR); |
504 | if (IS_ENABLED(CONFIG_64BIT)) | |
505 | iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32; | |
d25a2a16 LP |
506 | |
507 | /* | |
508 | * Clear the error status flags. Unlike traditional interrupt flag | |
509 | * registers that must be cleared by writing 1, this status register | |
510 | * seems to require 0. The error address register must be read before, | |
511 | * otherwise its value will be 0. | |
512 | */ | |
d574893a | 513 | ipmmu_ctx_write_root(domain, IMSTR, 0); |
d25a2a16 LP |
514 | |
515 | /* Log fatal errors. */ | |
516 | if (status & IMSTR_MHIT) | |
82576aa8 | 517 | dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", |
d25a2a16 LP |
518 | iova); |
519 | if (status & IMSTR_ABORT) | |
82576aa8 | 520 | dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", |
d25a2a16 LP |
521 | iova); |
522 | ||
523 | if (!(status & (IMSTR_PF | IMSTR_TF))) | |
524 | return IRQ_NONE; | |
525 | ||
526 | /* | |
527 | * Try to handle page faults and translation faults. | |
528 | * | |
529 | * TODO: We need to look up the faulty device based on the I/O VA. Use | |
530 | * the IOMMU device for now. | |
531 | */ | |
5914c5fd | 532 | if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) |
d25a2a16 LP |
533 | return IRQ_HANDLED; |
534 | ||
535 | dev_err_ratelimited(mmu->dev, | |
82576aa8 | 536 | "Unhandled fault: status 0x%08x iova 0x%lx\n", |
d25a2a16 LP |
537 | status, iova); |
538 | ||
539 | return IRQ_HANDLED; | |
540 | } | |
541 | ||
542 | static irqreturn_t ipmmu_irq(int irq, void *dev) | |
543 | { | |
544 | struct ipmmu_vmsa_device *mmu = dev; | |
dbb70692 MD |
545 | irqreturn_t status = IRQ_NONE; |
546 | unsigned int i; | |
547 | unsigned long flags; | |
d25a2a16 | 548 | |
dbb70692 MD |
549 | spin_lock_irqsave(&mmu->lock, flags); |
550 | ||
551 | /* | |
552 | * Check interrupts for all active contexts. | |
553 | */ | |
5fd16341 | 554 | for (i = 0; i < mmu->num_ctx; i++) { |
dbb70692 MD |
555 | if (!mmu->domains[i]) |
556 | continue; | |
557 | if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) | |
558 | status = IRQ_HANDLED; | |
559 | } | |
d25a2a16 | 560 | |
dbb70692 | 561 | spin_unlock_irqrestore(&mmu->lock, flags); |
d25a2a16 | 562 | |
dbb70692 | 563 | return status; |
d25a2a16 LP |
564 | } |
565 | ||
d25a2a16 LP |
566 | /* ----------------------------------------------------------------------------- |
567 | * IOMMU Operations | |
568 | */ | |
569 | ||
8e73bf65 | 570 | static struct iommu_domain *__ipmmu_domain_alloc(unsigned type) |
d25a2a16 LP |
571 | { |
572 | struct ipmmu_vmsa_domain *domain; | |
573 | ||
574 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
575 | if (!domain) | |
5914c5fd | 576 | return NULL; |
d25a2a16 | 577 | |
46583e8c | 578 | mutex_init(&domain->mutex); |
d25a2a16 | 579 | |
5914c5fd | 580 | return &domain->io_domain; |
d25a2a16 LP |
581 | } |
582 | ||
1c7e7c02 RM |
583 | static struct iommu_domain *ipmmu_domain_alloc(unsigned type) |
584 | { | |
585 | struct iommu_domain *io_domain = NULL; | |
586 | ||
587 | switch (type) { | |
588 | case IOMMU_DOMAIN_UNMANAGED: | |
589 | io_domain = __ipmmu_domain_alloc(type); | |
590 | break; | |
591 | ||
592 | case IOMMU_DOMAIN_DMA: | |
593 | io_domain = __ipmmu_domain_alloc(type); | |
594 | if (io_domain && iommu_get_dma_cookie(io_domain)) { | |
595 | kfree(io_domain); | |
596 | io_domain = NULL; | |
597 | } | |
598 | break; | |
599 | } | |
600 | ||
601 | return io_domain; | |
602 | } | |
603 | ||
5914c5fd | 604 | static void ipmmu_domain_free(struct iommu_domain *io_domain) |
d25a2a16 | 605 | { |
5914c5fd | 606 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
d25a2a16 LP |
607 | |
608 | /* | |
609 | * Free the domain resources. We assume that all devices have already | |
610 | * been detached. | |
611 | */ | |
1c7e7c02 | 612 | iommu_put_dma_cookie(io_domain); |
d25a2a16 | 613 | ipmmu_domain_destroy_context(domain); |
f20ed39f | 614 | free_io_pgtable_ops(domain->iop); |
d25a2a16 LP |
615 | kfree(domain); |
616 | } | |
617 | ||
618 | static int ipmmu_attach_device(struct iommu_domain *io_domain, | |
619 | struct device *dev) | |
620 | { | |
df903655 | 621 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
e4efe4a9 | 622 | struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); |
5914c5fd | 623 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
a166d31e | 624 | unsigned int i; |
d25a2a16 LP |
625 | int ret = 0; |
626 | ||
e4efe4a9 | 627 | if (!mmu) { |
d25a2a16 LP |
628 | dev_err(dev, "Cannot attach to IPMMU\n"); |
629 | return -ENXIO; | |
630 | } | |
631 | ||
46583e8c | 632 | mutex_lock(&domain->mutex); |
d25a2a16 LP |
633 | |
634 | if (!domain->mmu) { | |
635 | /* The domain hasn't been used yet, initialize it. */ | |
636 | domain->mmu = mmu; | |
637 | ret = ipmmu_domain_init_context(domain); | |
5fd16341 MD |
638 | if (ret < 0) { |
639 | dev_err(dev, "Unable to initialize IPMMU context\n"); | |
640 | domain->mmu = NULL; | |
641 | } else { | |
642 | dev_info(dev, "Using IPMMU context %u\n", | |
643 | domain->context_id); | |
644 | } | |
d25a2a16 LP |
645 | } else if (domain->mmu != mmu) { |
646 | /* | |
647 | * Something is wrong, we can't attach two devices using | |
648 | * different IOMMUs to the same domain. | |
649 | */ | |
650 | dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", | |
651 | dev_name(mmu->dev), dev_name(domain->mmu->dev)); | |
652 | ret = -EINVAL; | |
3ae47292 MD |
653 | } else |
654 | dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); | |
d25a2a16 | 655 | |
46583e8c | 656 | mutex_unlock(&domain->mutex); |
d25a2a16 LP |
657 | |
658 | if (ret < 0) | |
659 | return ret; | |
660 | ||
7b2d5961 MD |
661 | for (i = 0; i < fwspec->num_ids; ++i) |
662 | ipmmu_utlb_enable(domain, fwspec->ids[i]); | |
d25a2a16 LP |
663 | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static void ipmmu_detach_device(struct iommu_domain *io_domain, | |
668 | struct device *dev) | |
669 | { | |
df903655 | 670 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
5914c5fd | 671 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
a166d31e | 672 | unsigned int i; |
d25a2a16 | 673 | |
7b2d5961 MD |
674 | for (i = 0; i < fwspec->num_ids; ++i) |
675 | ipmmu_utlb_disable(domain, fwspec->ids[i]); | |
d25a2a16 LP |
676 | |
677 | /* | |
678 | * TODO: Optimize by disabling the context when no device is attached. | |
679 | */ | |
680 | } | |
681 | ||
682 | static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova, | |
781ca2de | 683 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
d25a2a16 | 684 | { |
5914c5fd | 685 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
d25a2a16 LP |
686 | |
687 | if (!domain) | |
688 | return -ENODEV; | |
689 | ||
f20ed39f | 690 | return domain->iop->map(domain->iop, iova, paddr, size, prot); |
d25a2a16 LP |
691 | } |
692 | ||
693 | static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova, | |
56f8af5e | 694 | size_t size, struct iommu_iotlb_gather *gather) |
d25a2a16 | 695 | { |
5914c5fd | 696 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
d25a2a16 | 697 | |
a2d3a382 | 698 | return domain->iop->unmap(domain->iop, iova, size, gather); |
d25a2a16 LP |
699 | } |
700 | ||
56f8af5e | 701 | static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain) |
32b12449 RM |
702 | { |
703 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); | |
704 | ||
705 | if (domain->mmu) | |
706 | ipmmu_tlb_flush_all(domain); | |
707 | } | |
708 | ||
56f8af5e WD |
709 | static void ipmmu_iotlb_sync(struct iommu_domain *io_domain, |
710 | struct iommu_iotlb_gather *gather) | |
711 | { | |
712 | ipmmu_flush_iotlb_all(io_domain); | |
713 | } | |
714 | ||
d25a2a16 LP |
715 | static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, |
716 | dma_addr_t iova) | |
717 | { | |
5914c5fd | 718 | struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); |
d25a2a16 LP |
719 | |
720 | /* TODO: Is locking needed ? */ | |
721 | ||
f20ed39f | 722 | return domain->iop->iova_to_phys(domain->iop, iova); |
d25a2a16 LP |
723 | } |
724 | ||
7b2d5961 MD |
725 | static int ipmmu_init_platform_device(struct device *dev, |
726 | struct of_phandle_args *args) | |
d25a2a16 | 727 | { |
7b2d5961 | 728 | struct platform_device *ipmmu_pdev; |
bb590c90 | 729 | |
7b2d5961 MD |
730 | ipmmu_pdev = of_find_device_by_node(args->np); |
731 | if (!ipmmu_pdev) | |
bb590c90 LP |
732 | return -ENODEV; |
733 | ||
be568d6d | 734 | dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev)); |
383fef5f | 735 | |
383fef5f | 736 | return 0; |
58b8e8bf MD |
737 | } |
738 | ||
0b8ac140 | 739 | static const struct soc_device_attribute soc_rcar_gen3[] = { |
60fb0083 | 740 | { .soc_id = "r8a774a1", }, |
757f26a3 | 741 | { .soc_id = "r8a774b1", }, |
b6d39cd8 | 742 | { .soc_id = "r8a774c0", }, |
4b2aa7a6 | 743 | { .soc_id = "r8a774e1", }, |
58b8e8bf | 744 | { .soc_id = "r8a7795", }, |
0b8ac140 | 745 | { .soc_id = "r8a7796", }, |
98dbffd3 | 746 | { .soc_id = "r8a77965", }, |
3701c123 | 747 | { .soc_id = "r8a77970", }, |
b0c32912 | 748 | { .soc_id = "r8a77990", }, |
3701c123 | 749 | { .soc_id = "r8a77995", }, |
58b8e8bf MD |
750 | { /* sentinel */ } |
751 | }; | |
752 | ||
b7ee92c6 | 753 | static const struct soc_device_attribute soc_rcar_gen3_whitelist[] = { |
757f26a3 | 754 | { .soc_id = "r8a774b1", }, |
b6d39cd8 | 755 | { .soc_id = "r8a774c0", }, |
4b2aa7a6 | 756 | { .soc_id = "r8a774e1", }, |
b7ee92c6 | 757 | { .soc_id = "r8a7795", .revision = "ES3.*" }, |
17fe1618 | 758 | { .soc_id = "r8a77961", }, |
b7ee92c6 YS |
759 | { .soc_id = "r8a77965", }, |
760 | { .soc_id = "r8a77990", }, | |
3701c123 | 761 | { .soc_id = "r8a77995", }, |
58b8e8bf MD |
762 | { /* sentinel */ } |
763 | }; | |
764 | ||
80759649 YS |
765 | static const char * const rcar_gen3_slave_whitelist[] = { |
766 | }; | |
767 | ||
b7ee92c6 YS |
768 | static bool ipmmu_slave_whitelist(struct device *dev) |
769 | { | |
80759649 YS |
770 | unsigned int i; |
771 | ||
b7ee92c6 YS |
772 | /* |
773 | * For R-Car Gen3 use a white list to opt-in slave devices. | |
774 | * For Other SoCs, this returns true anyway. | |
775 | */ | |
776 | if (!soc_device_match(soc_rcar_gen3)) | |
777 | return true; | |
778 | ||
779 | /* Check whether this R-Car Gen3 can use the IPMMU correctly or not */ | |
780 | if (!soc_device_match(soc_rcar_gen3_whitelist)) | |
781 | return false; | |
782 | ||
80759649 YS |
783 | /* Check whether this slave device can work with the IPMMU */ |
784 | for (i = 0; i < ARRAY_SIZE(rcar_gen3_slave_whitelist); i++) { | |
785 | if (!strcmp(dev_name(dev), rcar_gen3_slave_whitelist[i])) | |
786 | return true; | |
787 | } | |
788 | ||
789 | /* Otherwise, do not allow use of IPMMU */ | |
b7ee92c6 YS |
790 | return false; |
791 | } | |
792 | ||
49558da0 MD |
793 | static int ipmmu_of_xlate(struct device *dev, |
794 | struct of_phandle_args *spec) | |
795 | { | |
b7ee92c6 | 796 | if (!ipmmu_slave_whitelist(dev)) |
58b8e8bf MD |
797 | return -ENODEV; |
798 | ||
7b2d5961 MD |
799 | iommu_fwspec_add_ids(dev, spec->args, 1); |
800 | ||
49558da0 | 801 | /* Initialize once - xlate() will call multiple times */ |
e4efe4a9 | 802 | if (to_ipmmu(dev)) |
49558da0 MD |
803 | return 0; |
804 | ||
7b2d5961 | 805 | return ipmmu_init_platform_device(dev, spec); |
49558da0 MD |
806 | } |
807 | ||
49c875f0 | 808 | static int ipmmu_init_arm_mapping(struct device *dev) |
383fef5f | 809 | { |
e4efe4a9 | 810 | struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); |
383fef5f MD |
811 | int ret; |
812 | ||
d25a2a16 LP |
813 | /* |
814 | * Create the ARM mapping, used by the ARM DMA mapping core to allocate | |
815 | * VAs. This will allocate a corresponding IOMMU domain. | |
816 | * | |
817 | * TODO: | |
818 | * - Create one mapping per context (TLB). | |
819 | * - Make the mapping size configurable ? We currently use a 2GB mapping | |
820 | * at a 1GB offset to ensure that NULL VAs will fault. | |
821 | */ | |
822 | if (!mmu->mapping) { | |
823 | struct dma_iommu_mapping *mapping; | |
824 | ||
825 | mapping = arm_iommu_create_mapping(&platform_bus_type, | |
720b0cef | 826 | SZ_1G, SZ_2G); |
d25a2a16 LP |
827 | if (IS_ERR(mapping)) { |
828 | dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); | |
b8f80bff LP |
829 | ret = PTR_ERR(mapping); |
830 | goto error; | |
d25a2a16 LP |
831 | } |
832 | ||
833 | mmu->mapping = mapping; | |
834 | } | |
835 | ||
836 | /* Attach the ARM VA mapping to the device. */ | |
837 | ret = arm_iommu_attach_device(dev, mmu->mapping); | |
838 | if (ret < 0) { | |
839 | dev_err(dev, "Failed to attach device to VA mapping\n"); | |
840 | goto error; | |
841 | } | |
842 | ||
843 | return 0; | |
844 | ||
845 | error: | |
49c875f0 | 846 | if (mmu->mapping) |
383fef5f | 847 | arm_iommu_release_mapping(mmu->mapping); |
a166d31e | 848 | |
d25a2a16 LP |
849 | return ret; |
850 | } | |
851 | ||
6580c8a7 | 852 | static struct iommu_device *ipmmu_probe_device(struct device *dev) |
3ae47292 | 853 | { |
80eaa9f5 | 854 | struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); |
3ae47292 | 855 | |
0fbc8b04 MD |
856 | /* |
857 | * Only let through devices that have been verified in xlate() | |
0fbc8b04 | 858 | */ |
80eaa9f5 | 859 | if (!mmu) |
6580c8a7 | 860 | return ERR_PTR(-ENODEV); |
3ae47292 | 861 | |
6580c8a7 JR |
862 | return &mmu->iommu; |
863 | } | |
864 | ||
865 | static void ipmmu_probe_finalize(struct device *dev) | |
866 | { | |
867 | int ret = 0; | |
868 | ||
869 | if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)) | |
80eaa9f5 | 870 | ret = ipmmu_init_arm_mapping(dev); |
3ae47292 | 871 | |
6580c8a7 JR |
872 | if (ret) |
873 | dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); | |
3ae47292 MD |
874 | } |
875 | ||
6580c8a7 | 876 | static void ipmmu_release_device(struct device *dev) |
3ae47292 | 877 | { |
49c875f0 | 878 | arm_iommu_detach_device(dev); |
3ae47292 MD |
879 | } |
880 | ||
b354c73e | 881 | static struct iommu_group *ipmmu_find_group(struct device *dev) |
3ae47292 | 882 | { |
e4efe4a9 | 883 | struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); |
3ae47292 | 884 | struct iommu_group *group; |
3ae47292 | 885 | |
e4efe4a9 RM |
886 | if (mmu->group) |
887 | return iommu_group_ref_get(mmu->group); | |
b354c73e RM |
888 | |
889 | group = iommu_group_alloc(); | |
890 | if (!IS_ERR(group)) | |
e4efe4a9 | 891 | mmu->group = group; |
3ae47292 MD |
892 | |
893 | return group; | |
894 | } | |
895 | ||
3ae47292 | 896 | static const struct iommu_ops ipmmu_ops = { |
1c7e7c02 RM |
897 | .domain_alloc = ipmmu_domain_alloc, |
898 | .domain_free = ipmmu_domain_free, | |
3ae47292 MD |
899 | .attach_dev = ipmmu_attach_device, |
900 | .detach_dev = ipmmu_detach_device, | |
901 | .map = ipmmu_map, | |
902 | .unmap = ipmmu_unmap, | |
56f8af5e | 903 | .flush_iotlb_all = ipmmu_flush_iotlb_all, |
32b12449 | 904 | .iotlb_sync = ipmmu_iotlb_sync, |
3ae47292 | 905 | .iova_to_phys = ipmmu_iova_to_phys, |
6580c8a7 JR |
906 | .probe_device = ipmmu_probe_device, |
907 | .release_device = ipmmu_release_device, | |
908 | .probe_finalize = ipmmu_probe_finalize, | |
2ba20b5a AB |
909 | .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) |
910 | ? generic_device_group : ipmmu_find_group, | |
3ae47292 | 911 | .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, |
49558da0 | 912 | .of_xlate = ipmmu_of_xlate, |
3ae47292 MD |
913 | }; |
914 | ||
d25a2a16 LP |
915 | /* ----------------------------------------------------------------------------- |
916 | * Probe/remove and init | |
917 | */ | |
918 | ||
919 | static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) | |
920 | { | |
921 | unsigned int i; | |
922 | ||
923 | /* Disable all contexts. */ | |
5fd16341 | 924 | for (i = 0; i < mmu->num_ctx; ++i) |
16d9454f | 925 | ipmmu_ctx_write(mmu, i, IMCTR, 0); |
d25a2a16 LP |
926 | } |
927 | ||
33f3ac9b MD |
928 | static const struct ipmmu_features ipmmu_features_default = { |
929 | .use_ns_alias_offset = true, | |
fd5140e2 | 930 | .has_cache_leaf_nodes = false, |
5fd16341 | 931 | .number_of_contexts = 1, /* software only tested with one context */ |
b7f3f047 | 932 | .num_utlbs = 32, |
f5c85891 | 933 | .setup_imbuscr = true, |
c295f504 | 934 | .twobit_imttbcr_sl0 = false, |
2ae86955 | 935 | .reserved_context = false, |
3623002f | 936 | .cache_snoop = true, |
3dc28d9f YS |
937 | .ctx_offset_base = 0, |
938 | .ctx_offset_stride = 0x40, | |
1289f7f1 | 939 | .utlb_offset_base = 0, |
33f3ac9b MD |
940 | }; |
941 | ||
0b8ac140 | 942 | static const struct ipmmu_features ipmmu_features_rcar_gen3 = { |
58b8e8bf MD |
943 | .use_ns_alias_offset = false, |
944 | .has_cache_leaf_nodes = true, | |
945 | .number_of_contexts = 8, | |
b7f3f047 | 946 | .num_utlbs = 48, |
58b8e8bf MD |
947 | .setup_imbuscr = false, |
948 | .twobit_imttbcr_sl0 = true, | |
2ae86955 | 949 | .reserved_context = true, |
3623002f | 950 | .cache_snoop = false, |
3dc28d9f YS |
951 | .ctx_offset_base = 0, |
952 | .ctx_offset_stride = 0x40, | |
1289f7f1 | 953 | .utlb_offset_base = 0, |
58b8e8bf MD |
954 | }; |
955 | ||
33f3ac9b MD |
956 | static const struct of_device_id ipmmu_of_ids[] = { |
957 | { | |
958 | .compatible = "renesas,ipmmu-vmsa", | |
959 | .data = &ipmmu_features_default, | |
60fb0083 FC |
960 | }, { |
961 | .compatible = "renesas,ipmmu-r8a774a1", | |
962 | .data = &ipmmu_features_rcar_gen3, | |
757f26a3 BD |
963 | }, { |
964 | .compatible = "renesas,ipmmu-r8a774b1", | |
965 | .data = &ipmmu_features_rcar_gen3, | |
b6d39cd8 FC |
966 | }, { |
967 | .compatible = "renesas,ipmmu-r8a774c0", | |
968 | .data = &ipmmu_features_rcar_gen3, | |
4b2aa7a6 MCR |
969 | }, { |
970 | .compatible = "renesas,ipmmu-r8a774e1", | |
971 | .data = &ipmmu_features_rcar_gen3, | |
58b8e8bf MD |
972 | }, { |
973 | .compatible = "renesas,ipmmu-r8a7795", | |
0b8ac140 MD |
974 | .data = &ipmmu_features_rcar_gen3, |
975 | }, { | |
976 | .compatible = "renesas,ipmmu-r8a7796", | |
977 | .data = &ipmmu_features_rcar_gen3, | |
17fe1618 YS |
978 | }, { |
979 | .compatible = "renesas,ipmmu-r8a77961", | |
980 | .data = &ipmmu_features_rcar_gen3, | |
98dbffd3 JM |
981 | }, { |
982 | .compatible = "renesas,ipmmu-r8a77965", | |
983 | .data = &ipmmu_features_rcar_gen3, | |
3701c123 SH |
984 | }, { |
985 | .compatible = "renesas,ipmmu-r8a77970", | |
986 | .data = &ipmmu_features_rcar_gen3, | |
b0c32912 HNP |
987 | }, { |
988 | .compatible = "renesas,ipmmu-r8a77990", | |
989 | .data = &ipmmu_features_rcar_gen3, | |
3701c123 SH |
990 | }, { |
991 | .compatible = "renesas,ipmmu-r8a77995", | |
992 | .data = &ipmmu_features_rcar_gen3, | |
33f3ac9b MD |
993 | }, { |
994 | /* Terminator */ | |
995 | }, | |
996 | }; | |
997 | ||
d25a2a16 LP |
998 | static int ipmmu_probe(struct platform_device *pdev) |
999 | { | |
1000 | struct ipmmu_vmsa_device *mmu; | |
1001 | struct resource *res; | |
1002 | int irq; | |
1003 | int ret; | |
1004 | ||
d25a2a16 LP |
1005 | mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); |
1006 | if (!mmu) { | |
1007 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
1008 | return -ENOMEM; | |
1009 | } | |
1010 | ||
1011 | mmu->dev = &pdev->dev; | |
dbb70692 MD |
1012 | spin_lock_init(&mmu->lock); |
1013 | bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); | |
33f3ac9b | 1014 | mmu->features = of_device_get_match_data(&pdev->dev); |
da38e9ec | 1015 | memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); |
1c894225 | 1016 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); |
d25a2a16 LP |
1017 | |
1018 | /* Map I/O memory and request IRQ. */ | |
1019 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1020 | mmu->base = devm_ioremap_resource(&pdev->dev, res); | |
1021 | if (IS_ERR(mmu->base)) | |
1022 | return PTR_ERR(mmu->base); | |
1023 | ||
275f5053 LP |
1024 | /* |
1025 | * The IPMMU has two register banks, for secure and non-secure modes. | |
1026 | * The bank mapped at the beginning of the IPMMU address space | |
1027 | * corresponds to the running mode of the CPU. When running in secure | |
1028 | * mode the non-secure register bank is also available at an offset. | |
1029 | * | |
1030 | * Secure mode operation isn't clearly documented and is thus currently | |
1031 | * not implemented in the driver. Furthermore, preliminary tests of | |
1032 | * non-secure operation with the main register bank were not successful. | |
1033 | * Offset the registers base unconditionally to point to the non-secure | |
1034 | * alias space for now. | |
1035 | */ | |
33f3ac9b MD |
1036 | if (mmu->features->use_ns_alias_offset) |
1037 | mmu->base += IM_NS_ALIAS_OFFSET; | |
275f5053 | 1038 | |
b43e0d8a | 1039 | mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); |
5fd16341 | 1040 | |
fd5140e2 MD |
1041 | /* |
1042 | * Determine if this IPMMU instance is a root device by checking for | |
1043 | * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. | |
1044 | */ | |
1045 | if (!mmu->features->has_cache_leaf_nodes || | |
1046 | !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL)) | |
1047 | mmu->root = mmu; | |
1048 | else | |
1049 | mmu->root = ipmmu_find_root(); | |
d25a2a16 | 1050 | |
fd5140e2 MD |
1051 | /* |
1052 | * Wait until the root device has been registered for sure. | |
1053 | */ | |
1054 | if (!mmu->root) | |
1055 | return -EPROBE_DEFER; | |
1056 | ||
1057 | /* Root devices have mandatory IRQs */ | |
1058 | if (ipmmu_is_root(mmu)) { | |
ec37d4e9 | 1059 | irq = platform_get_irq(pdev, 0); |
565d4542 | 1060 | if (irq < 0) |
fd5140e2 | 1061 | return irq; |
fd5140e2 MD |
1062 | |
1063 | ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, | |
1064 | dev_name(&pdev->dev), mmu); | |
1065 | if (ret < 0) { | |
1066 | dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); | |
1067 | return ret; | |
1068 | } | |
1069 | ||
1070 | ipmmu_device_reset(mmu); | |
2ae86955 YS |
1071 | |
1072 | if (mmu->features->reserved_context) { | |
1073 | dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); | |
1074 | set_bit(0, mmu->ctx); | |
1075 | } | |
fd5140e2 | 1076 | } |
d25a2a16 | 1077 | |
cda52fcd MD |
1078 | /* |
1079 | * Register the IPMMU to the IOMMU subsystem in the following cases: | |
1080 | * - R-Car Gen2 IPMMU (all devices registered) | |
1081 | * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) | |
1082 | */ | |
1083 | if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { | |
1084 | ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, | |
1085 | dev_name(&pdev->dev)); | |
1086 | if (ret) | |
1087 | return ret; | |
7af9a5fd | 1088 | |
cda52fcd MD |
1089 | iommu_device_set_ops(&mmu->iommu, &ipmmu_ops); |
1090 | iommu_device_set_fwnode(&mmu->iommu, | |
1091 | &pdev->dev.of_node->fwnode); | |
01da21e5 | 1092 | |
cda52fcd MD |
1093 | ret = iommu_device_register(&mmu->iommu); |
1094 | if (ret) | |
1095 | return ret; | |
1096 | ||
1097 | #if defined(CONFIG_IOMMU_DMA) | |
1098 | if (!iommu_present(&platform_bus_type)) | |
1099 | bus_set_iommu(&platform_bus_type, &ipmmu_ops); | |
1100 | #endif | |
1101 | } | |
01da21e5 | 1102 | |
d25a2a16 LP |
1103 | /* |
1104 | * We can't create the ARM mapping here as it requires the bus to have | |
1105 | * an IOMMU, which only happens when bus_set_iommu() is called in | |
1106 | * ipmmu_init() after the probe function returns. | |
1107 | */ | |
1108 | ||
d25a2a16 LP |
1109 | platform_set_drvdata(pdev, mmu); |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static int ipmmu_remove(struct platform_device *pdev) | |
1115 | { | |
1116 | struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev); | |
1117 | ||
7af9a5fd | 1118 | iommu_device_sysfs_remove(&mmu->iommu); |
01da21e5 MD |
1119 | iommu_device_unregister(&mmu->iommu); |
1120 | ||
d25a2a16 LP |
1121 | arm_iommu_release_mapping(mmu->mapping); |
1122 | ||
1123 | ipmmu_device_reset(mmu); | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
da38e9ec GU |
1128 | #ifdef CONFIG_PM_SLEEP |
1129 | static int ipmmu_resume_noirq(struct device *dev) | |
1130 | { | |
1131 | struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); | |
1132 | unsigned int i; | |
1133 | ||
1134 | /* Reset root MMU and restore contexts */ | |
1135 | if (ipmmu_is_root(mmu)) { | |
1136 | ipmmu_device_reset(mmu); | |
1137 | ||
1138 | for (i = 0; i < mmu->num_ctx; i++) { | |
1139 | if (!mmu->domains[i]) | |
1140 | continue; | |
1141 | ||
1142 | ipmmu_domain_setup_context(mmu->domains[i]); | |
1143 | } | |
1144 | } | |
1145 | ||
1146 | /* Re-enable active micro-TLBs */ | |
1147 | for (i = 0; i < mmu->features->num_utlbs; i++) { | |
1148 | if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) | |
1149 | continue; | |
1150 | ||
1151 | ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); | |
1152 | } | |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static const struct dev_pm_ops ipmmu_pm = { | |
1158 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq) | |
1159 | }; | |
1160 | #define DEV_PM_OPS &ipmmu_pm | |
1161 | #else | |
1162 | #define DEV_PM_OPS NULL | |
1163 | #endif /* CONFIG_PM_SLEEP */ | |
1164 | ||
d25a2a16 LP |
1165 | static struct platform_driver ipmmu_driver = { |
1166 | .driver = { | |
d25a2a16 | 1167 | .name = "ipmmu-vmsa", |
275f5053 | 1168 | .of_match_table = of_match_ptr(ipmmu_of_ids), |
da38e9ec | 1169 | .pm = DEV_PM_OPS, |
d25a2a16 LP |
1170 | }, |
1171 | .probe = ipmmu_probe, | |
1172 | .remove = ipmmu_remove, | |
1173 | }; | |
1174 | ||
1175 | static int __init ipmmu_init(void) | |
1176 | { | |
5c5c8741 | 1177 | struct device_node *np; |
cda52fcd | 1178 | static bool setup_done; |
d25a2a16 LP |
1179 | int ret; |
1180 | ||
cda52fcd MD |
1181 | if (setup_done) |
1182 | return 0; | |
1183 | ||
5c5c8741 DO |
1184 | np = of_find_matching_node(NULL, ipmmu_of_ids); |
1185 | if (!np) | |
1186 | return 0; | |
1187 | ||
1188 | of_node_put(np); | |
1189 | ||
d25a2a16 LP |
1190 | ret = platform_driver_register(&ipmmu_driver); |
1191 | if (ret < 0) | |
1192 | return ret; | |
1193 | ||
cda52fcd | 1194 | #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA) |
d25a2a16 LP |
1195 | if (!iommu_present(&platform_bus_type)) |
1196 | bus_set_iommu(&platform_bus_type, &ipmmu_ops); | |
cda52fcd | 1197 | #endif |
d25a2a16 | 1198 | |
cda52fcd | 1199 | setup_done = true; |
d25a2a16 LP |
1200 | return 0; |
1201 | } | |
d25a2a16 | 1202 | subsys_initcall(ipmmu_init); |