Commit | Line | Data |
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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e1d3c0fd WD |
2 | /* |
3 | * CPU-agnostic ARM page table allocator. | |
4 | * | |
e1d3c0fd WD |
5 | * Copyright (C) 2014 ARM Limited |
6 | * | |
7 | * Author: Will Deacon <will.deacon@arm.com> | |
8 | */ | |
9 | ||
10 | #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt | |
11 | ||
2c3d273e | 12 | #include <linux/atomic.h> |
6c89928f | 13 | #include <linux/bitops.h> |
b77cf11f | 14 | #include <linux/io-pgtable.h> |
e1d3c0fd WD |
15 | #include <linux/kernel.h> |
16 | #include <linux/sizes.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/types.h> | |
8f6aff98 | 19 | #include <linux/dma-mapping.h> |
e1d3c0fd | 20 | |
87a91b15 RM |
21 | #include <asm/barrier.h> |
22 | ||
6c89928f | 23 | #define ARM_LPAE_MAX_ADDR_BITS 52 |
e1d3c0fd WD |
24 | #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16 |
25 | #define ARM_LPAE_MAX_LEVELS 4 | |
26 | ||
27 | /* Struct accessors */ | |
28 | #define io_pgtable_to_data(x) \ | |
29 | container_of((x), struct arm_lpae_io_pgtable, iop) | |
30 | ||
e1d3c0fd WD |
31 | #define io_pgtable_ops_to_data(x) \ |
32 | io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) | |
33 | ||
e1d3c0fd WD |
34 | /* |
35 | * Calculate the right shift amount to get to the portion describing level l | |
36 | * in a virtual address mapped by the pagetable in d. | |
37 | */ | |
38 | #define ARM_LPAE_LVL_SHIFT(l,d) \ | |
5fb190b0 RM |
39 | (((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \ |
40 | ilog2(sizeof(arm_lpae_iopte))) | |
e1d3c0fd | 41 | |
5fb190b0 RM |
42 | #define ARM_LPAE_GRANULE(d) \ |
43 | (sizeof(arm_lpae_iopte) << (d)->bits_per_level) | |
c79278c1 RM |
44 | #define ARM_LPAE_PGD_SIZE(d) \ |
45 | (sizeof(arm_lpae_iopte) << (d)->pgd_bits) | |
e1d3c0fd WD |
46 | |
47 | /* | |
48 | * Calculate the index at level l used to map virtual address a using the | |
49 | * pagetable in d. | |
50 | */ | |
51 | #define ARM_LPAE_PGD_IDX(l,d) \ | |
c79278c1 | 52 | ((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0) |
e1d3c0fd WD |
53 | |
54 | #define ARM_LPAE_LVL_IDX(a,l,d) \ | |
367bd978 | 55 | (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \ |
e1d3c0fd WD |
56 | ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1)) |
57 | ||
58 | /* Calculate the block/page mapping size at level l for pagetable in d. */ | |
5fb190b0 | 59 | #define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d)) |
e1d3c0fd WD |
60 | |
61 | /* Page table bits */ | |
62 | #define ARM_LPAE_PTE_TYPE_SHIFT 0 | |
63 | #define ARM_LPAE_PTE_TYPE_MASK 0x3 | |
64 | ||
65 | #define ARM_LPAE_PTE_TYPE_BLOCK 1 | |
66 | #define ARM_LPAE_PTE_TYPE_TABLE 3 | |
67 | #define ARM_LPAE_PTE_TYPE_PAGE 3 | |
68 | ||
6c89928f RM |
69 | #define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12) |
70 | ||
c896c132 | 71 | #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) |
e1d3c0fd WD |
72 | #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) |
73 | #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) | |
74 | #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) | |
75 | #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8) | |
76 | #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8) | |
c896c132 | 77 | #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5) |
e1d3c0fd WD |
78 | #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0) |
79 | ||
80 | #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2) | |
81 | /* Ignore the contiguous bit for block splitting */ | |
82 | #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52) | |
83 | #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \ | |
84 | ARM_LPAE_PTE_ATTR_HI_MASK) | |
2c3d273e RM |
85 | /* Software bit for solving coherency races */ |
86 | #define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55) | |
e1d3c0fd WD |
87 | |
88 | /* Stage-1 PTE */ | |
89 | #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6) | |
90 | #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6) | |
91 | #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2 | |
92 | #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11) | |
93 | ||
94 | /* Stage-2 PTE */ | |
95 | #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6) | |
96 | #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6) | |
97 | #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6) | |
98 | #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2) | |
99 | #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2) | |
100 | #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2) | |
101 | ||
102 | /* Register bits */ | |
fb485eb1 | 103 | #define ARM_64_LPAE_VTCR_RES1 (1U << 31) |
e1d3c0fd | 104 | |
fb485eb1 RM |
105 | #define ARM_LPAE_VTCR_TG0_SHIFT 14 |
106 | #define ARM_LPAE_TCR_TG0_4K 0 | |
107 | #define ARM_LPAE_TCR_TG0_64K 1 | |
108 | #define ARM_LPAE_TCR_TG0_16K 2 | |
e1d3c0fd WD |
109 | |
110 | #define ARM_LPAE_TCR_SH0_SHIFT 12 | |
e1d3c0fd WD |
111 | #define ARM_LPAE_TCR_SH_NS 0 |
112 | #define ARM_LPAE_TCR_SH_OS 2 | |
113 | #define ARM_LPAE_TCR_SH_IS 3 | |
114 | ||
115 | #define ARM_LPAE_TCR_ORGN0_SHIFT 10 | |
116 | #define ARM_LPAE_TCR_IRGN0_SHIFT 8 | |
e1d3c0fd WD |
117 | #define ARM_LPAE_TCR_RGN_NC 0 |
118 | #define ARM_LPAE_TCR_RGN_WBWA 1 | |
119 | #define ARM_LPAE_TCR_RGN_WT 2 | |
120 | #define ARM_LPAE_TCR_RGN_WB 3 | |
121 | ||
fb485eb1 RM |
122 | #define ARM_LPAE_VTCR_SL0_SHIFT 6 |
123 | #define ARM_LPAE_VTCR_SL0_MASK 0x3 | |
e1d3c0fd WD |
124 | |
125 | #define ARM_LPAE_TCR_T0SZ_SHIFT 0 | |
e1d3c0fd | 126 | |
fb485eb1 RM |
127 | #define ARM_LPAE_VTCR_PS_SHIFT 16 |
128 | #define ARM_LPAE_VTCR_PS_MASK 0x7 | |
e1d3c0fd WD |
129 | |
130 | #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL | |
131 | #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL | |
132 | #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL | |
133 | #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL | |
134 | #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL | |
135 | #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL | |
6c89928f | 136 | #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL |
e1d3c0fd WD |
137 | |
138 | #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3) | |
139 | #define ARM_LPAE_MAIR_ATTR_MASK 0xff | |
140 | #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04 | |
141 | #define ARM_LPAE_MAIR_ATTR_NC 0x44 | |
90ec7a76 | 142 | #define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4 |
e1d3c0fd WD |
143 | #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff |
144 | #define ARM_LPAE_MAIR_ATTR_IDX_NC 0 | |
145 | #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1 | |
146 | #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2 | |
90ec7a76 | 147 | #define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3 |
e1d3c0fd | 148 | |
d08d42de RH |
149 | #define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0) |
150 | #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2) | |
151 | #define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4) | |
152 | ||
52f325f4 RM |
153 | #define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL |
154 | #define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL | |
155 | ||
e1d3c0fd | 156 | /* IOPTE accessors */ |
6c89928f | 157 | #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d)) |
e1d3c0fd WD |
158 | |
159 | #define iopte_type(pte,l) \ | |
160 | (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK) | |
161 | ||
162 | #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK) | |
163 | ||
e1d3c0fd WD |
164 | struct arm_lpae_io_pgtable { |
165 | struct io_pgtable iop; | |
166 | ||
c79278c1 | 167 | int pgd_bits; |
594ab90f | 168 | int start_level; |
5fb190b0 | 169 | int bits_per_level; |
e1d3c0fd WD |
170 | |
171 | void *pgd; | |
172 | }; | |
173 | ||
174 | typedef u64 arm_lpae_iopte; | |
175 | ||
d08d42de RH |
176 | static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl, |
177 | enum io_pgtable_fmt fmt) | |
178 | { | |
179 | if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE) | |
180 | return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_PAGE; | |
181 | ||
182 | return iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_BLOCK; | |
183 | } | |
184 | ||
6c89928f RM |
185 | static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr, |
186 | struct arm_lpae_io_pgtable *data) | |
187 | { | |
188 | arm_lpae_iopte pte = paddr; | |
189 | ||
190 | /* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */ | |
191 | return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK; | |
192 | } | |
193 | ||
194 | static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte, | |
195 | struct arm_lpae_io_pgtable *data) | |
196 | { | |
78688059 | 197 | u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK; |
6c89928f | 198 | |
5fb190b0 | 199 | if (ARM_LPAE_GRANULE(data) < SZ_64K) |
6c89928f RM |
200 | return paddr; |
201 | ||
202 | /* Rotate the packed high-order bits back to the top */ | |
203 | return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4); | |
204 | } | |
205 | ||
fe4b991d WD |
206 | static bool selftest_running = false; |
207 | ||
ffcb6d16 | 208 | static dma_addr_t __arm_lpae_dma_addr(void *pages) |
f8d54961 | 209 | { |
ffcb6d16 | 210 | return (dma_addr_t)virt_to_phys(pages); |
f8d54961 RM |
211 | } |
212 | ||
213 | static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, | |
214 | struct io_pgtable_cfg *cfg) | |
215 | { | |
216 | struct device *dev = cfg->iommu_dev; | |
4b123757 RM |
217 | int order = get_order(size); |
218 | struct page *p; | |
f8d54961 | 219 | dma_addr_t dma; |
4b123757 | 220 | void *pages; |
f8d54961 | 221 | |
4b123757 | 222 | VM_BUG_ON((gfp & __GFP_HIGHMEM)); |
fac83d29 JPB |
223 | p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE, |
224 | gfp | __GFP_ZERO, order); | |
4b123757 | 225 | if (!p) |
f8d54961 RM |
226 | return NULL; |
227 | ||
4b123757 | 228 | pages = page_address(p); |
4f41845b | 229 | if (!cfg->coherent_walk) { |
f8d54961 RM |
230 | dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE); |
231 | if (dma_mapping_error(dev, dma)) | |
232 | goto out_free; | |
233 | /* | |
234 | * We depend on the IOMMU being able to work with any physical | |
ffcb6d16 RM |
235 | * address directly, so if the DMA layer suggests otherwise by |
236 | * translating or truncating them, that bodes very badly... | |
f8d54961 | 237 | */ |
ffcb6d16 | 238 | if (dma != virt_to_phys(pages)) |
f8d54961 RM |
239 | goto out_unmap; |
240 | } | |
241 | ||
242 | return pages; | |
243 | ||
244 | out_unmap: | |
245 | dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); | |
246 | dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); | |
247 | out_free: | |
4b123757 | 248 | __free_pages(p, order); |
f8d54961 RM |
249 | return NULL; |
250 | } | |
251 | ||
252 | static void __arm_lpae_free_pages(void *pages, size_t size, | |
253 | struct io_pgtable_cfg *cfg) | |
254 | { | |
4f41845b | 255 | if (!cfg->coherent_walk) |
ffcb6d16 | 256 | dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), |
f8d54961 | 257 | size, DMA_TO_DEVICE); |
4b123757 | 258 | free_pages((unsigned long)pages, get_order(size)); |
f8d54961 RM |
259 | } |
260 | ||
2c3d273e RM |
261 | static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, |
262 | struct io_pgtable_cfg *cfg) | |
263 | { | |
264 | dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep), | |
265 | sizeof(*ptep), DMA_TO_DEVICE); | |
266 | } | |
267 | ||
f8d54961 | 268 | static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte, |
87a91b15 | 269 | struct io_pgtable_cfg *cfg) |
f8d54961 | 270 | { |
f8d54961 RM |
271 | *ptep = pte; |
272 | ||
4f41845b | 273 | if (!cfg->coherent_walk) |
2c3d273e | 274 | __arm_lpae_sync_pte(ptep, cfg); |
f8d54961 RM |
275 | } |
276 | ||
193e67c0 | 277 | static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, |
3951c41a | 278 | struct iommu_iotlb_gather *gather, |
193e67c0 VG |
279 | unsigned long iova, size_t size, int lvl, |
280 | arm_lpae_iopte *ptep); | |
cf27ec93 | 281 | |
fb3a9579 RM |
282 | static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, |
283 | phys_addr_t paddr, arm_lpae_iopte prot, | |
284 | int lvl, arm_lpae_iopte *ptep) | |
285 | { | |
286 | arm_lpae_iopte pte = prot; | |
287 | ||
d08d42de | 288 | if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1) |
fb3a9579 RM |
289 | pte |= ARM_LPAE_PTE_TYPE_PAGE; |
290 | else | |
291 | pte |= ARM_LPAE_PTE_TYPE_BLOCK; | |
292 | ||
6c89928f | 293 | pte |= paddr_to_iopte(paddr, data); |
fb3a9579 RM |
294 | |
295 | __arm_lpae_set_pte(ptep, pte, &data->iop.cfg); | |
296 | } | |
297 | ||
e1d3c0fd WD |
298 | static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, |
299 | unsigned long iova, phys_addr_t paddr, | |
300 | arm_lpae_iopte prot, int lvl, | |
301 | arm_lpae_iopte *ptep) | |
302 | { | |
fb3a9579 | 303 | arm_lpae_iopte pte = *ptep; |
e1d3c0fd | 304 | |
d08d42de | 305 | if (iopte_leaf(pte, lvl, data->iop.fmt)) { |
cf27ec93 | 306 | /* We require an unmap first */ |
fe4b991d | 307 | WARN_ON(!selftest_running); |
e1d3c0fd | 308 | return -EEXIST; |
fb3a9579 | 309 | } else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) { |
cf27ec93 WD |
310 | /* |
311 | * We need to unmap and free the old table before | |
312 | * overwriting it with a block entry. | |
313 | */ | |
314 | arm_lpae_iopte *tblp; | |
315 | size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data); | |
316 | ||
317 | tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data); | |
3951c41a WD |
318 | if (__arm_lpae_unmap(data, NULL, iova, sz, lvl, tblp) != sz) { |
319 | WARN_ON(1); | |
cf27ec93 | 320 | return -EINVAL; |
3951c41a | 321 | } |
fe4b991d | 322 | } |
e1d3c0fd | 323 | |
fb3a9579 RM |
324 | __arm_lpae_init_pte(data, paddr, prot, lvl, ptep); |
325 | return 0; | |
326 | } | |
c896c132 | 327 | |
fb3a9579 RM |
328 | static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table, |
329 | arm_lpae_iopte *ptep, | |
2c3d273e | 330 | arm_lpae_iopte curr, |
fb3a9579 RM |
331 | struct io_pgtable_cfg *cfg) |
332 | { | |
2c3d273e | 333 | arm_lpae_iopte old, new; |
e1d3c0fd | 334 | |
fb3a9579 RM |
335 | new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE; |
336 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) | |
337 | new |= ARM_LPAE_PTE_NSTABLE; | |
e1d3c0fd | 338 | |
77f34458 WD |
339 | /* |
340 | * Ensure the table itself is visible before its PTE can be. | |
341 | * Whilst we could get away with cmpxchg64_release below, this | |
342 | * doesn't have any ordering semantics when !CONFIG_SMP. | |
343 | */ | |
344 | dma_wmb(); | |
2c3d273e RM |
345 | |
346 | old = cmpxchg64_relaxed(ptep, curr, new); | |
347 | ||
4f41845b | 348 | if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC)) |
2c3d273e RM |
349 | return old; |
350 | ||
351 | /* Even if it's not ours, there's no point waiting; just kick it */ | |
352 | __arm_lpae_sync_pte(ptep, cfg); | |
353 | if (old == curr) | |
354 | WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC); | |
355 | ||
356 | return old; | |
e1d3c0fd WD |
357 | } |
358 | ||
359 | static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, | |
360 | phys_addr_t paddr, size_t size, arm_lpae_iopte prot, | |
361 | int lvl, arm_lpae_iopte *ptep) | |
362 | { | |
363 | arm_lpae_iopte *cptep, pte; | |
e1d3c0fd | 364 | size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data); |
2c3d273e | 365 | size_t tblsz = ARM_LPAE_GRANULE(data); |
f8d54961 | 366 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
e1d3c0fd WD |
367 | |
368 | /* Find our entry at the current level */ | |
369 | ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); | |
370 | ||
371 | /* If we can install a leaf entry at this level, then do so */ | |
f7b90d2c | 372 | if (size == block_size) |
e1d3c0fd WD |
373 | return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep); |
374 | ||
375 | /* We can't allocate tables at the final level */ | |
376 | if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)) | |
377 | return -EINVAL; | |
378 | ||
379 | /* Grab a pointer to the next level */ | |
2c3d273e | 380 | pte = READ_ONCE(*ptep); |
e1d3c0fd | 381 | if (!pte) { |
2c3d273e | 382 | cptep = __arm_lpae_alloc_pages(tblsz, GFP_ATOMIC, cfg); |
e1d3c0fd WD |
383 | if (!cptep) |
384 | return -ENOMEM; | |
385 | ||
2c3d273e RM |
386 | pte = arm_lpae_install_table(cptep, ptep, 0, cfg); |
387 | if (pte) | |
388 | __arm_lpae_free_pages(cptep, tblsz, cfg); | |
4f41845b | 389 | } else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) { |
2c3d273e RM |
390 | __arm_lpae_sync_pte(ptep, cfg); |
391 | } | |
392 | ||
d08d42de | 393 | if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) { |
e1d3c0fd | 394 | cptep = iopte_deref(pte, data); |
2c3d273e | 395 | } else if (pte) { |
ed46e66c OT |
396 | /* We require an unmap first */ |
397 | WARN_ON(!selftest_running); | |
398 | return -EEXIST; | |
e1d3c0fd WD |
399 | } |
400 | ||
401 | /* Rinse, repeat */ | |
402 | return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep); | |
403 | } | |
404 | ||
405 | static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, | |
406 | int prot) | |
407 | { | |
408 | arm_lpae_iopte pte; | |
409 | ||
410 | if (data->iop.fmt == ARM_64_LPAE_S1 || | |
411 | data->iop.fmt == ARM_32_LPAE_S1) { | |
e7468a23 | 412 | pte = ARM_LPAE_PTE_nG; |
e1d3c0fd WD |
413 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
414 | pte |= ARM_LPAE_PTE_AP_RDONLY; | |
e7468a23 JG |
415 | if (!(prot & IOMMU_PRIV)) |
416 | pte |= ARM_LPAE_PTE_AP_UNPRIV; | |
e1d3c0fd WD |
417 | } else { |
418 | pte = ARM_LPAE_PTE_HAP_FAULT; | |
419 | if (prot & IOMMU_READ) | |
420 | pte |= ARM_LPAE_PTE_HAP_READ; | |
421 | if (prot & IOMMU_WRITE) | |
422 | pte |= ARM_LPAE_PTE_HAP_WRITE; | |
d08d42de RH |
423 | } |
424 | ||
425 | /* | |
426 | * Note that this logic is structured to accommodate Mali LPAE | |
427 | * having stage-1-like attributes but stage-2-like permissions. | |
428 | */ | |
429 | if (data->iop.fmt == ARM_64_LPAE_S2 || | |
430 | data->iop.fmt == ARM_32_LPAE_S2) { | |
fb948251 RM |
431 | if (prot & IOMMU_MMIO) |
432 | pte |= ARM_LPAE_PTE_MEMATTR_DEV; | |
433 | else if (prot & IOMMU_CACHE) | |
e1d3c0fd WD |
434 | pte |= ARM_LPAE_PTE_MEMATTR_OIWB; |
435 | else | |
436 | pte |= ARM_LPAE_PTE_MEMATTR_NC; | |
d08d42de RH |
437 | } else { |
438 | if (prot & IOMMU_MMIO) | |
439 | pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV | |
440 | << ARM_LPAE_PTE_ATTRINDX_SHIFT); | |
441 | else if (prot & IOMMU_CACHE) | |
442 | pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE | |
443 | << ARM_LPAE_PTE_ATTRINDX_SHIFT); | |
dd5ddd3c | 444 | else if (prot & IOMMU_SYS_CACHE_ONLY) |
90ec7a76 VG |
445 | pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE |
446 | << ARM_LPAE_PTE_ATTRINDX_SHIFT); | |
e1d3c0fd WD |
447 | } |
448 | ||
7618e479 RM |
449 | if (prot & IOMMU_CACHE) |
450 | pte |= ARM_LPAE_PTE_SH_IS; | |
451 | else | |
452 | pte |= ARM_LPAE_PTE_SH_OS; | |
453 | ||
e1d3c0fd WD |
454 | if (prot & IOMMU_NOEXEC) |
455 | pte |= ARM_LPAE_PTE_XN; | |
456 | ||
7618e479 RM |
457 | if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS) |
458 | pte |= ARM_LPAE_PTE_NS; | |
459 | ||
460 | if (data->iop.fmt != ARM_MALI_LPAE) | |
461 | pte |= ARM_LPAE_PTE_AF; | |
462 | ||
e1d3c0fd WD |
463 | return pte; |
464 | } | |
465 | ||
466 | static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, | |
467 | phys_addr_t paddr, size_t size, int iommu_prot) | |
468 | { | |
469 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
f7b90d2c | 470 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
e1d3c0fd | 471 | arm_lpae_iopte *ptep = data->pgd; |
594ab90f | 472 | int ret, lvl = data->start_level; |
e1d3c0fd WD |
473 | arm_lpae_iopte prot; |
474 | ||
475 | /* If no access, then nothing to do */ | |
476 | if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) | |
477 | return 0; | |
478 | ||
f7b90d2c RM |
479 | if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) |
480 | return -EINVAL; | |
481 | ||
67f3e53d | 482 | if (WARN_ON(iova >> data->iop.cfg.ias || paddr >> data->iop.cfg.oas)) |
76557391 RM |
483 | return -ERANGE; |
484 | ||
e1d3c0fd | 485 | prot = arm_lpae_prot_to_pte(data, iommu_prot); |
87a91b15 RM |
486 | ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep); |
487 | /* | |
488 | * Synchronise all PTE updates for the new mapping before there's | |
489 | * a chance for anything to kick off a table walk for the new iova. | |
490 | */ | |
491 | wmb(); | |
492 | ||
493 | return ret; | |
e1d3c0fd WD |
494 | } |
495 | ||
496 | static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl, | |
497 | arm_lpae_iopte *ptep) | |
498 | { | |
499 | arm_lpae_iopte *start, *end; | |
500 | unsigned long table_size; | |
501 | ||
594ab90f | 502 | if (lvl == data->start_level) |
c79278c1 | 503 | table_size = ARM_LPAE_PGD_SIZE(data); |
e1d3c0fd | 504 | else |
06c610e8 | 505 | table_size = ARM_LPAE_GRANULE(data); |
e1d3c0fd WD |
506 | |
507 | start = ptep; | |
12c2ab09 WD |
508 | |
509 | /* Only leaf entries at the last level */ | |
510 | if (lvl == ARM_LPAE_MAX_LEVELS - 1) | |
511 | end = ptep; | |
512 | else | |
513 | end = (void *)ptep + table_size; | |
e1d3c0fd WD |
514 | |
515 | while (ptep != end) { | |
516 | arm_lpae_iopte pte = *ptep++; | |
517 | ||
d08d42de | 518 | if (!pte || iopte_leaf(pte, lvl, data->iop.fmt)) |
e1d3c0fd WD |
519 | continue; |
520 | ||
521 | __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data)); | |
522 | } | |
523 | ||
f8d54961 | 524 | __arm_lpae_free_pages(start, table_size, &data->iop.cfg); |
e1d3c0fd WD |
525 | } |
526 | ||
527 | static void arm_lpae_free_pgtable(struct io_pgtable *iop) | |
528 | { | |
529 | struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop); | |
530 | ||
594ab90f | 531 | __arm_lpae_free_pgtable(data, data->start_level, data->pgd); |
e1d3c0fd WD |
532 | kfree(data); |
533 | } | |
534 | ||
193e67c0 | 535 | static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, |
3951c41a | 536 | struct iommu_iotlb_gather *gather, |
193e67c0 VG |
537 | unsigned long iova, size_t size, |
538 | arm_lpae_iopte blk_pte, int lvl, | |
539 | arm_lpae_iopte *ptep) | |
e1d3c0fd | 540 | { |
fb3a9579 RM |
541 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
542 | arm_lpae_iopte pte, *tablep; | |
e1d3c0fd | 543 | phys_addr_t blk_paddr; |
fb3a9579 RM |
544 | size_t tablesz = ARM_LPAE_GRANULE(data); |
545 | size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data); | |
546 | int i, unmap_idx = -1; | |
547 | ||
548 | if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) | |
549 | return 0; | |
e1d3c0fd | 550 | |
fb3a9579 RM |
551 | tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg); |
552 | if (!tablep) | |
553 | return 0; /* Bytes unmapped */ | |
e1d3c0fd | 554 | |
fb3a9579 RM |
555 | if (size == split_sz) |
556 | unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data); | |
e1d3c0fd | 557 | |
6c89928f | 558 | blk_paddr = iopte_to_paddr(blk_pte, data); |
fb3a9579 RM |
559 | pte = iopte_prot(blk_pte); |
560 | ||
561 | for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) { | |
e1d3c0fd | 562 | /* Unmap! */ |
fb3a9579 | 563 | if (i == unmap_idx) |
e1d3c0fd WD |
564 | continue; |
565 | ||
fb3a9579 | 566 | __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]); |
e1d3c0fd WD |
567 | } |
568 | ||
2c3d273e RM |
569 | pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg); |
570 | if (pte != blk_pte) { | |
571 | __arm_lpae_free_pages(tablep, tablesz, cfg); | |
572 | /* | |
573 | * We may race against someone unmapping another part of this | |
574 | * block, but anything else is invalid. We can't misinterpret | |
575 | * a page entry here since we're never at the last level. | |
576 | */ | |
577 | if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE) | |
578 | return 0; | |
579 | ||
580 | tablep = iopte_deref(pte, data); | |
85c7a0f1 | 581 | } else if (unmap_idx >= 0) { |
3951c41a | 582 | io_pgtable_tlb_add_page(&data->iop, gather, iova, size); |
85c7a0f1 | 583 | return size; |
2c3d273e | 584 | } |
fb3a9579 | 585 | |
3951c41a | 586 | return __arm_lpae_unmap(data, gather, iova, size, lvl, tablep); |
e1d3c0fd WD |
587 | } |
588 | ||
193e67c0 | 589 | static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, |
3951c41a | 590 | struct iommu_iotlb_gather *gather, |
193e67c0 VG |
591 | unsigned long iova, size_t size, int lvl, |
592 | arm_lpae_iopte *ptep) | |
e1d3c0fd WD |
593 | { |
594 | arm_lpae_iopte pte; | |
507e4c9d | 595 | struct io_pgtable *iop = &data->iop; |
e1d3c0fd | 596 | |
2eb97c78 RM |
597 | /* Something went horribly wrong and we ran out of page table */ |
598 | if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) | |
599 | return 0; | |
600 | ||
e1d3c0fd | 601 | ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
2c3d273e | 602 | pte = READ_ONCE(*ptep); |
2eb97c78 | 603 | if (WARN_ON(!pte)) |
e1d3c0fd WD |
604 | return 0; |
605 | ||
606 | /* If the size matches this level, we're in the right place */ | |
fb3a9579 | 607 | if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { |
507e4c9d | 608 | __arm_lpae_set_pte(ptep, 0, &iop->cfg); |
e1d3c0fd | 609 | |
d08d42de | 610 | if (!iopte_leaf(pte, lvl, iop->fmt)) { |
e1d3c0fd | 611 | /* Also flush any partial walks */ |
10b7a7d9 WD |
612 | io_pgtable_tlb_flush_walk(iop, iova, size, |
613 | ARM_LPAE_GRANULE(data)); | |
e1d3c0fd WD |
614 | ptep = iopte_deref(pte, data); |
615 | __arm_lpae_free_pgtable(data, lvl + 1, ptep); | |
b6b65ca2 ZL |
616 | } else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) { |
617 | /* | |
618 | * Order the PTE update against queueing the IOVA, to | |
619 | * guarantee that a flush callback from a different CPU | |
620 | * has observed it before the TLBIALL can be issued. | |
621 | */ | |
622 | smp_wmb(); | |
e1d3c0fd | 623 | } else { |
3951c41a | 624 | io_pgtable_tlb_add_page(iop, gather, iova, size); |
e1d3c0fd WD |
625 | } |
626 | ||
627 | return size; | |
d08d42de | 628 | } else if (iopte_leaf(pte, lvl, iop->fmt)) { |
e1d3c0fd WD |
629 | /* |
630 | * Insert a table at the next level to map the old region, | |
631 | * minus the part we want to unmap | |
632 | */ | |
3951c41a | 633 | return arm_lpae_split_blk_unmap(data, gather, iova, size, pte, |
fb3a9579 | 634 | lvl + 1, ptep); |
e1d3c0fd WD |
635 | } |
636 | ||
637 | /* Keep on walkin' */ | |
638 | ptep = iopte_deref(pte, data); | |
3951c41a | 639 | return __arm_lpae_unmap(data, gather, iova, size, lvl + 1, ptep); |
e1d3c0fd WD |
640 | } |
641 | ||
193e67c0 | 642 | static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, |
a2d3a382 | 643 | size_t size, struct iommu_iotlb_gather *gather) |
e1d3c0fd | 644 | { |
e1d3c0fd | 645 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); |
f7b90d2c | 646 | struct io_pgtable_cfg *cfg = &data->iop.cfg; |
e1d3c0fd | 647 | arm_lpae_iopte *ptep = data->pgd; |
e1d3c0fd | 648 | |
f7b90d2c RM |
649 | if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) |
650 | return 0; | |
651 | ||
67f3e53d | 652 | if (WARN_ON(iova >> data->iop.cfg.ias)) |
76557391 RM |
653 | return 0; |
654 | ||
594ab90f | 655 | return __arm_lpae_unmap(data, gather, iova, size, data->start_level, ptep); |
e1d3c0fd WD |
656 | } |
657 | ||
658 | static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, | |
659 | unsigned long iova) | |
660 | { | |
661 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
662 | arm_lpae_iopte pte, *ptep = data->pgd; | |
594ab90f | 663 | int lvl = data->start_level; |
e1d3c0fd WD |
664 | |
665 | do { | |
666 | /* Valid IOPTE pointer? */ | |
667 | if (!ptep) | |
668 | return 0; | |
669 | ||
670 | /* Grab the IOPTE we're interested in */ | |
2c3d273e RM |
671 | ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
672 | pte = READ_ONCE(*ptep); | |
e1d3c0fd WD |
673 | |
674 | /* Valid entry? */ | |
675 | if (!pte) | |
676 | return 0; | |
677 | ||
678 | /* Leaf entry? */ | |
d08d42de | 679 | if (iopte_leaf(pte, lvl, data->iop.fmt)) |
e1d3c0fd WD |
680 | goto found_translation; |
681 | ||
682 | /* Take it to the next level */ | |
683 | ptep = iopte_deref(pte, data); | |
684 | } while (++lvl < ARM_LPAE_MAX_LEVELS); | |
685 | ||
686 | /* Ran out of page tables to walk */ | |
687 | return 0; | |
688 | ||
689 | found_translation: | |
7c6d90e2 | 690 | iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1); |
6c89928f | 691 | return iopte_to_paddr(pte, data) | iova; |
e1d3c0fd WD |
692 | } |
693 | ||
694 | static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) | |
695 | { | |
6c89928f RM |
696 | unsigned long granule, page_sizes; |
697 | unsigned int max_addr_bits = 48; | |
e1d3c0fd WD |
698 | |
699 | /* | |
700 | * We need to restrict the supported page sizes to match the | |
701 | * translation regime for a particular granule. Aim to match | |
702 | * the CPU page size if possible, otherwise prefer smaller sizes. | |
703 | * While we're at it, restrict the block sizes to match the | |
704 | * chosen granule. | |
705 | */ | |
706 | if (cfg->pgsize_bitmap & PAGE_SIZE) | |
707 | granule = PAGE_SIZE; | |
708 | else if (cfg->pgsize_bitmap & ~PAGE_MASK) | |
709 | granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK); | |
710 | else if (cfg->pgsize_bitmap & PAGE_MASK) | |
711 | granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK); | |
712 | else | |
713 | granule = 0; | |
714 | ||
715 | switch (granule) { | |
716 | case SZ_4K: | |
6c89928f | 717 | page_sizes = (SZ_4K | SZ_2M | SZ_1G); |
e1d3c0fd WD |
718 | break; |
719 | case SZ_16K: | |
6c89928f | 720 | page_sizes = (SZ_16K | SZ_32M); |
e1d3c0fd WD |
721 | break; |
722 | case SZ_64K: | |
6c89928f RM |
723 | max_addr_bits = 52; |
724 | page_sizes = (SZ_64K | SZ_512M); | |
725 | if (cfg->oas > 48) | |
726 | page_sizes |= 1ULL << 42; /* 4TB */ | |
e1d3c0fd WD |
727 | break; |
728 | default: | |
6c89928f | 729 | page_sizes = 0; |
e1d3c0fd | 730 | } |
6c89928f RM |
731 | |
732 | cfg->pgsize_bitmap &= page_sizes; | |
733 | cfg->ias = min(cfg->ias, max_addr_bits); | |
734 | cfg->oas = min(cfg->oas, max_addr_bits); | |
e1d3c0fd WD |
735 | } |
736 | ||
737 | static struct arm_lpae_io_pgtable * | |
738 | arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) | |
739 | { | |
e1d3c0fd | 740 | struct arm_lpae_io_pgtable *data; |
5fb190b0 | 741 | int levels, va_bits, pg_shift; |
e1d3c0fd WD |
742 | |
743 | arm_lpae_restrict_pgsizes(cfg); | |
744 | ||
745 | if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K))) | |
746 | return NULL; | |
747 | ||
748 | if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS) | |
749 | return NULL; | |
750 | ||
751 | if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS) | |
752 | return NULL; | |
753 | ||
ffcb6d16 RM |
754 | if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) { |
755 | dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n"); | |
756 | return NULL; | |
757 | } | |
758 | ||
e1d3c0fd WD |
759 | data = kmalloc(sizeof(*data), GFP_KERNEL); |
760 | if (!data) | |
761 | return NULL; | |
762 | ||
5fb190b0 RM |
763 | pg_shift = __ffs(cfg->pgsize_bitmap); |
764 | data->bits_per_level = pg_shift - ilog2(sizeof(arm_lpae_iopte)); | |
e1d3c0fd | 765 | |
5fb190b0 | 766 | va_bits = cfg->ias - pg_shift; |
594ab90f RM |
767 | levels = DIV_ROUND_UP(va_bits, data->bits_per_level); |
768 | data->start_level = ARM_LPAE_MAX_LEVELS - levels; | |
e1d3c0fd WD |
769 | |
770 | /* Calculate the actual size of our pgd (without concatenation) */ | |
c79278c1 | 771 | data->pgd_bits = va_bits - (data->bits_per_level * (levels - 1)); |
e1d3c0fd WD |
772 | |
773 | data->iop.ops = (struct io_pgtable_ops) { | |
774 | .map = arm_lpae_map, | |
775 | .unmap = arm_lpae_unmap, | |
776 | .iova_to_phys = arm_lpae_iova_to_phys, | |
777 | }; | |
778 | ||
779 | return data; | |
780 | } | |
781 | ||
782 | static struct io_pgtable * | |
783 | arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) | |
784 | { | |
785 | u64 reg; | |
3850db49 | 786 | struct arm_lpae_io_pgtable *data; |
fb485eb1 | 787 | typeof(&cfg->arm_lpae_s1_cfg.tcr) tcr = &cfg->arm_lpae_s1_cfg.tcr; |
3850db49 | 788 | |
4f41845b | 789 | if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | |
b6b65ca2 | 790 | IO_PGTABLE_QUIRK_NON_STRICT)) |
3850db49 | 791 | return NULL; |
e1d3c0fd | 792 | |
3850db49 | 793 | data = arm_lpae_alloc_pgtable(cfg); |
e1d3c0fd WD |
794 | if (!data) |
795 | return NULL; | |
796 | ||
797 | /* TCR */ | |
9e6ea59f | 798 | if (cfg->coherent_walk) { |
fb485eb1 RM |
799 | tcr->sh = ARM_LPAE_TCR_SH_IS; |
800 | tcr->irgn = ARM_LPAE_TCR_RGN_WBWA; | |
801 | tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; | |
9e6ea59f | 802 | } else { |
fb485eb1 RM |
803 | tcr->sh = ARM_LPAE_TCR_SH_OS; |
804 | tcr->irgn = ARM_LPAE_TCR_RGN_NC; | |
805 | tcr->orgn = ARM_LPAE_TCR_RGN_NC; | |
9e6ea59f | 806 | } |
e1d3c0fd | 807 | |
06c610e8 | 808 | switch (ARM_LPAE_GRANULE(data)) { |
e1d3c0fd | 809 | case SZ_4K: |
fb485eb1 | 810 | tcr->tg = ARM_LPAE_TCR_TG0_4K; |
e1d3c0fd WD |
811 | break; |
812 | case SZ_16K: | |
fb485eb1 | 813 | tcr->tg = ARM_LPAE_TCR_TG0_16K; |
e1d3c0fd WD |
814 | break; |
815 | case SZ_64K: | |
fb485eb1 | 816 | tcr->tg = ARM_LPAE_TCR_TG0_64K; |
e1d3c0fd WD |
817 | break; |
818 | } | |
819 | ||
820 | switch (cfg->oas) { | |
821 | case 32: | |
fb485eb1 | 822 | tcr->ips = ARM_LPAE_TCR_PS_32_BIT; |
e1d3c0fd WD |
823 | break; |
824 | case 36: | |
fb485eb1 | 825 | tcr->ips = ARM_LPAE_TCR_PS_36_BIT; |
e1d3c0fd WD |
826 | break; |
827 | case 40: | |
fb485eb1 | 828 | tcr->ips = ARM_LPAE_TCR_PS_40_BIT; |
e1d3c0fd WD |
829 | break; |
830 | case 42: | |
fb485eb1 | 831 | tcr->ips = ARM_LPAE_TCR_PS_42_BIT; |
e1d3c0fd WD |
832 | break; |
833 | case 44: | |
fb485eb1 | 834 | tcr->ips = ARM_LPAE_TCR_PS_44_BIT; |
e1d3c0fd WD |
835 | break; |
836 | case 48: | |
fb485eb1 | 837 | tcr->ips = ARM_LPAE_TCR_PS_48_BIT; |
e1d3c0fd | 838 | break; |
6c89928f | 839 | case 52: |
fb485eb1 | 840 | tcr->ips = ARM_LPAE_TCR_PS_52_BIT; |
6c89928f | 841 | break; |
e1d3c0fd WD |
842 | default: |
843 | goto out_free_data; | |
844 | } | |
845 | ||
fb485eb1 | 846 | tcr->tsz = 64ULL - cfg->ias; |
e1d3c0fd WD |
847 | |
848 | /* MAIRs */ | |
849 | reg = (ARM_LPAE_MAIR_ATTR_NC | |
850 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) | | |
851 | (ARM_LPAE_MAIR_ATTR_WBRWA | |
852 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) | | |
853 | (ARM_LPAE_MAIR_ATTR_DEVICE | |
90ec7a76 VG |
854 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) | |
855 | (ARM_LPAE_MAIR_ATTR_INC_OWBRWA | |
856 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)); | |
e1d3c0fd | 857 | |
205577ab | 858 | cfg->arm_lpae_s1_cfg.mair = reg; |
e1d3c0fd WD |
859 | |
860 | /* Looking good; allocate a pgd */ | |
c79278c1 RM |
861 | data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), |
862 | GFP_KERNEL, cfg); | |
e1d3c0fd WD |
863 | if (!data->pgd) |
864 | goto out_free_data; | |
865 | ||
87a91b15 RM |
866 | /* Ensure the empty pgd is visible before any actual TTBR write */ |
867 | wmb(); | |
e1d3c0fd | 868 | |
d1e5f26f RM |
869 | /* TTBR */ |
870 | cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); | |
e1d3c0fd WD |
871 | return &data->iop; |
872 | ||
873 | out_free_data: | |
874 | kfree(data); | |
875 | return NULL; | |
876 | } | |
877 | ||
878 | static struct io_pgtable * | |
879 | arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) | |
880 | { | |
881 | u64 reg, sl; | |
3850db49 RM |
882 | struct arm_lpae_io_pgtable *data; |
883 | ||
884 | /* The NS quirk doesn't apply at stage 2 */ | |
4f41845b | 885 | if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT)) |
3850db49 | 886 | return NULL; |
e1d3c0fd | 887 | |
3850db49 | 888 | data = arm_lpae_alloc_pgtable(cfg); |
e1d3c0fd WD |
889 | if (!data) |
890 | return NULL; | |
891 | ||
892 | /* | |
893 | * Concatenate PGDs at level 1 if possible in order to reduce | |
894 | * the depth of the stage-2 walk. | |
895 | */ | |
594ab90f | 896 | if (data->start_level == 0) { |
e1d3c0fd WD |
897 | unsigned long pgd_pages; |
898 | ||
c79278c1 | 899 | pgd_pages = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte); |
e1d3c0fd | 900 | if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) { |
c79278c1 | 901 | data->pgd_bits += data->bits_per_level; |
594ab90f | 902 | data->start_level++; |
e1d3c0fd WD |
903 | } |
904 | } | |
905 | ||
906 | /* VTCR */ | |
fb485eb1 | 907 | reg = ARM_64_LPAE_VTCR_RES1; |
30d2acb6 WD |
908 | if (cfg->coherent_walk) { |
909 | reg |= (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | | |
910 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | | |
911 | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); | |
912 | } else { | |
913 | reg |= (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | | |
914 | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | | |
915 | (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT); | |
916 | } | |
e1d3c0fd | 917 | |
594ab90f | 918 | sl = data->start_level; |
e1d3c0fd | 919 | |
06c610e8 | 920 | switch (ARM_LPAE_GRANULE(data)) { |
e1d3c0fd | 921 | case SZ_4K: |
fb485eb1 | 922 | reg |= (ARM_LPAE_TCR_TG0_4K << ARM_LPAE_VTCR_TG0_SHIFT); |
e1d3c0fd WD |
923 | sl++; /* SL0 format is different for 4K granule size */ |
924 | break; | |
925 | case SZ_16K: | |
fb485eb1 | 926 | reg |= (ARM_LPAE_TCR_TG0_16K << ARM_LPAE_VTCR_TG0_SHIFT); |
e1d3c0fd WD |
927 | break; |
928 | case SZ_64K: | |
fb485eb1 | 929 | reg |= (ARM_LPAE_TCR_TG0_64K << ARM_LPAE_VTCR_TG0_SHIFT); |
e1d3c0fd WD |
930 | break; |
931 | } | |
932 | ||
933 | switch (cfg->oas) { | |
934 | case 32: | |
fb485eb1 | 935 | reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd WD |
936 | break; |
937 | case 36: | |
fb485eb1 | 938 | reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd WD |
939 | break; |
940 | case 40: | |
fb485eb1 | 941 | reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd WD |
942 | break; |
943 | case 42: | |
fb485eb1 | 944 | reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd WD |
945 | break; |
946 | case 44: | |
fb485eb1 | 947 | reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd WD |
948 | break; |
949 | case 48: | |
fb485eb1 | 950 | reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
e1d3c0fd | 951 | break; |
6c89928f | 952 | case 52: |
fb485eb1 | 953 | reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_VTCR_PS_SHIFT); |
6c89928f | 954 | break; |
e1d3c0fd WD |
955 | default: |
956 | goto out_free_data; | |
957 | } | |
958 | ||
959 | reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; | |
fb485eb1 | 960 | reg |= (~sl & ARM_LPAE_VTCR_SL0_MASK) << ARM_LPAE_VTCR_SL0_SHIFT; |
e1d3c0fd WD |
961 | cfg->arm_lpae_s2_cfg.vtcr = reg; |
962 | ||
963 | /* Allocate pgd pages */ | |
c79278c1 RM |
964 | data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), |
965 | GFP_KERNEL, cfg); | |
e1d3c0fd WD |
966 | if (!data->pgd) |
967 | goto out_free_data; | |
968 | ||
87a91b15 RM |
969 | /* Ensure the empty pgd is visible before any actual TTBR write */ |
970 | wmb(); | |
e1d3c0fd WD |
971 | |
972 | /* VTTBR */ | |
973 | cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd); | |
974 | return &data->iop; | |
975 | ||
976 | out_free_data: | |
977 | kfree(data); | |
978 | return NULL; | |
979 | } | |
980 | ||
981 | static struct io_pgtable * | |
982 | arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) | |
983 | { | |
e1d3c0fd WD |
984 | if (cfg->ias > 32 || cfg->oas > 40) |
985 | return NULL; | |
986 | ||
987 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
e1d3c0fd | 988 | |
fb485eb1 | 989 | return arm_64_lpae_alloc_pgtable_s1(cfg, cookie); |
e1d3c0fd WD |
990 | } |
991 | ||
992 | static struct io_pgtable * | |
993 | arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) | |
994 | { | |
995 | struct io_pgtable *iop; | |
996 | ||
997 | if (cfg->ias > 40 || cfg->oas > 40) | |
998 | return NULL; | |
999 | ||
1000 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
1001 | iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie); | |
1002 | if (iop) | |
1003 | cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff; | |
1004 | ||
1005 | return iop; | |
1006 | } | |
1007 | ||
d08d42de RH |
1008 | static struct io_pgtable * |
1009 | arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) | |
1010 | { | |
52f325f4 | 1011 | struct arm_lpae_io_pgtable *data; |
d08d42de | 1012 | |
52f325f4 RM |
1013 | /* No quirks for Mali (hopefully) */ |
1014 | if (cfg->quirks) | |
1015 | return NULL; | |
d08d42de | 1016 | |
1be08f45 | 1017 | if (cfg->ias > 48 || cfg->oas > 40) |
d08d42de RH |
1018 | return NULL; |
1019 | ||
1020 | cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); | |
d08d42de | 1021 | |
52f325f4 RM |
1022 | data = arm_lpae_alloc_pgtable(cfg); |
1023 | if (!data) | |
1024 | return NULL; | |
d08d42de | 1025 | |
1be08f45 | 1026 | /* Mali seems to need a full 4-level table regardless of IAS */ |
594ab90f RM |
1027 | if (data->start_level > 0) { |
1028 | data->start_level = 0; | |
c79278c1 | 1029 | data->pgd_bits = 0; |
d08d42de | 1030 | } |
52f325f4 RM |
1031 | /* |
1032 | * MEMATTR: Mali has no actual notion of a non-cacheable type, so the | |
1033 | * best we can do is mimic the out-of-tree driver and hope that the | |
1034 | * "implementation-defined caching policy" is good enough. Similarly, | |
1035 | * we'll use it for the sake of a valid attribute for our 'device' | |
1036 | * index, although callers should never request that in practice. | |
1037 | */ | |
1038 | cfg->arm_mali_lpae_cfg.memattr = | |
1039 | (ARM_MALI_LPAE_MEMATTR_IMP_DEF | |
1040 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) | | |
1041 | (ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC | |
1042 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) | | |
1043 | (ARM_MALI_LPAE_MEMATTR_IMP_DEF | |
1044 | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)); | |
d08d42de | 1045 | |
c79278c1 RM |
1046 | data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), GFP_KERNEL, |
1047 | cfg); | |
52f325f4 RM |
1048 | if (!data->pgd) |
1049 | goto out_free_data; | |
1050 | ||
1051 | /* Ensure the empty pgd is visible before TRANSTAB can be written */ | |
1052 | wmb(); | |
1053 | ||
1054 | cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) | | |
1055 | ARM_MALI_LPAE_TTBR_READ_INNER | | |
1056 | ARM_MALI_LPAE_TTBR_ADRMODE_TABLE; | |
1057 | return &data->iop; | |
1058 | ||
1059 | out_free_data: | |
1060 | kfree(data); | |
1061 | return NULL; | |
d08d42de RH |
1062 | } |
1063 | ||
e1d3c0fd WD |
1064 | struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = { |
1065 | .alloc = arm_64_lpae_alloc_pgtable_s1, | |
1066 | .free = arm_lpae_free_pgtable, | |
1067 | }; | |
1068 | ||
1069 | struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = { | |
1070 | .alloc = arm_64_lpae_alloc_pgtable_s2, | |
1071 | .free = arm_lpae_free_pgtable, | |
1072 | }; | |
1073 | ||
1074 | struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = { | |
1075 | .alloc = arm_32_lpae_alloc_pgtable_s1, | |
1076 | .free = arm_lpae_free_pgtable, | |
1077 | }; | |
1078 | ||
1079 | struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = { | |
1080 | .alloc = arm_32_lpae_alloc_pgtable_s2, | |
1081 | .free = arm_lpae_free_pgtable, | |
1082 | }; | |
fe4b991d | 1083 | |
d08d42de RH |
1084 | struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = { |
1085 | .alloc = arm_mali_lpae_alloc_pgtable, | |
1086 | .free = arm_lpae_free_pgtable, | |
1087 | }; | |
1088 | ||
fe4b991d WD |
1089 | #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST |
1090 | ||
b5813c16 | 1091 | static struct io_pgtable_cfg *cfg_cookie __initdata; |
fe4b991d | 1092 | |
b5813c16 | 1093 | static void __init dummy_tlb_flush_all(void *cookie) |
fe4b991d WD |
1094 | { |
1095 | WARN_ON(cookie != cfg_cookie); | |
1096 | } | |
1097 | ||
b5813c16 RM |
1098 | static void __init dummy_tlb_flush(unsigned long iova, size_t size, |
1099 | size_t granule, void *cookie) | |
fe4b991d WD |
1100 | { |
1101 | WARN_ON(cookie != cfg_cookie); | |
1102 | WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); | |
1103 | } | |
1104 | ||
b5813c16 RM |
1105 | static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather, |
1106 | unsigned long iova, size_t granule, | |
1107 | void *cookie) | |
10b7a7d9 | 1108 | { |
abfd6fe0 | 1109 | dummy_tlb_flush(iova, granule, granule, cookie); |
10b7a7d9 WD |
1110 | } |
1111 | ||
298f7889 | 1112 | static const struct iommu_flush_ops dummy_tlb_ops __initconst = { |
fe4b991d | 1113 | .tlb_flush_all = dummy_tlb_flush_all, |
10b7a7d9 WD |
1114 | .tlb_flush_walk = dummy_tlb_flush, |
1115 | .tlb_flush_leaf = dummy_tlb_flush, | |
abfd6fe0 | 1116 | .tlb_add_page = dummy_tlb_add_page, |
fe4b991d WD |
1117 | }; |
1118 | ||
1119 | static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops) | |
1120 | { | |
1121 | struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
1122 | struct io_pgtable_cfg *cfg = &data->iop.cfg; | |
1123 | ||
1124 | pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n", | |
1125 | cfg->pgsize_bitmap, cfg->ias); | |
5fb190b0 | 1126 | pr_err("data: %d levels, 0x%zx pgd_size, %u pg_shift, %u bits_per_level, pgd @ %p\n", |
c79278c1 | 1127 | ARM_LPAE_MAX_LEVELS - data->start_level, ARM_LPAE_PGD_SIZE(data), |
5fb190b0 | 1128 | ilog2(ARM_LPAE_GRANULE(data)), data->bits_per_level, data->pgd); |
fe4b991d WD |
1129 | } |
1130 | ||
1131 | #define __FAIL(ops, i) ({ \ | |
1132 | WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \ | |
1133 | arm_lpae_dump_ops(ops); \ | |
1134 | selftest_running = false; \ | |
1135 | -EFAULT; \ | |
1136 | }) | |
1137 | ||
1138 | static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg) | |
1139 | { | |
9062c1d0 | 1140 | static const enum io_pgtable_fmt fmts[] __initconst = { |
fe4b991d WD |
1141 | ARM_64_LPAE_S1, |
1142 | ARM_64_LPAE_S2, | |
1143 | }; | |
1144 | ||
1145 | int i, j; | |
1146 | unsigned long iova; | |
1147 | size_t size; | |
1148 | struct io_pgtable_ops *ops; | |
1149 | ||
1150 | selftest_running = true; | |
1151 | ||
1152 | for (i = 0; i < ARRAY_SIZE(fmts); ++i) { | |
1153 | cfg_cookie = cfg; | |
1154 | ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg); | |
1155 | if (!ops) { | |
1156 | pr_err("selftest: failed to allocate io pgtable ops\n"); | |
1157 | return -ENOMEM; | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * Initial sanity checks. | |
1162 | * Empty page tables shouldn't provide any translations. | |
1163 | */ | |
1164 | if (ops->iova_to_phys(ops, 42)) | |
1165 | return __FAIL(ops, i); | |
1166 | ||
1167 | if (ops->iova_to_phys(ops, SZ_1G + 42)) | |
1168 | return __FAIL(ops, i); | |
1169 | ||
1170 | if (ops->iova_to_phys(ops, SZ_2G + 42)) | |
1171 | return __FAIL(ops, i); | |
1172 | ||
1173 | /* | |
1174 | * Distinct mappings of different granule sizes. | |
1175 | */ | |
1176 | iova = 0; | |
4ae8a5c5 | 1177 | for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) { |
fe4b991d WD |
1178 | size = 1UL << j; |
1179 | ||
1180 | if (ops->map(ops, iova, iova, size, IOMMU_READ | | |
1181 | IOMMU_WRITE | | |
1182 | IOMMU_NOEXEC | | |
1183 | IOMMU_CACHE)) | |
1184 | return __FAIL(ops, i); | |
1185 | ||
1186 | /* Overlapping mappings */ | |
1187 | if (!ops->map(ops, iova, iova + size, size, | |
1188 | IOMMU_READ | IOMMU_NOEXEC)) | |
1189 | return __FAIL(ops, i); | |
1190 | ||
1191 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
1192 | return __FAIL(ops, i); | |
1193 | ||
1194 | iova += SZ_1G; | |
fe4b991d WD |
1195 | } |
1196 | ||
1197 | /* Partial unmap */ | |
1198 | size = 1UL << __ffs(cfg->pgsize_bitmap); | |
a2d3a382 | 1199 | if (ops->unmap(ops, SZ_1G + size, size, NULL) != size) |
fe4b991d WD |
1200 | return __FAIL(ops, i); |
1201 | ||
1202 | /* Remap of partial unmap */ | |
1203 | if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ)) | |
1204 | return __FAIL(ops, i); | |
1205 | ||
1206 | if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42)) | |
1207 | return __FAIL(ops, i); | |
1208 | ||
1209 | /* Full unmap */ | |
1210 | iova = 0; | |
f793b13e | 1211 | for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) { |
fe4b991d WD |
1212 | size = 1UL << j; |
1213 | ||
a2d3a382 | 1214 | if (ops->unmap(ops, iova, size, NULL) != size) |
fe4b991d WD |
1215 | return __FAIL(ops, i); |
1216 | ||
1217 | if (ops->iova_to_phys(ops, iova + 42)) | |
1218 | return __FAIL(ops, i); | |
1219 | ||
1220 | /* Remap full block */ | |
1221 | if (ops->map(ops, iova, iova, size, IOMMU_WRITE)) | |
1222 | return __FAIL(ops, i); | |
1223 | ||
1224 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
1225 | return __FAIL(ops, i); | |
1226 | ||
1227 | iova += SZ_1G; | |
fe4b991d WD |
1228 | } |
1229 | ||
1230 | free_io_pgtable_ops(ops); | |
1231 | } | |
1232 | ||
1233 | selftest_running = false; | |
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static int __init arm_lpae_do_selftests(void) | |
1238 | { | |
9062c1d0 | 1239 | static const unsigned long pgsize[] __initconst = { |
fe4b991d WD |
1240 | SZ_4K | SZ_2M | SZ_1G, |
1241 | SZ_16K | SZ_32M, | |
1242 | SZ_64K | SZ_512M, | |
1243 | }; | |
1244 | ||
9062c1d0 | 1245 | static const unsigned int ias[] __initconst = { |
fe4b991d WD |
1246 | 32, 36, 40, 42, 44, 48, |
1247 | }; | |
1248 | ||
1249 | int i, j, pass = 0, fail = 0; | |
1250 | struct io_pgtable_cfg cfg = { | |
1251 | .tlb = &dummy_tlb_ops, | |
1252 | .oas = 48, | |
4f41845b | 1253 | .coherent_walk = true, |
fe4b991d WD |
1254 | }; |
1255 | ||
1256 | for (i = 0; i < ARRAY_SIZE(pgsize); ++i) { | |
1257 | for (j = 0; j < ARRAY_SIZE(ias); ++j) { | |
1258 | cfg.pgsize_bitmap = pgsize[i]; | |
1259 | cfg.ias = ias[j]; | |
1260 | pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n", | |
1261 | pgsize[i], ias[j]); | |
1262 | if (arm_lpae_run_tests(&cfg)) | |
1263 | fail++; | |
1264 | else | |
1265 | pass++; | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail); | |
1270 | return fail ? -EFAULT : 0; | |
1271 | } | |
1272 | subsys_initcall(arm_lpae_do_selftests); | |
1273 | #endif |