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Merge tag 'for-linus-4.11-rc1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / iommu / io-pgtable-arm-v7s.c
CommitLineData
e5fc9753
RM		 1/*
2 * CPU-agnostic ARM page table allocator.
3 *
4 * ARMv7 Short-descriptor format, supporting
5 * - Basic memory attributes
6 * - Simplified access permissions (AP[2:1] model)
7 * - Backwards-compatible TEX remap
8 * - Large pages/supersections (if indicated by the caller)
9 *
10 * Not supporting:
11 * - Legacy access permissions (AP[2:0] model)
12 *
13 * Almost certainly never supporting:
14 * - PXN
15 * - Domains
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 *
29 * Copyright (C) 2014-2015 ARM Limited
30 * Copyright (c) 2014-2015 MediaTek Inc.
31 */
32
33#define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
34
35#include <linux/dma-mapping.h>
36#include <linux/gfp.h>
37#include <linux/iommu.h>
38#include <linux/kernel.h>
39#include <linux/kmemleak.h>
40#include <linux/sizes.h>
41#include <linux/slab.h>
42#include <linux/types.h>
43
44#include <asm/barrier.h>
45
46#include "io-pgtable.h"
47
48/* Struct accessors */
49#define io_pgtable_to_data(x) \
50 container_of((x), struct arm_v7s_io_pgtable, iop)
51
52#define io_pgtable_ops_to_data(x) \
53 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
54
55/*
56 * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
57 * and 12 bits in a page. With some carefully-chosen coefficients we can
58 * hide the ugly inconsistencies behind these macros and at least let the
59 * rest of the code pretend to be somewhat sane.
60 */
61#define ARM_V7S_ADDR_BITS 32
62#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
63#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
64#define ARM_V7S_TABLE_SHIFT 10
65
66#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
67#define ARM_V7S_TABLE_SIZE(lvl) \
68 (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
69
70#define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
71#define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
72#define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
73#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
74#define ARM_V7S_LVL_IDX(addr, lvl) ({ \
75 int _l = lvl; \
76 ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
77})
78
79/*
80 * Large page/supersection entries are effectively a block of 16 page/section
81 * entries, along the lines of the LPAE contiguous hint, but all with the
82 * same output address. For want of a better common name we'll call them
83 * "contiguous" versions of their respective page/section entries here, but
84 * noting the distinction (WRT to TLB maintenance) that they represent *one*
85 * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
86 */
87#define ARM_V7S_CONT_PAGES 16
88
89/* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
90#define ARM_V7S_PTE_TYPE_TABLE 0x1
91#define ARM_V7S_PTE_TYPE_PAGE 0x2
92#define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
93
94#define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
95#define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE))
96
97/* Page table bits */
98#define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
99#define ARM_V7S_ATTR_B BIT(2)
100#define ARM_V7S_ATTR_C BIT(3)
101#define ARM_V7S_ATTR_NS_TABLE BIT(3)
102#define ARM_V7S_ATTR_NS_SECTION BIT(19)
103
104#define ARM_V7S_CONT_SECTION BIT(18)
105#define ARM_V7S_CONT_PAGE_XN_SHIFT 15
106
107/*
108 * The attribute bits are consistently ordered*, but occupy bits [17:10] of
109 * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
110 * fields relative to that 8-bit block, plus a total shift relative to the PTE.
111 */
112#define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
113
114#define ARM_V7S_ATTR_MASK 0xff
115#define ARM_V7S_ATTR_AP0 BIT(0)
116#define ARM_V7S_ATTR_AP1 BIT(1)
117#define ARM_V7S_ATTR_AP2 BIT(5)
118#define ARM_V7S_ATTR_S BIT(6)
119#define ARM_V7S_ATTR_NG BIT(7)
120#define ARM_V7S_TEX_SHIFT 2
121#define ARM_V7S_TEX_MASK 0x7
122#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
123
1afe2319
YW		 124#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
125
e5fc9753
RM		 126/* *well, except for TEX on level 2 large pages, of course :( */
127#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
128#define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
129
130/* Simplified access permissions */
131#define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
132#define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
133#define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
134
135/* Register bits */
136#define ARM_V7S_RGN_NC 0
137#define ARM_V7S_RGN_WBWA 1
138#define ARM_V7S_RGN_WT 2
139#define ARM_V7S_RGN_WB 3
140
141#define ARM_V7S_PRRR_TYPE_DEVICE 1
142#define ARM_V7S_PRRR_TYPE_NORMAL 2
143#define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
144#define ARM_V7S_PRRR_DS0 BIT(16)
145#define ARM_V7S_PRRR_DS1 BIT(17)
146#define ARM_V7S_PRRR_NS0 BIT(18)
147#define ARM_V7S_PRRR_NS1 BIT(19)
148#define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
149
150#define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
151#define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
152
153#define ARM_V7S_TTBR_S BIT(1)
154#define ARM_V7S_TTBR_NOS BIT(5)
155#define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
156#define ARM_V7S_TTBR_IRGN_ATTR(attr) \
157 ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
158
159#define ARM_V7S_TCR_PD1 BIT(5)
160
161typedef u32 arm_v7s_iopte;
162
163static bool selftest_running;
164
165struct arm_v7s_io_pgtable {
166 struct io_pgtable iop;
167
168 arm_v7s_iopte *pgd;
169 struct kmem_cache *l2_tables;
170};
171
172static dma_addr_t __arm_v7s_dma_addr(void *pages)
173{
174 return (dma_addr_t)virt_to_phys(pages);
175}
176
177static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
178{
179 if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
180 pte &= ARM_V7S_TABLE_MASK;
181 else
182 pte &= ARM_V7S_LVL_MASK(lvl);
183 return phys_to_virt(pte);
184}
185
186static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
187 struct arm_v7s_io_pgtable *data)
188{
189 struct device *dev = data->iop.cfg.iommu_dev;
190 dma_addr_t dma;
191 size_t size = ARM_V7S_TABLE_SIZE(lvl);
192 void *table = NULL;
193
194 if (lvl == 1)
195 table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size));
196 else if (lvl == 2)
048b31ca 197 table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA);
e5fc9753
RM		 198 if (table && !selftest_running) {
199 dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
200 if (dma_mapping_error(dev, dma))
201 goto out_free;
202 /*
203 * We depend on the IOMMU being able to work with any physical
204 * address directly, so if the DMA layer suggests otherwise by
205 * translating or truncating them, that bodes very badly...
206 */
207 if (dma != virt_to_phys(table))
208 goto out_unmap;
209 }
210 kmemleak_ignore(table);
211 return table;
212
213out_unmap:
214 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
215 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
216out_free:
217 if (lvl == 1)
218 free_pages((unsigned long)table, get_order(size));
219 else
220 kmem_cache_free(data->l2_tables, table);
221 return NULL;
222}
223
224static void __arm_v7s_free_table(void *table, int lvl,
225 struct arm_v7s_io_pgtable *data)
226{
227 struct device *dev = data->iop.cfg.iommu_dev;
228 size_t size = ARM_V7S_TABLE_SIZE(lvl);
229
230 if (!selftest_running)
231 dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
232 DMA_TO_DEVICE);
233 if (lvl == 1)
234 free_pages((unsigned long)table, get_order(size));
235 else
236 kmem_cache_free(data->l2_tables, table);
237}
238
239static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
240 struct io_pgtable_cfg *cfg)
241{
242 if (selftest_running)
243 return;
244
245 dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
246 num_entries * sizeof(*ptep), DMA_TO_DEVICE);
247}
248static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
249 int num_entries, struct io_pgtable_cfg *cfg)
250{
251 int i;
252
253 for (i = 0; i < num_entries; i++)
254 ptep[i] = pte;
255
256 __arm_v7s_pte_sync(ptep, num_entries, cfg);
257}
258
259static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
260 struct io_pgtable_cfg *cfg)
261{
262 bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
e88ccab1 263 arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
e5fc9753 264
e88ccab1
RM		 265 if (!(prot & IOMMU_MMIO))
266 pte |= ARM_V7S_ATTR_TEX(1);
e5fc9753 267 if (ap) {
5baf1e9d
RM		 268 pte |= ARM_V7S_PTE_AF;
269 if (!(prot & IOMMU_PRIV))
270 pte |= ARM_V7S_PTE_AP_UNPRIV;
e5fc9753
RM		 271 if (!(prot & IOMMU_WRITE))
272 pte |= ARM_V7S_PTE_AP_RDONLY;
273 }
274 pte <<= ARM_V7S_ATTR_SHIFT(lvl);
275
276 if ((prot & IOMMU_NOEXEC) && ap)
277 pte |= ARM_V7S_ATTR_XN(lvl);
e88ccab1
RM		 278 if (prot & IOMMU_MMIO)
279 pte |= ARM_V7S_ATTR_B;
280 else if (prot & IOMMU_CACHE)
e5fc9753
RM		 281 pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
282
283 return pte;
284}
285
286static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
287{
288 int prot = IOMMU_READ;
e88ccab1 289 arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
e5fc9753 290
e633fc7a 291 if (!(attr & ARM_V7S_PTE_AP_RDONLY))
e5fc9753 292 prot |= IOMMU_WRITE;
5baf1e9d
RM		 293 if (!(attr & ARM_V7S_PTE_AP_UNPRIV))
294 prot |= IOMMU_PRIV;
e88ccab1
RM		 295 if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
296 prot |= IOMMU_MMIO;
297 else if (pte & ARM_V7S_ATTR_C)
e5fc9753 298 prot |= IOMMU_CACHE;
e633fc7a
RM		 299 if (pte & ARM_V7S_ATTR_XN(lvl))
300 prot |= IOMMU_NOEXEC;
e5fc9753
RM		 301
302 return prot;
303}
304
305static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
306{
307 if (lvl == 1) {
308 pte |= ARM_V7S_CONT_SECTION;
309 } else if (lvl == 2) {
310 arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
311 arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
312
313 pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
314 pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
315 (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
316 ARM_V7S_PTE_TYPE_CONT_PAGE;
317 }
318 return pte;
319}
320
321static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
322{
323 if (lvl == 1) {
324 pte &= ~ARM_V7S_CONT_SECTION;
325 } else if (lvl == 2) {
326 arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
327 arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
328 ARM_V7S_CONT_PAGE_TEX_SHIFT);
329
330 pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
331 pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
332 (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
333 ARM_V7S_PTE_TYPE_PAGE;
334 }
335 return pte;
336}
337
338static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
339{
340 if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
341 return pte & ARM_V7S_CONT_SECTION;
342 else if (lvl == 2)
343 return !(pte & ARM_V7S_PTE_TYPE_PAGE);
344 return false;
345}
346
347static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long,
348 size_t, int, arm_v7s_iopte *);
349
350static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
351 unsigned long iova, phys_addr_t paddr, int prot,
352 int lvl, int num_entries, arm_v7s_iopte *ptep)
353{
354 struct io_pgtable_cfg *cfg = &data->iop.cfg;
355 arm_v7s_iopte pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
356 int i;
357
358 for (i = 0; i < num_entries; i++)
359 if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
360 /*
361 * We need to unmap and free the old table before
362 * overwriting it with a block entry.
363 */
364 arm_v7s_iopte *tblp;
365 size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
366
367 tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
368 if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz,
369 sz, lvl, tblp) != sz))
370 return -EINVAL;
371 } else if (ptep[i]) {
372 /* We require an unmap first */
373 WARN_ON(!selftest_running);
374 return -EEXIST;
375 }
376
377 pte |= ARM_V7S_PTE_TYPE_PAGE;
378 if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
379 pte |= ARM_V7S_ATTR_NS_SECTION;
380
1afe2319
YW		 381 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
382 pte |= ARM_V7S_ATTR_MTK_4GB;
383
e5fc9753
RM		 384 if (num_entries > 1)
385 pte = arm_v7s_pte_to_cont(pte, lvl);
386
387 pte |= paddr & ARM_V7S_LVL_MASK(lvl);
388
389 __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
390 return 0;
391}
392
393static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
394 phys_addr_t paddr, size_t size, int prot,
395 int lvl, arm_v7s_iopte *ptep)
396{
397 struct io_pgtable_cfg *cfg = &data->iop.cfg;
398 arm_v7s_iopte pte, *cptep;
399 int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
400
401 /* Find our entry at the current level */
402 ptep += ARM_V7S_LVL_IDX(iova, lvl);
403
404 /* If we can install a leaf entry at this level, then do so */
405 if (num_entries)
406 return arm_v7s_init_pte(data, iova, paddr, prot,
407 lvl, num_entries, ptep);
408
409 /* We can't allocate tables at the final level */
410 if (WARN_ON(lvl == 2))
411 return -EINVAL;
412
413 /* Grab a pointer to the next level */
414 pte = *ptep;
415 if (!pte) {
416 cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
417 if (!cptep)
418 return -ENOMEM;
419
420 pte = virt_to_phys(cptep) | ARM_V7S_PTE_TYPE_TABLE;
421 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
422 pte |= ARM_V7S_ATTR_NS_TABLE;
423
424 __arm_v7s_set_pte(ptep, pte, 1, cfg);
425 } else {
426 cptep = iopte_deref(pte, lvl);
427 }
428
429 /* Rinse, repeat */
430 return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep);
431}
432
433static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
434 phys_addr_t paddr, size_t size, int prot)
435{
436 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
507e4c9d 437 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 438 int ret;
439
440 /* If no access, then nothing to do */
441 if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
442 return 0;
443
444 ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd);
445 /*
446 * Synchronise all PTE updates for the new mapping before there's
447 * a chance for anything to kick off a table walk for the new iova.
448 */
507e4c9d
RM		 449 if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) {
450 io_pgtable_tlb_add_flush(iop, iova, size,
451 ARM_V7S_BLOCK_SIZE(2), false);
452 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 453 } else {
454 wmb();
455 }
456
457 return ret;
458}
459
460static void arm_v7s_free_pgtable(struct io_pgtable *iop)
461{
462 struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
463 int i;
464
465 for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
466 arm_v7s_iopte pte = data->pgd[i];
467
468 if (ARM_V7S_PTE_IS_TABLE(pte, 1))
469 __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
470 }
471 __arm_v7s_free_table(data->pgd, 1, data);
472 kmem_cache_destroy(data->l2_tables);
473 kfree(data);
474}
475
476static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
477 unsigned long iova, int idx, int lvl,
478 arm_v7s_iopte *ptep)
479{
507e4c9d 480 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 481 arm_v7s_iopte pte;
482 size_t size = ARM_V7S_BLOCK_SIZE(lvl);
483 int i;
484
485 ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
486 pte = arm_v7s_cont_to_pte(*ptep, lvl);
487 for (i = 0; i < ARM_V7S_CONT_PAGES; i++) {
488 ptep[i] = pte;
489 pte += size;
490 }
491
507e4c9d 492 __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
e5fc9753
RM		 493
494 size *= ARM_V7S_CONT_PAGES;
507e4c9d
RM		 495 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
496 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 497}
498
499static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
500 unsigned long iova, size_t size,
501 arm_v7s_iopte *ptep)
502{
503 unsigned long blk_start, blk_end, blk_size;
504 phys_addr_t blk_paddr;
505 arm_v7s_iopte table = 0;
e5fc9753
RM		 506 int prot = arm_v7s_pte_to_prot(*ptep, 1);
507
508 blk_size = ARM_V7S_BLOCK_SIZE(1);
509 blk_start = iova & ARM_V7S_LVL_MASK(1);
510 blk_end = blk_start + ARM_V7S_BLOCK_SIZE(1);
511 blk_paddr = *ptep & ARM_V7S_LVL_MASK(1);
512
513 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
514 arm_v7s_iopte *tablep;
515
516 /* Unmap! */
517 if (blk_start == iova)
518 continue;
519
520 /* __arm_v7s_map expects a pointer to the start of the table */
521 tablep = &table - ARM_V7S_LVL_IDX(blk_start, 1);
522 if (__arm_v7s_map(data, blk_start, blk_paddr, size, prot, 1,
523 tablep) < 0) {
524 if (table) {
525 /* Free the table we allocated */
526 tablep = iopte_deref(table, 1);
527 __arm_v7s_free_table(tablep, 2, data);
528 }
529 return 0; /* Bytes unmapped */
530 }
531 }
532
507e4c9d 533 __arm_v7s_set_pte(ptep, table, 1, &data->iop.cfg);
e5fc9753 534 iova &= ~(blk_size - 1);
507e4c9d 535 io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true);
e5fc9753
RM		 536 return size;
537}
538
539static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
540 unsigned long iova, size_t size, int lvl,
541 arm_v7s_iopte *ptep)
542{
543 arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
507e4c9d 544 struct io_pgtable *iop = &data->iop;
e5fc9753
RM		 545 int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
546
547 /* Something went horribly wrong and we ran out of page table */
548 if (WARN_ON(lvl > 2))
549 return 0;
550
551 idx = ARM_V7S_LVL_IDX(iova, lvl);
552 ptep += idx;
553 do {
554 if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i])))
555 return 0;
556 pte[i] = ptep[i];
557 } while (++i < num_entries);
558
559 /*
560 * If we've hit a contiguous 'large page' entry at this level, it
561 * needs splitting first, unless we're unmapping the whole lot.
562 */
563 if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl))
564 arm_v7s_split_cont(data, iova, idx, lvl, ptep);
565
566 /* If the size matches this level, we're in the right place */
567 if (num_entries) {
568 size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
569
507e4c9d 570 __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
e5fc9753
RM		 571
572 for (i = 0; i < num_entries; i++) {
573 if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
574 /* Also flush any partial walks */
507e4c9d
RM		 575 io_pgtable_tlb_add_flush(iop, iova, blk_size,
576 ARM_V7S_BLOCK_SIZE(lvl + 1), false);
577 io_pgtable_tlb_sync(iop);
e5fc9753
RM		 578 ptep = iopte_deref(pte[i], lvl);
579 __arm_v7s_free_table(ptep, lvl + 1, data);
580 } else {
507e4c9d
RM		 581 io_pgtable_tlb_add_flush(iop, iova, blk_size,
582 blk_size, true);
e5fc9753
RM		 583 }
584 iova += blk_size;
585 }
586 return size;
587 } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
588 /*
589 * Insert a table at the next level to map the old region,
590 * minus the part we want to unmap
591 */
592 return arm_v7s_split_blk_unmap(data, iova, size, ptep);
593 }
594
595 /* Keep on walkin' */
596 ptep = iopte_deref(pte[0], lvl);
597 return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
598}
599
600static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
601 size_t size)
602{
e5fc9753 603 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
507e4c9d 604 size_t unmapped;
e5fc9753
RM		 605
606 unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd);
607 if (unmapped)
507e4c9d 608 io_pgtable_tlb_sync(&data->iop);
e5fc9753
RM		 609
610 return unmapped;
611}
612
613static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
614 unsigned long iova)
615{
616 struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
617 arm_v7s_iopte *ptep = data->pgd, pte;
618 int lvl = 0;
619 u32 mask;
620
621 do {
622 pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)];
623 ptep = iopte_deref(pte, lvl);
624 } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
625
626 if (!ARM_V7S_PTE_IS_VALID(pte))
627 return 0;
628
629 mask = ARM_V7S_LVL_MASK(lvl);
630 if (arm_v7s_pte_is_cont(pte, lvl))
631 mask *= ARM_V7S_CONT_PAGES;
632 return (pte & mask) | (iova & ~mask);
633}
634
635static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
636 void *cookie)
637{
638 struct arm_v7s_io_pgtable *data;
639
82db33dc
RM		 640#ifdef PHYS_OFFSET
641 if (upper_32_bits(PHYS_OFFSET))
642 return NULL;
643#endif
e5fc9753
RM		 644 if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS)
645 return NULL;
646
3850db49
RM		 647 if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
648 IO_PGTABLE_QUIRK_NO_PERMS |
1afe2319
YW		 649 IO_PGTABLE_QUIRK_TLBI_ON_MAP |
650 IO_PGTABLE_QUIRK_ARM_MTK_4GB))
3850db49
RM		 651 return NULL;
652
1afe2319
YW		 653 /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
654 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
655 !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
656 return NULL;
657
e5fc9753
RM		 658 data = kmalloc(sizeof(*data), GFP_KERNEL);
659 if (!data)
660 return NULL;
661
662 data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
663 ARM_V7S_TABLE_SIZE(2),
664 ARM_V7S_TABLE_SIZE(2),
665 SLAB_CACHE_DMA, NULL);
666 if (!data->l2_tables)
667 goto out_free_data;
668
669 data->iop.ops = (struct io_pgtable_ops) {
670 .map = arm_v7s_map,
671 .unmap = arm_v7s_unmap,
672 .iova_to_phys = arm_v7s_iova_to_phys,
673 };
674
675 /* We have to do this early for __arm_v7s_alloc_table to work... */
676 data->iop.cfg = *cfg;
677
678 /*
679 * Unless the IOMMU driver indicates supersection support by
680 * having SZ_16M set in the initial bitmap, they won't be used.
681 */
682 cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
683
684 /* TCR: T0SZ=0, disable TTBR1 */
685 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1;
686
687 /*
688 * TEX remap: the indices used map to the closest equivalent types
689 * under the non-TEX-remap interpretation of those attribute bits,
690 * excepting various implementation-defined aspects of shareability.
691 */
692 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
693 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
694 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
695 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
696 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
697 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
698 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
699
700 /* Looking good; allocate a pgd */
701 data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
702 if (!data->pgd)
703 goto out_free_data;
704
705 /* Ensure the empty pgd is visible before any actual TTBR write */
706 wmb();
707
708 /* TTBRs */
709 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) |
710 ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS |
711 ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
712 ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA);
713 cfg->arm_v7s_cfg.ttbr[1] = 0;
714 return &data->iop;
715
716out_free_data:
717 kmem_cache_destroy(data->l2_tables);
718 kfree(data);
719 return NULL;
720}
721
722struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
723 .alloc = arm_v7s_alloc_pgtable,
724 .free = arm_v7s_free_pgtable,
725};
726
727#ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
728
729static struct io_pgtable_cfg *cfg_cookie;
730
731static void dummy_tlb_flush_all(void *cookie)
732{
733 WARN_ON(cookie != cfg_cookie);
734}
735
736static void dummy_tlb_add_flush(unsigned long iova, size_t size,
737 size_t granule, bool leaf, void *cookie)
738{
739 WARN_ON(cookie != cfg_cookie);
740 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
741}
742
743static void dummy_tlb_sync(void *cookie)
744{
745 WARN_ON(cookie != cfg_cookie);
746}
747
748static struct iommu_gather_ops dummy_tlb_ops = {
749 .tlb_flush_all = dummy_tlb_flush_all,
750 .tlb_add_flush = dummy_tlb_add_flush,
751 .tlb_sync = dummy_tlb_sync,
752};
753
754#define __FAIL(ops) ({ \
755 WARN(1, "selftest: test failed\n"); \
756 selftest_running = false; \
757 -EFAULT; \
758})
759
760static int __init arm_v7s_do_selftests(void)
761{
762 struct io_pgtable_ops *ops;
763 struct io_pgtable_cfg cfg = {
764 .tlb = &dummy_tlb_ops,
765 .oas = 32,
766 .ias = 32,
767 .quirks = IO_PGTABLE_QUIRK_ARM_NS,
768 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
769 };
770 unsigned int iova, size, iova_start;
771 unsigned int i, loopnr = 0;
772
773 selftest_running = true;
774
775 cfg_cookie = &cfg;
776
777 ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
778 if (!ops) {
779 pr_err("selftest: failed to allocate io pgtable ops\n");
780 return -EINVAL;
781 }
782
783 /*
784 * Initial sanity checks.
785 * Empty page tables shouldn't provide any translations.
786 */
787 if (ops->iova_to_phys(ops, 42))
788 return __FAIL(ops);
789
790 if (ops->iova_to_phys(ops, SZ_1G + 42))
791 return __FAIL(ops);
792
793 if (ops->iova_to_phys(ops, SZ_2G + 42))
794 return __FAIL(ops);
795
796 /*
797 * Distinct mappings of different granule sizes.
798 */
799 iova = 0;
4ae8a5c5 800 for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
e5fc9753
RM		 801 size = 1UL << i;
802 if (ops->map(ops, iova, iova, size, IOMMU_READ |
803 IOMMU_WRITE |
804 IOMMU_NOEXEC |
805 IOMMU_CACHE))
806 return __FAIL(ops);
807
808 /* Overlapping mappings */
809 if (!ops->map(ops, iova, iova + size, size,
810 IOMMU_READ | IOMMU_NOEXEC))
811 return __FAIL(ops);
812
813 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
814 return __FAIL(ops);
815
816 iova += SZ_16M;
e5fc9753
RM		 817 loopnr++;
818 }
819
820 /* Partial unmap */
821 i = 1;
822 size = 1UL << __ffs(cfg.pgsize_bitmap);
823 while (i < loopnr) {
824 iova_start = i * SZ_16M;
825 if (ops->unmap(ops, iova_start + size, size) != size)
826 return __FAIL(ops);
827
828 /* Remap of partial unmap */
829 if (ops->map(ops, iova_start + size, size, size, IOMMU_READ))
830 return __FAIL(ops);
831
832 if (ops->iova_to_phys(ops, iova_start + size + 42)
833 != (size + 42))
834 return __FAIL(ops);
835 i++;
836 }
837
838 /* Full unmap */
839 iova = 0;
840 i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
841 while (i != BITS_PER_LONG) {
842 size = 1UL << i;
843
844 if (ops->unmap(ops, iova, size) != size)
845 return __FAIL(ops);
846
847 if (ops->iova_to_phys(ops, iova + 42))
848 return __FAIL(ops);
849
850 /* Remap full block */
851 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
852 return __FAIL(ops);
853
854 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
855 return __FAIL(ops);
856
857 iova += SZ_16M;
858 i++;
859 i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
860 }
861
862 free_io_pgtable_ops(ops);
863
864 selftest_running = false;
865
866 pr_info("self test ok\n");
867 return 0;
868}
869subsys_initcall(arm_v7s_do_selftests);
870#endif
Linux 6.x block layer and io_uring tree(s)