[linux-2.6-block.git] / drivers / iommu / intel-pasid.c

// SPDX-License-Identifier: GPL-2.0
/**
 * intel-pasid.c - PASID idr, table and entry manipulation
 *
 * Copyright (C) 2018 Intel Corporation
 *
 * Author: Lu Baolu <baolu.lu@linux.intel.com>
 */

#define pr_fmt(fmt)	"DMAR: " fmt

#include <linux/bitops.h>
#include <linux/cpufeature.h>
#include <linux/dmar.h>
#include <linux/intel-iommu.h>
#include <linux/iommu.h>
#include <linux/memory.h>
#include <linux/pci.h>
#include <linux/pci-ats.h>
#include <linux/spinlock.h>

#include "intel-pasid.h"

/*
 * Intel IOMMU system wide PASID name space:
 */
static DEFINE_SPINLOCK(pasid_lock);
u32 intel_pasid_max_id = PASID_MAX;
static DEFINE_IDR(pasid_idr);

int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp)
{
	int ret, min, max;

	min = max_t(int, start, PASID_MIN);
	max = min_t(int, end, intel_pasid_max_id);

	WARN_ON(in_interrupt());
	idr_preload(gfp);
	spin_lock(&pasid_lock);
	ret = idr_alloc(&pasid_idr, ptr, min, max, GFP_ATOMIC);
	spin_unlock(&pasid_lock);
	idr_preload_end();

	return ret;
}

void intel_pasid_free_id(int pasid)
{
	spin_lock(&pasid_lock);
	idr_remove(&pasid_idr, pasid);
	spin_unlock(&pasid_lock);
}

void *intel_pasid_lookup_id(int pasid)
{
	void *p;

	spin_lock(&pasid_lock);
	p = idr_find(&pasid_idr, pasid);
	spin_unlock(&pasid_lock);

	return p;
}

/*
 * Per device pasid table management:
 */
static inline void
device_attach_pasid_table(struct device_domain_info *info,
			  struct pasid_table *pasid_table)
{
	info->pasid_table = pasid_table;
	list_add(&info->table, &pasid_table->dev);
}

static inline void
device_detach_pasid_table(struct device_domain_info *info,
			  struct pasid_table *pasid_table)
{
	info->pasid_table = NULL;
	list_del(&info->table);
}

struct pasid_table_opaque {
	struct pasid_table	**pasid_table;
	int			segment;
	int			bus;
	int			devfn;
};

static int search_pasid_table(struct device_domain_info *info, void *opaque)
{
	struct pasid_table_opaque *data = opaque;

	if (info->iommu->segment == data->segment &&
	    info->bus == data->bus &&
	    info->devfn == data->devfn &&
	    info->pasid_table) {
		*data->pasid_table = info->pasid_table;
		return 1;
	}

	return 0;
}

static int get_alias_pasid_table(struct pci_dev *pdev, u16 alias, void *opaque)
{
	struct pasid_table_opaque *data = opaque;

	data->segment = pci_domain_nr(pdev->bus);
	data->bus = PCI_BUS_NUM(alias);
	data->devfn = alias & 0xff;

	return for_each_device_domain(&search_pasid_table, data);
}

/*
 * Allocate a pasid table for @dev. It should be called in a
 * single-thread context.
 */
int intel_pasid_alloc_table(struct device *dev)
{
	struct device_domain_info *info;
	struct pasid_table *pasid_table;
	struct pasid_table_opaque data;
	struct page *pages;
	int max_pasid = 0;
	int ret, order;
	int size;

	might_sleep();
	info = dev->archdata.iommu;
	if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table))
		return -EINVAL;

	/* DMA alias device already has a pasid table, use it: */
	data.pasid_table = &pasid_table;
	ret = pci_for_each_dma_alias(to_pci_dev(dev),
				     &get_alias_pasid_table, &data);
	if (ret)
		goto attach_out;

	pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
	if (!pasid_table)
		return -ENOMEM;
	INIT_LIST_HEAD(&pasid_table->dev);

	if (info->pasid_supported)
		max_pasid = min_t(int, pci_max_pasids(to_pci_dev(dev)),
				  intel_pasid_max_id);

	size = max_pasid >> (PASID_PDE_SHIFT - 3);
	order = size ? get_order(size) : 0;
	pages = alloc_pages_node(info->iommu->node,
				 GFP_KERNEL | __GFP_ZERO, order);
	if (!pages)
		return -ENOMEM;

	pasid_table->table = page_address(pages);
	pasid_table->order = order;
	pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);

attach_out:
	device_attach_pasid_table(info, pasid_table);

	return 0;
}

/* Get PRESENT bit of a PASID directory entry. */
static inline bool
pasid_pde_is_present(struct pasid_dir_entry *pde)
{
	return READ_ONCE(pde->val) & PASID_PTE_PRESENT;
}

/* Get PASID table from a PASID directory entry. */
static inline struct pasid_entry *
get_pasid_table_from_pde(struct pasid_dir_entry *pde)
{
	if (!pasid_pde_is_present(pde))
		return NULL;

	return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK);
}

void intel_pasid_free_table(struct device *dev)
{
	struct device_domain_info *info;
	struct pasid_table *pasid_table;
	struct pasid_dir_entry *dir;
	struct pasid_entry *table;
	int i, max_pde;

	info = dev->archdata.iommu;
	if (!info || !dev_is_pci(dev) || !info->pasid_table)
		return;

	pasid_table = info->pasid_table;
	device_detach_pasid_table(info, pasid_table);

	if (!list_empty(&pasid_table->dev))
		return;

	/* Free scalable mode PASID directory tables: */
	dir = pasid_table->table;
	max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT;
	for (i = 0; i < max_pde; i++) {
		table = get_pasid_table_from_pde(&dir[i]);
		free_pgtable_page(table);
	}

	free_pages((unsigned long)pasid_table->table, pasid_table->order);
	kfree(pasid_table);
}

struct pasid_table *intel_pasid_get_table(struct device *dev)
{
	struct device_domain_info *info;

	info = dev->archdata.iommu;
	if (!info)
		return NULL;

	return info->pasid_table;
}

int intel_pasid_get_dev_max_id(struct device *dev)
{
	struct device_domain_info *info;

	info = dev->archdata.iommu;
	if (!info || !info->pasid_table)
		return 0;

	return info->pasid_table->max_pasid;
}

struct pasid_entry *intel_pasid_get_entry(struct device *dev, int pasid)
{
	struct device_domain_info *info;
	struct pasid_table *pasid_table;
	struct pasid_dir_entry *dir;
	struct pasid_entry *entries;
	int dir_index, index;

	pasid_table = intel_pasid_get_table(dev);
	if (WARN_ON(!pasid_table || pasid < 0 ||
		    pasid >= intel_pasid_get_dev_max_id(dev)))
		return NULL;

	dir = pasid_table->table;
	info = dev->archdata.iommu;
	dir_index = pasid >> PASID_PDE_SHIFT;
	index = pasid & PASID_PTE_MASK;

	spin_lock(&pasid_lock);
	entries = get_pasid_table_from_pde(&dir[dir_index]);
	if (!entries) {
		entries = alloc_pgtable_page(info->iommu->node);
		if (!entries) {
			spin_unlock(&pasid_lock);
			return NULL;
		}

		WRITE_ONCE(dir[dir_index].val,
			   (u64)virt_to_phys(entries) | PASID_PTE_PRESENT);
	}
	spin_unlock(&pasid_lock);

	return &entries[index];
}

/*
 * Interfaces for PASID table entry manipulation:
 */
static inline void pasid_clear_entry(struct pasid_entry *pe)
{
	WRITE_ONCE(pe->val[0], 0);
	WRITE_ONCE(pe->val[1], 0);
	WRITE_ONCE(pe->val[2], 0);
	WRITE_ONCE(pe->val[3], 0);
	WRITE_ONCE(pe->val[4], 0);
	WRITE_ONCE(pe->val[5], 0);
	WRITE_ONCE(pe->val[6], 0);
	WRITE_ONCE(pe->val[7], 0);
}

static void intel_pasid_clear_entry(struct device *dev, int pasid)
{
	struct pasid_entry *pe;

	pe = intel_pasid_get_entry(dev, pasid);
	if (WARN_ON(!pe))
		return;

	pasid_clear_entry(pe);
}

static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)
{
	u64 old;

	old = READ_ONCE(*ptr);
	WRITE_ONCE(*ptr, (old & ~mask) | bits);
}

/*
 * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode
 * PASID entry.
 */
static inline void
pasid_set_domain_id(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
}

/*
 * Get domain ID value of a scalable mode PASID entry.
 */
static inline u16
pasid_get_domain_id(struct pasid_entry *pe)
{
	return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
}

/*
 * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)
 * of a scalable mode PASID entry.
 */
static inline void
pasid_set_slptr(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
}

/*
 * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID
 * entry.
 */
static inline void
pasid_set_address_width(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
}

/*
 * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)
 * of a scalable mode PASID entry.
 */
static inline void
pasid_set_translation_type(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
}

/*
 * Enable fault processing by clearing the FPD(Fault Processing
 * Disable) field (Bit 1) of a scalable mode PASID entry.
 */
static inline void pasid_set_fault_enable(struct pasid_entry *pe)
{
	pasid_set_bits(&pe->val[0], 1 << 1, 0);
}

/*
 * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a
 * scalable mode PASID entry.
 */
static inline void pasid_set_sre(struct pasid_entry *pe)
{
	pasid_set_bits(&pe->val[2], 1 << 0, 1);
}

/*
 * Setup the P(Present) field (Bit 0) of a scalable mode PASID
 * entry.
 */
static inline void pasid_set_present(struct pasid_entry *pe)
{
	pasid_set_bits(&pe->val[0], 1 << 0, 1);
}

/*
 * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID
 * entry.
 */
static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
{
	pasid_set_bits(&pe->val[1], 1 << 23, value);
}

/*
 * Setup the First Level Page table Pointer field (Bit 140~191)
 * of a scalable mode PASID entry.
 */
static inline void
pasid_set_flptr(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
}

/*
 * Setup the First Level Paging Mode field (Bit 130~131) of a
 * scalable mode PASID entry.
 */
static inline void
pasid_set_flpm(struct pasid_entry *pe, u64 value)
{
	pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
}

static void
pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
				    u16 did, int pasid)
{
	struct qi_desc desc;

	desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
	desc.qw1 = 0;
	desc.qw2 = 0;
	desc.qw3 = 0;

	qi_submit_sync(&desc, iommu);
}

static void
iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid)
{
	struct qi_desc desc;

	desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
			QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
	desc.qw1 = 0;
	desc.qw2 = 0;
	desc.qw3 = 0;

	qi_submit_sync(&desc, iommu);
}

static void
devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
			       struct device *dev, int pasid)
{
	struct device_domain_info *info;
	u16 sid, qdep, pfsid;

	info = dev->archdata.iommu;
	if (!info || !info->ats_enabled)
		return;

	sid = info->bus << 8 | info->devfn;
	qdep = info->ats_qdep;
	pfsid = info->pfsid;

	qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
}

void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
				 struct device *dev, int pasid)
{
	struct pasid_entry *pte;
	u16 did;

	pte = intel_pasid_get_entry(dev, pasid);
	if (WARN_ON(!pte))
		return;

	did = pasid_get_domain_id(pte);
	intel_pasid_clear_entry(dev, pasid);

	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(pte, sizeof(*pte));

	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
	iotlb_invalidation_with_pasid(iommu, did, pasid);

	/* Device IOTLB doesn't need to be flushed in caching mode. */
	if (!cap_caching_mode(iommu->cap))
		devtlb_invalidation_with_pasid(iommu, dev, pasid);
}

/*
 * Set up the scalable mode pasid table entry for first only
 * translation type.
 */
int intel_pasid_setup_first_level(struct intel_iommu *iommu,
				  struct device *dev, pgd_t *pgd,
				  int pasid, u16 did, int flags)
{
	struct pasid_entry *pte;

	if (!ecap_flts(iommu->ecap)) {
		pr_err("No first level translation support on %s\n",
		       iommu->name);
		return -EINVAL;
	}

	pte = intel_pasid_get_entry(dev, pasid);
	if (WARN_ON(!pte))
		return -EINVAL;

	pasid_clear_entry(pte);

	/* Setup the first level page table pointer: */
	pasid_set_flptr(pte, (u64)__pa(pgd));
	if (flags & PASID_FLAG_SUPERVISOR_MODE) {
		if (!ecap_srs(iommu->ecap)) {
			pr_err("No supervisor request support on %s\n",
			       iommu->name);
			return -EINVAL;
		}
		pasid_set_sre(pte);
	}

#ifdef CONFIG_X86
	if (cpu_feature_enabled(X86_FEATURE_LA57))
		pasid_set_flpm(pte, 1);
#endif /* CONFIG_X86 */

	pasid_set_domain_id(pte, did);
	pasid_set_address_width(pte, iommu->agaw);
	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));

	/* Setup Present and PASID Granular Transfer Type: */
	pasid_set_translation_type(pte, 1);
	pasid_set_present(pte);

	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(pte, sizeof(*pte));

	if (cap_caching_mode(iommu->cap)) {
		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
		iotlb_invalidation_with_pasid(iommu, did, pasid);
	} else {
		iommu_flush_write_buffer(iommu);
	}

	return 0;
}

/*
 * Set up the scalable mode pasid entry for second only translation type.
 */
int intel_pasid_setup_second_level(struct intel_iommu *iommu,
				   struct dmar_domain *domain,
				   struct device *dev, int pasid)
{
	struct pasid_entry *pte;
	struct dma_pte *pgd;
	u64 pgd_val;
	int agaw;
	u16 did;

	/*
	 * If hardware advertises no support for second level
	 * translation, return directly.
	 */
	if (!ecap_slts(iommu->ecap)) {
		pr_err("No second level translation support on %s\n",
		       iommu->name);
		return -EINVAL;
	}

	/*
	 * Skip top levels of page tables for iommu which has less agaw
	 * than default. Unnecessary for PT mode.
	 */
	pgd = domain->pgd;
	for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
		pgd = phys_to_virt(dma_pte_addr(pgd));
		if (!dma_pte_present(pgd)) {
			dev_err(dev, "Invalid domain page table\n");
			return -EINVAL;
		}
	}

	pgd_val = virt_to_phys(pgd);
	did = domain->iommu_did[iommu->seq_id];

	pte = intel_pasid_get_entry(dev, pasid);
	if (!pte) {
		dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
		return -ENODEV;
	}

	pasid_clear_entry(pte);
	pasid_set_domain_id(pte, did);
	pasid_set_slptr(pte, pgd_val);
	pasid_set_address_width(pte, agaw);
	pasid_set_translation_type(pte, 2);
	pasid_set_fault_enable(pte);
	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));

	/*
	 * Since it is a second level only translation setup, we should
	 * set SRE bit as well (addresses are expected to be GPAs).
	 */
	pasid_set_sre(pte);
	pasid_set_present(pte);

	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(pte, sizeof(*pte));

	if (cap_caching_mode(iommu->cap)) {
		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
		iotlb_invalidation_with_pasid(iommu, did, pasid);
	} else {
		iommu_flush_write_buffer(iommu);
	}

	return 0;
}

/*
 * Set up the scalable mode pasid entry for passthrough translation type.
 */
int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
				   struct dmar_domain *domain,
				   struct device *dev, int pasid)
{
	u16 did = FLPT_DEFAULT_DID;
	struct pasid_entry *pte;

	pte = intel_pasid_get_entry(dev, pasid);
	if (!pte) {
		dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
		return -ENODEV;
	}

	pasid_clear_entry(pte);
	pasid_set_domain_id(pte, did);
	pasid_set_address_width(pte, iommu->agaw);
	pasid_set_translation_type(pte, 4);
	pasid_set_fault_enable(pte);
	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));

	/*
	 * We should set SRE bit as well since the addresses are expected
	 * to be GPAs.
	 */
	pasid_set_sre(pte);
	pasid_set_present(pte);

	if (!ecap_coherent(iommu->ecap))
		clflush_cache_range(pte, sizeof(*pte));

	if (cap_caching_mode(iommu->cap)) {
		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
		iotlb_invalidation_with_pasid(iommu, did, pasid);
	} else {
		iommu_flush_write_buffer(iommu);
	}

	return 0;
}
Commit	Line	Data
56283174 LB	1	// SPDX-License-Identifier: GPL-2.0
	2	/**
	3	* intel-pasid.c - PASID idr, table and entry manipulation
	4	*
	5	* Copyright (C) 2018 Intel Corporation
	6	*
	7	* Author: Lu Baolu <baolu.lu@linux.intel.com>
	8	*/
	9
	10	#define pr_fmt(fmt) "DMAR: " fmt
	11
6f7db75e	12	#include <linux/bitops.h>
437f35e1	13	#include <linux/cpufeature.h>
56283174 LB	14	#include <linux/dmar.h>
	15	#include <linux/intel-iommu.h>
	16	#include <linux/iommu.h>
	17	#include <linux/memory.h>
cc580e41 LB	18	#include <linux/pci.h>
cc580e41 LB	19	#include <linux/pci-ats.h>
56283174 LB	20	#include <linux/spinlock.h>
	21
	22	#include "intel-pasid.h"
	23
	24	/*
	25	* Intel IOMMU system wide PASID name space:
	26	*/
	27	static DEFINE_SPINLOCK(pasid_lock);
	28	u32 intel_pasid_max_id = PASID_MAX;
	29	static DEFINE_IDR(pasid_idr);
	30
	31	int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp)
	32	{
	33	int ret, min, max;
	34
	35	min = max_t(int, start, PASID_MIN);
	36	max = min_t(int, end, intel_pasid_max_id);
	37
	38	WARN_ON(in_interrupt());
	39	idr_preload(gfp);
	40	spin_lock(&pasid_lock);
	41	ret = idr_alloc(&pasid_idr, ptr, min, max, GFP_ATOMIC);
	42	spin_unlock(&pasid_lock);
	43	idr_preload_end();
	44
	45	return ret;
	46	}
	47
	48	void intel_pasid_free_id(int pasid)
	49	{
	50	spin_lock(&pasid_lock);
	51	idr_remove(&pasid_idr, pasid);
	52	spin_unlock(&pasid_lock);
	53	}
	54
	55	void *intel_pasid_lookup_id(int pasid)
	56	{
	57	void *p;
	58
	59	spin_lock(&pasid_lock);
	60	p = idr_find(&pasid_idr, pasid);
	61	spin_unlock(&pasid_lock);
	62
	63	return p;
	64	}
cc580e41 LB	65
	66	/*
	67	* Per device pasid table management:
	68	*/
	69	static inline void
	70	device_attach_pasid_table(struct device_domain_info *info,
	71	struct pasid_table *pasid_table)
	72	{
	73	info->pasid_table = pasid_table;
	74	list_add(&info->table, &pasid_table->dev);
	75	}
	76
	77	static inline void
	78	device_detach_pasid_table(struct device_domain_info *info,
	79	struct pasid_table *pasid_table)
	80	{
	81	info->pasid_table = NULL;
	82	list_del(&info->table);
	83	}
	84
	85	struct pasid_table_opaque {
	86	struct pasid_table **pasid_table;
	87	int segment;
	88	int bus;
	89	int devfn;
	90	};
	91
	92	static int search_pasid_table(struct device_domain_info info, void opaque)
	93	{
	94	struct pasid_table_opaque *data = opaque;
	95
	96	if (info->iommu->segment == data->segment &&
	97	info->bus == data->bus &&
	98	info->devfn == data->devfn &&
	99	info->pasid_table) {
	100	*data->pasid_table = info->pasid_table;
	101	return 1;
	102	}
	103
	104	return 0;
	105	}
	106
	107	static int get_alias_pasid_table(struct pci_dev pdev, u16 alias, void opaque)
	108	{
	109	struct pasid_table_opaque *data = opaque;
	110
	111	data->segment = pci_domain_nr(pdev->bus);
	112	data->bus = PCI_BUS_NUM(alias);
	113	data->devfn = alias & 0xff;
	114
	115	return for_each_device_domain(&search_pasid_table, data);
	116	}
	117
	118	/*
	119	* Allocate a pasid table for @dev. It should be called in a
	120	* single-thread context.
	121	*/
	122	int intel_pasid_alloc_table(struct device *dev)
	123	{
	124	struct device_domain_info *info;
	125	struct pasid_table *pasid_table;
	126	struct pasid_table_opaque data;
	127	struct page *pages;
0bbeb01a	128	int max_pasid = 0;
cc580e41	129	int ret, order;
0bbeb01a	130	int size;
cc580e41	131
0bbeb01a	132	might_sleep();
cc580e41	133	info = dev->archdata.iommu;
0bbeb01a	134	if (WARN_ON(!info \|\| !dev_is_pci(dev) \|\| info->pasid_table))
cc580e41 LB	135	return -EINVAL;
	136
	137	/* DMA alias device already has a pasid table, use it: */
	138	data.pasid_table = &pasid_table;
	139	ret = pci_for_each_dma_alias(to_pci_dev(dev),
	140	&get_alias_pasid_table, &data);
	141	if (ret)
	142	goto attach_out;
	143
0bbeb01a	144	pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
cc580e41 LB	145	if (!pasid_table)
	146	return -ENOMEM;
	147	INIT_LIST_HEAD(&pasid_table->dev);
	148
0bbeb01a LB	149	if (info->pasid_supported)
	150	max_pasid = min_t(int, pci_max_pasids(to_pci_dev(dev)),
	151	intel_pasid_max_id);
	152
	153	size = max_pasid >> (PASID_PDE_SHIFT - 3);
	154	order = size ? get_order(size) : 0;
cc580e41	155	pages = alloc_pages_node(info->iommu->node,
0bbeb01a	156	GFP_KERNEL \| __GFP_ZERO, order);
cc580e41 LB	157	if (!pages)
	158	return -ENOMEM;
	159
	160	pasid_table->table = page_address(pages);
	161	pasid_table->order = order;
0bbeb01a	162	pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);
cc580e41 LB	163
	164	attach_out:
	165	device_attach_pasid_table(info, pasid_table);
	166
	167	return 0;
	168	}
	169
0bbeb01a LB	170	/* Get PRESENT bit of a PASID directory entry. */
	171	static inline bool
	172	pasid_pde_is_present(struct pasid_dir_entry *pde)
	173	{
	174	return READ_ONCE(pde->val) & PASID_PTE_PRESENT;
	175	}
	176
	177	/* Get PASID table from a PASID directory entry. */
	178	static inline struct pasid_entry *
	179	get_pasid_table_from_pde(struct pasid_dir_entry *pde)
	180	{
	181	if (!pasid_pde_is_present(pde))
	182	return NULL;
	183
	184	return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK);
	185	}
	186
cc580e41 LB	187	void intel_pasid_free_table(struct device *dev)
	188	{
	189	struct device_domain_info *info;
	190	struct pasid_table *pasid_table;
0bbeb01a LB	191	struct pasid_dir_entry *dir;
	192	struct pasid_entry *table;
	193	int i, max_pde;
cc580e41 LB	194
cc580e41 LB	195	info = dev->archdata.iommu;
0bbeb01a	196	if (!info \|\| !dev_is_pci(dev) \|\| !info->pasid_table)
cc580e41 LB	197	return;
	198
	199	pasid_table = info->pasid_table;
	200	device_detach_pasid_table(info, pasid_table);
	201
	202	if (!list_empty(&pasid_table->dev))
	203	return;
	204
0bbeb01a LB	205	/* Free scalable mode PASID directory tables: */
	206	dir = pasid_table->table;
	207	max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT;
	208	for (i = 0; i < max_pde; i++) {
	209	table = get_pasid_table_from_pde(&dir[i]);
	210	free_pgtable_page(table);
	211	}
	212
cc580e41 LB	213	free_pages((unsigned long)pasid_table->table, pasid_table->order);
	214	kfree(pasid_table);
	215	}
	216
	217	struct pasid_table intel_pasid_get_table(struct device dev)
	218	{
	219	struct device_domain_info *info;
	220
	221	info = dev->archdata.iommu;
	222	if (!info)
	223	return NULL;
	224
	225	return info->pasid_table;
	226	}
	227
	228	int intel_pasid_get_dev_max_id(struct device *dev)
	229	{
	230	struct device_domain_info *info;
	231
	232	info = dev->archdata.iommu;
	233	if (!info \|\| !info->pasid_table)
	234	return 0;
	235
	236	return info->pasid_table->max_pasid;
	237	}
	238
	239	struct pasid_entry intel_pasid_get_entry(struct device dev, int pasid)
	240	{
0bbeb01a	241	struct device_domain_info *info;
cc580e41	242	struct pasid_table *pasid_table;
0bbeb01a	243	struct pasid_dir_entry *dir;
cc580e41	244	struct pasid_entry *entries;
0bbeb01a	245	int dir_index, index;
cc580e41 LB	246
	247	pasid_table = intel_pasid_get_table(dev);
	248	if (WARN_ON(!pasid_table \|\| pasid < 0 \|\|
	249	pasid >= intel_pasid_get_dev_max_id(dev)))
	250	return NULL;
	251
0bbeb01a LB	252	dir = pasid_table->table;
	253	info = dev->archdata.iommu;
	254	dir_index = pasid >> PASID_PDE_SHIFT;
	255	index = pasid & PASID_PTE_MASK;
	256
	257	spin_lock(&pasid_lock);
	258	entries = get_pasid_table_from_pde(&dir[dir_index]);
	259	if (!entries) {
	260	entries = alloc_pgtable_page(info->iommu->node);
	261	if (!entries) {
	262	spin_unlock(&pasid_lock);
	263	return NULL;
	264	}
	265
	266	WRITE_ONCE(dir[dir_index].val,
	267	(u64)virt_to_phys(entries) \| PASID_PTE_PRESENT);
	268	}
	269	spin_unlock(&pasid_lock);
cc580e41	270
0bbeb01a	271	return &entries[index];
cc580e41 LB	272	}
	273
	274	/*
	275	* Interfaces for PASID table entry manipulation:
	276	*/
	277	static inline void pasid_clear_entry(struct pasid_entry *pe)
	278	{
0bbeb01a LB	279	WRITE_ONCE(pe->val[0], 0);
	280	WRITE_ONCE(pe->val[1], 0);
	281	WRITE_ONCE(pe->val[2], 0);
	282	WRITE_ONCE(pe->val[3], 0);
	283	WRITE_ONCE(pe->val[4], 0);
	284	WRITE_ONCE(pe->val[5], 0);
	285	WRITE_ONCE(pe->val[6], 0);
	286	WRITE_ONCE(pe->val[7], 0);
cc580e41 LB	287	}
cc580e41 LB	288
1c4f88b7	289	static void intel_pasid_clear_entry(struct device *dev, int pasid)
cc580e41 LB	290	{
	291	struct pasid_entry *pe;
	292
	293	pe = intel_pasid_get_entry(dev, pasid);
	294	if (WARN_ON(!pe))
	295	return;
	296
	297	pasid_clear_entry(pe);
	298	}
6f7db75e LB	299
	300	static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)
	301	{
	302	u64 old;
	303
	304	old = READ_ONCE(*ptr);
	305	WRITE_ONCE(*ptr, (old & ~mask) \| bits);
	306	}
	307
	308	/*
	309	* Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode
	310	* PASID entry.
	311	*/
	312	static inline void
	313	pasid_set_domain_id(struct pasid_entry *pe, u64 value)
	314	{
	315	pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
	316	}
	317
	318	/*
	319	* Get domain ID value of a scalable mode PASID entry.
	320	*/
	321	static inline u16
	322	pasid_get_domain_id(struct pasid_entry *pe)
	323	{
	324	return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
	325	}
	326
	327	/*
	328	* Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)
	329	* of a scalable mode PASID entry.
	330	*/
	331	static inline void
	332	pasid_set_slptr(struct pasid_entry *pe, u64 value)
	333	{
	334	pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
	335	}
	336
	337	/*
	338	* Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID
	339	* entry.
	340	*/
	341	static inline void
	342	pasid_set_address_width(struct pasid_entry *pe, u64 value)
	343	{
	344	pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
	345	}
	346
	347	/*
	348	* Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)
	349	* of a scalable mode PASID entry.
	350	*/
	351	static inline void
	352	pasid_set_translation_type(struct pasid_entry *pe, u64 value)
	353	{
	354	pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
	355	}
	356
	357	/*
	358	* Enable fault processing by clearing the FPD(Fault Processing
	359	* Disable) field (Bit 1) of a scalable mode PASID entry.
	360	*/
	361	static inline void pasid_set_fault_enable(struct pasid_entry *pe)
	362	{
363	pasid_set_bits(&pe->val[0], 1 << 1, 0);
364	}
365
366	/*
367	* Setup the SRE(Supervisor Request Enable) field (Bit 128) of a
368	* scalable mode PASID entry.
369	*/
370	static inline void pasid_set_sre(struct pasid_entry *pe)
371	{
372	pasid_set_bits(&pe->val[2], 1 << 0, 1);
373	}
374
375	/*
376	* Setup the P(Present) field (Bit 0) of a scalable mode PASID
377	* entry.
378	*/
379	static inline void pasid_set_present(struct pasid_entry *pe)
380	{
381	pasid_set_bits(&pe->val[0], 1 << 0, 1);
382	}
383
384	/*
385	* Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID
386	* entry.
387	*/
388	static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
389	{
390	pasid_set_bits(&pe->val[1], 1 << 23, value);
391	}
392
437f35e1 LB	393	/*
	394	* Setup the First Level Page table Pointer field (Bit 140~191)
	395	* of a scalable mode PASID entry.
	396	*/
	397	static inline void
	398	pasid_set_flptr(struct pasid_entry *pe, u64 value)
	399	{
	400	pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
	401	}
	402
	403	/*
	404	* Setup the First Level Paging Mode field (Bit 130~131) of a
	405	* scalable mode PASID entry.
	406	*/
	407	static inline void
	408	pasid_set_flpm(struct pasid_entry *pe, u64 value)
	409	{
	410	pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
	411	}
	412
6f7db75e LB	413	static void
	414	pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
	415	u16 did, int pasid)
	416	{
	417	struct qi_desc desc;
	418
	419	desc.qw0 = QI_PC_DID(did) \| QI_PC_PASID_SEL \| QI_PC_PASID(pasid);
	420	desc.qw1 = 0;
	421	desc.qw2 = 0;
	422	desc.qw3 = 0;
	423
	424	qi_submit_sync(&desc, iommu);
	425	}
	426
	427	static void
	428	iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid)
	429	{
	430	struct qi_desc desc;
	431
	432	desc.qw0 = QI_EIOTLB_PASID(pasid) \| QI_EIOTLB_DID(did) \|
	433	QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) \| QI_EIOTLB_TYPE;
	434	desc.qw1 = 0;
	435	desc.qw2 = 0;
	436	desc.qw3 = 0;
	437
	438	qi_submit_sync(&desc, iommu);
	439	}
	440
	441	static void
	442	devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
	443	struct device *dev, int pasid)
	444	{
	445	struct device_domain_info *info;
	446	u16 sid, qdep, pfsid;
	447
	448	info = dev->archdata.iommu;
	449	if (!info \|\| !info->ats_enabled)
	450	return;
	451
	452	sid = info->bus << 8 \| info->devfn;
	453	qdep = info->ats_qdep;
	454	pfsid = info->pfsid;
	455
	456	qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
	457	}
	458
	459	void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
	460	struct device *dev, int pasid)
	461	{
	462	struct pasid_entry *pte;
	463	u16 did;
	464
	465	pte = intel_pasid_get_entry(dev, pasid);
	466	if (WARN_ON(!pte))
	467	return;
	468
6f7db75e	469	did = pasid_get_domain_id(pte);
48739afa	470	intel_pasid_clear_entry(dev, pasid);
6f7db75e LB	471
	472	if (!ecap_coherent(iommu->ecap))
	473	clflush_cache_range(pte, sizeof(*pte));
	474
	475	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
	476	iotlb_invalidation_with_pasid(iommu, did, pasid);
	477
	478	/* Device IOTLB doesn't need to be flushed in caching mode. */
	479	if (!cap_caching_mode(iommu->cap))
	480	devtlb_invalidation_with_pasid(iommu, dev, pasid);
	481	}
	482
437f35e1 LB	483	/*
	484	* Set up the scalable mode pasid table entry for first only
	485	* translation type.
	486	*/
	487	int intel_pasid_setup_first_level(struct intel_iommu *iommu,
	488	struct device dev, pgd_t pgd,
	489	int pasid, u16 did, int flags)
	490	{
	491	struct pasid_entry *pte;
	492
	493	if (!ecap_flts(iommu->ecap)) {
	494	pr_err("No first level translation support on %s\n",
	495	iommu->name);
	496	return -EINVAL;
	497	}
	498
	499	pte = intel_pasid_get_entry(dev, pasid);
	500	if (WARN_ON(!pte))
	501	return -EINVAL;
	502
	503	pasid_clear_entry(pte);
	504
	505	/* Setup the first level page table pointer: */
	506	pasid_set_flptr(pte, (u64)__pa(pgd));
	507	if (flags & PASID_FLAG_SUPERVISOR_MODE) {
	508	if (!ecap_srs(iommu->ecap)) {
	509	pr_err("No supervisor request support on %s\n",
	510	iommu->name);
	511	return -EINVAL;
	512	}
	513	pasid_set_sre(pte);
	514	}
	515
	516	#ifdef CONFIG_X86
	517	if (cpu_feature_enabled(X86_FEATURE_LA57))
	518	pasid_set_flpm(pte, 1);
	519	#endif /* CONFIG_X86 */
	520
	521	pasid_set_domain_id(pte, did);
	522	pasid_set_address_width(pte, iommu->agaw);
	523	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
	524
	525	/* Setup Present and PASID Granular Transfer Type: */
	526	pasid_set_translation_type(pte, 1);
	527	pasid_set_present(pte);
	528
	529	if (!ecap_coherent(iommu->ecap))
	530	clflush_cache_range(pte, sizeof(*pte));
	531
	532	if (cap_caching_mode(iommu->cap)) {
	533	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
	534	iotlb_invalidation_with_pasid(iommu, did, pasid);
	535	} else {
	536	iommu_flush_write_buffer(iommu);
	537	}
	538
	539	return 0;
	540	}
	541
6f7db75e LB	542	/*
	543	* Set up the scalable mode pasid entry for second only translation type.
	544	*/
	545	int intel_pasid_setup_second_level(struct intel_iommu *iommu,
	546	struct dmar_domain *domain,
	547	struct device *dev, int pasid)
	548	{
	549	struct pasid_entry *pte;
	550	struct dma_pte *pgd;
	551	u64 pgd_val;
	552	int agaw;
	553	u16 did;
	554
	555	/*
	556	* If hardware advertises no support for second level
	557	* translation, return directly.
	558	*/
	559	if (!ecap_slts(iommu->ecap)) {
	560	pr_err("No second level translation support on %s\n",
	561	iommu->name);
	562	return -EINVAL;
	563	}
	564
	565	/*
	566	* Skip top levels of page tables for iommu which has less agaw
	567	* than default. Unnecessary for PT mode.
	568	*/
	569	pgd = domain->pgd;
	570	for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
	571	pgd = phys_to_virt(dma_pte_addr(pgd));
	572	if (!dma_pte_present(pgd)) {
	573	dev_err(dev, "Invalid domain page table\n");
	574	return -EINVAL;
	575	}
	576	}
	577
	578	pgd_val = virt_to_phys(pgd);
	579	did = domain->iommu_did[iommu->seq_id];
	580
	581	pte = intel_pasid_get_entry(dev, pasid);
	582	if (!pte) {
	583	dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
	584	return -ENODEV;
	585	}
	586
	587	pasid_clear_entry(pte);
	588	pasid_set_domain_id(pte, did);
	589	pasid_set_slptr(pte, pgd_val);
	590	pasid_set_address_width(pte, agaw);
	591	pasid_set_translation_type(pte, 2);
	592	pasid_set_fault_enable(pte);
	593	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
	594
	595	/*
	596	* Since it is a second level only translation setup, we should
	597	* set SRE bit as well (addresses are expected to be GPAs).
	598	*/
	599	pasid_set_sre(pte);
	600	pasid_set_present(pte);
	601
	602	if (!ecap_coherent(iommu->ecap))
	603	clflush_cache_range(pte, sizeof(*pte));
	604
	605	if (cap_caching_mode(iommu->cap)) {
606	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
607	iotlb_invalidation_with_pasid(iommu, did, pasid);
608	} else {
609	iommu_flush_write_buffer(iommu);
610	}
611
612	return 0;
613	}
614
615	/*
616	* Set up the scalable mode pasid entry for passthrough translation type.
617	*/
618	int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
619	struct dmar_domain *domain,
620	struct device *dev, int pasid)
621	{
622	u16 did = FLPT_DEFAULT_DID;
623	struct pasid_entry *pte;
624
625	pte = intel_pasid_get_entry(dev, pasid);
626	if (!pte) {
627	dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
628	return -ENODEV;
629	}
630
631	pasid_clear_entry(pte);
632	pasid_set_domain_id(pte, did);
633	pasid_set_address_width(pte, iommu->agaw);
634	pasid_set_translation_type(pte, 4);
635	pasid_set_fault_enable(pte);
636	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
637
638	/*
639	* We should set SRE bit as well since the addresses are expected
640	* to be GPAs.
641	*/
642	pasid_set_sre(pte);
643	pasid_set_present(pte);
644
645	if (!ecap_coherent(iommu->ecap))
646	clflush_cache_range(pte, sizeof(*pte));
647
648	if (cap_caching_mode(iommu->cap)) {
649	pasid_cache_invalidation_with_pasid(iommu, did, pasid);
650	iotlb_invalidation_with_pasid(iommu, did, pasid);
651	} else {
652	iommu_flush_write_buffer(iommu);
653	}
654
655	return 0;
656	}