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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
740a01ee MS |
2 | /* |
3 | * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. | |
2a96536e | 4 | * http://www.samsung.com |
2a96536e KC |
5 | */ |
6 | ||
7 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
8 | #define DEBUG | |
9 | #endif | |
10 | ||
2a96536e | 11 | #include <linux/clk.h> |
8ed55c81 | 12 | #include <linux/dma-mapping.h> |
2a96536e | 13 | #include <linux/err.h> |
312900c6 | 14 | #include <linux/io.h> |
2a96536e | 15 | #include <linux/iommu.h> |
312900c6 | 16 | #include <linux/interrupt.h> |
514c6032 | 17 | #include <linux/kmemleak.h> |
2a96536e | 18 | #include <linux/list.h> |
8ed55c81 | 19 | #include <linux/of.h> |
8ed55c81 | 20 | #include <linux/of_platform.h> |
312900c6 MS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
2a96536e | 24 | |
fe046f1b PT |
25 | #include "iommu-pages.h" |
26 | ||
d09d78fc CK |
27 | typedef u32 sysmmu_iova_t; |
28 | typedef u32 sysmmu_pte_t; | |
b3d14960 | 29 | static struct iommu_domain exynos_identity_domain; |
d09d78fc | 30 | |
f171abab | 31 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
32 | #define SECT_ORDER 20 |
33 | #define LPAGE_ORDER 16 | |
34 | #define SPAGE_ORDER 12 | |
35 | ||
36 | #define SECT_SIZE (1 << SECT_ORDER) | |
37 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
38 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
39 | ||
40 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
41 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
42 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
43 | ||
66a7ed84 CK |
44 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
45 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
47 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
48 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
49 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
50 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
51 | ||
52 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
53 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
54 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
55 | ||
740a01ee MS |
56 | /* |
57 | * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces | |
58 | * v5.0 introduced support for 36bit physical address space by shifting | |
59 | * all page entry values by 4 bits. | |
60 | * All SYSMMU controllers in the system support the address spaces of the same | |
61 | * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper | |
62 | * value (0 or 4). | |
63 | */ | |
64 | static short PG_ENT_SHIFT = -1; | |
65 | #define SYSMMU_PG_ENT_SHIFT 0 | |
66 | #define SYSMMU_V5_PG_ENT_SHIFT 4 | |
67 | ||
1a0d8dac MS |
68 | static const sysmmu_pte_t *LV1_PROT; |
69 | static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { | |
70 | ((0 << 15) | (0 << 10)), /* no access */ | |
71 | ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ | |
72 | ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ | |
73 | ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ | |
74 | }; | |
75 | static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { | |
76 | (0 << 4), /* no access */ | |
77 | (1 << 4), /* IOMMU_READ only */ | |
78 | (2 << 4), /* IOMMU_WRITE only */ | |
79 | (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ | |
80 | }; | |
81 | ||
82 | static const sysmmu_pte_t *LV2_PROT; | |
83 | static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { | |
84 | ((0 << 9) | (0 << 4)), /* no access */ | |
85 | ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ | |
86 | ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ | |
87 | ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ | |
88 | }; | |
89 | static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { | |
90 | (0 << 2), /* no access */ | |
91 | (1 << 2), /* IOMMU_READ only */ | |
92 | (2 << 2), /* IOMMU_WRITE only */ | |
93 | (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ | |
94 | }; | |
95 | ||
96 | #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) | |
97 | ||
740a01ee MS |
98 | #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) |
99 | #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) | |
100 | #define section_offs(iova) (iova & (SECT_SIZE - 1)) | |
101 | #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) | |
102 | #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) | |
103 | #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) | |
104 | #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) | |
2a96536e KC |
105 | |
106 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 107 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 108 | |
d09d78fc CK |
109 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
110 | { | |
111 | return iova >> SECT_ORDER; | |
112 | } | |
113 | ||
114 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
115 | { | |
116 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
117 | } | |
118 | ||
5e3435eb | 119 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 120 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
121 | |
122 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
740a01ee | 123 | #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) |
2a96536e | 124 | |
1a0d8dac | 125 | #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) |
740a01ee | 126 | #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) |
1a0d8dac MS |
127 | #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) |
128 | #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) | |
2a96536e KC |
129 | |
130 | #define CTRL_ENABLE 0x5 | |
131 | #define CTRL_BLOCK 0x7 | |
132 | #define CTRL_DISABLE 0x0 | |
133 | ||
eeb5184b | 134 | #define CFG_LRU 0x1 |
1a0d8dac | 135 | #define CFG_EAP (1 << 2) |
eeb5184b | 136 | #define CFG_QOS(n) ((n & 0xF) << 7) |
eeb5184b CK |
137 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ |
138 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
139 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
140 | ||
7fee5d6f SP |
141 | #define CTRL_VM_ENABLE BIT(0) |
142 | #define CTRL_VM_FAULT_MODE_STALL BIT(3) | |
0892c498 SP |
143 | #define CAPA0_CAPA1_EXIST BIT(11) |
144 | #define CAPA1_VCR_ENABLED BIT(14) | |
145 | ||
740a01ee | 146 | /* common registers */ |
2a96536e KC |
147 | #define REG_MMU_CTRL 0x000 |
148 | #define REG_MMU_CFG 0x004 | |
149 | #define REG_MMU_STATUS 0x008 | |
740a01ee MS |
150 | #define REG_MMU_VERSION 0x034 |
151 | ||
152 | #define MMU_MAJ_VER(val) ((val) >> 7) | |
153 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
154 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
155 | ||
156 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
157 | ||
158 | /* v1.x - v3.x registers */ | |
2a96536e KC |
159 | #define REG_PAGE_FAULT_ADDR 0x024 |
160 | #define REG_AW_FAULT_ADDR 0x028 | |
161 | #define REG_AR_FAULT_ADDR 0x02C | |
162 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
163 | ||
740a01ee | 164 | /* v5.x registers */ |
740a01ee MS |
165 | #define REG_V5_FAULT_AR_VA 0x070 |
166 | #define REG_V5_FAULT_AW_VA 0x080 | |
2a96536e | 167 | |
0892c498 SP |
168 | /* v7.x registers */ |
169 | #define REG_V7_CAPA0 0x870 | |
170 | #define REG_V7_CAPA1 0x874 | |
7fee5d6f | 171 | #define REG_V7_CTRL_VM 0x8000 |
0892c498 | 172 | |
0f45b04d | 173 | #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) |
6b21a5db | 174 | |
5e3435eb | 175 | static struct device *dma_dev; |
734c3c73 | 176 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
177 | static sysmmu_pte_t *zero_lv2_table; |
178 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 179 | |
d09d78fc | 180 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
181 | { |
182 | return pgtable + lv1ent_offset(iova); | |
183 | } | |
184 | ||
d09d78fc | 185 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 186 | { |
d09d78fc | 187 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 188 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
189 | } |
190 | ||
c64074bf SP |
191 | struct sysmmu_fault { |
192 | sysmmu_iova_t addr; /* IOVA address that caused fault */ | |
193 | const char *name; /* human readable fault name */ | |
194 | unsigned int type; /* fault type for report_iommu_fault() */ | |
195 | }; | |
196 | ||
197 | struct sysmmu_v1_fault_info { | |
198 | unsigned short addr_reg; /* register to read IOVA fault address */ | |
d093fc7e MS |
199 | const char *name; /* human readable fault name */ |
200 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
201 | }; |
202 | ||
c64074bf SP |
203 | static const struct sysmmu_v1_fault_info sysmmu_v1_faults[] = { |
204 | { REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
205 | { REG_AR_FAULT_ADDR, "MULTI-HIT", IOMMU_FAULT_READ }, | |
206 | { REG_AW_FAULT_ADDR, "MULTI-HIT", IOMMU_FAULT_WRITE }, | |
207 | { REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
208 | { REG_AR_FAULT_ADDR, "SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
209 | { REG_AR_FAULT_ADDR, "ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
210 | { REG_AW_FAULT_ADDR, "SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
211 | { REG_AW_FAULT_ADDR, "ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
212 | }; |
213 | ||
c64074bf SP |
214 | /* SysMMU v5 has the same faults for AR (0..4 bits) and AW (16..20 bits) */ |
215 | static const char * const sysmmu_v5_fault_names[] = { | |
216 | "PTW", | |
217 | "PAGE", | |
218 | "MULTI-HIT", | |
219 | "ACCESS PROTECTION", | |
220 | "SECURITY PROTECTION" | |
2a96536e KC |
221 | }; |
222 | ||
2f599c3f SP |
223 | static const char * const sysmmu_v7_fault_names[] = { |
224 | "PTW", | |
225 | "PAGE", | |
226 | "ACCESS PROTECTION", | |
227 | "RESERVED" | |
740a01ee MS |
228 | }; |
229 | ||
2860af3c | 230 | /* |
0f45b04d | 231 | * This structure is attached to dev->iommu->priv of the master device |
2860af3c MS |
232 | * on device add, contains a list of SYSMMU controllers defined by device tree, |
233 | * which are bound to given master device. It is usually referenced by 'owner' | |
234 | * pointer. | |
235 | */ | |
6b21a5db | 236 | struct exynos_iommu_owner { |
1b092054 | 237 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
5fa61cbf | 238 | struct iommu_domain *domain; /* domain this device is attached */ |
9b265536 | 239 | struct mutex rpm_lock; /* for runtime pm of all sysmmus */ |
6b21a5db CK |
240 | }; |
241 | ||
2860af3c MS |
242 | /* |
243 | * This structure exynos specific generalization of struct iommu_domain. | |
244 | * It contains list of SYSMMU controllers from all master devices, which has | |
245 | * been attached to this domain and page tables of IO address space defined by | |
246 | * it. It is usually referenced by 'domain' pointer. | |
247 | */ | |
2a96536e | 248 | struct exynos_iommu_domain { |
2860af3c MS |
249 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
250 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
251 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
252 | spinlock_t lock; /* lock for modyfying list of clients */ | |
253 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 254 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
255 | }; |
256 | ||
c64074bf SP |
257 | struct sysmmu_drvdata; |
258 | ||
2125afbe SP |
259 | /* |
260 | * SysMMU version specific data. Contains offsets for the registers which can | |
261 | * be found in different SysMMU variants, but have different offset values. | |
c64074bf | 262 | * Also contains version specific callbacks to abstract the hardware. |
2125afbe SP |
263 | */ |
264 | struct sysmmu_variant { | |
265 | u32 pt_base; /* page table base address (physical) */ | |
266 | u32 flush_all; /* invalidate all TLB entries */ | |
267 | u32 flush_entry; /* invalidate specific TLB entry */ | |
268 | u32 flush_range; /* invalidate TLB entries in specified range */ | |
269 | u32 flush_start; /* start address of range invalidation */ | |
270 | u32 flush_end; /* end address of range invalidation */ | |
271 | u32 int_status; /* interrupt status information */ | |
272 | u32 int_clear; /* clear the interrupt */ | |
2f599c3f SP |
273 | u32 fault_va; /* IOVA address that caused fault */ |
274 | u32 fault_info; /* fault transaction info */ | |
c64074bf SP |
275 | |
276 | int (*get_fault_info)(struct sysmmu_drvdata *data, unsigned int itype, | |
277 | struct sysmmu_fault *fault); | |
2125afbe SP |
278 | }; |
279 | ||
2860af3c MS |
280 | /* |
281 | * This structure hold all data of a single SYSMMU controller, this includes | |
282 | * hw resources like registers and clocks, pointers and list nodes to connect | |
283 | * it to all other structures, internal state and parameters read from device | |
284 | * tree. It is usually referenced by 'data' pointer. | |
285 | */ | |
2a96536e | 286 | struct sysmmu_drvdata { |
2860af3c MS |
287 | struct device *sysmmu; /* SYSMMU controller device */ |
288 | struct device *master; /* master device (owner) */ | |
7a974b29 | 289 | struct device_link *link; /* runtime PM link to master */ |
2860af3c MS |
290 | void __iomem *sfrbase; /* our registers */ |
291 | struct clk *clk; /* SYSMMU's clock */ | |
740a01ee MS |
292 | struct clk *aclk; /* SYSMMU's aclk clock */ |
293 | struct clk *pclk; /* SYSMMU's pclk clock */ | |
2860af3c | 294 | struct clk *clk_master; /* master's device clock */ |
2860af3c | 295 | spinlock_t lock; /* lock for modyfying state */ |
47a574ff | 296 | bool active; /* current status */ |
2860af3c MS |
297 | struct exynos_iommu_domain *domain; /* domain we belong to */ |
298 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 299 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
300 | phys_addr_t pgtable; /* assigned page table structure */ |
301 | unsigned int version; /* our version */ | |
d2c302b6 JR |
302 | |
303 | struct iommu_device iommu; /* IOMMU core handle */ | |
2125afbe | 304 | const struct sysmmu_variant *variant; /* version specific data */ |
0892c498 SP |
305 | |
306 | /* v7 fields */ | |
307 | bool has_vcr; /* virtual machine control register */ | |
2125afbe SP |
308 | }; |
309 | ||
310 | #define SYSMMU_REG(data, reg) ((data)->sfrbase + (data)->variant->reg) | |
311 | ||
c64074bf SP |
312 | static int exynos_sysmmu_v1_get_fault_info(struct sysmmu_drvdata *data, |
313 | unsigned int itype, | |
314 | struct sysmmu_fault *fault) | |
315 | { | |
316 | const struct sysmmu_v1_fault_info *finfo; | |
317 | ||
318 | if (itype >= ARRAY_SIZE(sysmmu_v1_faults)) | |
319 | return -ENXIO; | |
320 | ||
321 | finfo = &sysmmu_v1_faults[itype]; | |
322 | fault->addr = readl(data->sfrbase + finfo->addr_reg); | |
323 | fault->name = finfo->name; | |
324 | fault->type = finfo->type; | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static int exynos_sysmmu_v5_get_fault_info(struct sysmmu_drvdata *data, | |
330 | unsigned int itype, | |
331 | struct sysmmu_fault *fault) | |
332 | { | |
333 | unsigned int addr_reg; | |
334 | ||
335 | if (itype < ARRAY_SIZE(sysmmu_v5_fault_names)) { | |
336 | fault->type = IOMMU_FAULT_READ; | |
337 | addr_reg = REG_V5_FAULT_AR_VA; | |
338 | } else if (itype >= 16 && itype <= 20) { | |
339 | fault->type = IOMMU_FAULT_WRITE; | |
340 | addr_reg = REG_V5_FAULT_AW_VA; | |
341 | itype -= 16; | |
342 | } else { | |
343 | return -ENXIO; | |
344 | } | |
345 | ||
346 | fault->name = sysmmu_v5_fault_names[itype]; | |
347 | fault->addr = readl(data->sfrbase + addr_reg); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
2f599c3f SP |
352 | static int exynos_sysmmu_v7_get_fault_info(struct sysmmu_drvdata *data, |
353 | unsigned int itype, | |
354 | struct sysmmu_fault *fault) | |
355 | { | |
356 | u32 info = readl(SYSMMU_REG(data, fault_info)); | |
357 | ||
358 | fault->addr = readl(SYSMMU_REG(data, fault_va)); | |
359 | fault->name = sysmmu_v7_fault_names[itype % 4]; | |
360 | fault->type = (info & BIT(20)) ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
2125afbe SP |
365 | /* SysMMU v1..v3 */ |
366 | static const struct sysmmu_variant sysmmu_v1_variant = { | |
367 | .flush_all = 0x0c, | |
368 | .flush_entry = 0x10, | |
369 | .pt_base = 0x14, | |
370 | .int_status = 0x18, | |
371 | .int_clear = 0x1c, | |
c64074bf SP |
372 | |
373 | .get_fault_info = exynos_sysmmu_v1_get_fault_info, | |
2125afbe SP |
374 | }; |
375 | ||
2f599c3f | 376 | /* SysMMU v5 */ |
2125afbe SP |
377 | static const struct sysmmu_variant sysmmu_v5_variant = { |
378 | .pt_base = 0x0c, | |
379 | .flush_all = 0x10, | |
380 | .flush_entry = 0x14, | |
381 | .flush_range = 0x18, | |
382 | .flush_start = 0x20, | |
383 | .flush_end = 0x24, | |
384 | .int_status = 0x60, | |
385 | .int_clear = 0x64, | |
c64074bf SP |
386 | |
387 | .get_fault_info = exynos_sysmmu_v5_get_fault_info, | |
2a96536e KC |
388 | }; |
389 | ||
2f599c3f SP |
390 | /* SysMMU v7: non-VM capable register layout */ |
391 | static const struct sysmmu_variant sysmmu_v7_variant = { | |
392 | .pt_base = 0x0c, | |
393 | .flush_all = 0x10, | |
394 | .flush_entry = 0x14, | |
395 | .flush_range = 0x18, | |
396 | .flush_start = 0x20, | |
397 | .flush_end = 0x24, | |
398 | .int_status = 0x60, | |
399 | .int_clear = 0x64, | |
400 | .fault_va = 0x70, | |
401 | .fault_info = 0x78, | |
402 | ||
403 | .get_fault_info = exynos_sysmmu_v7_get_fault_info, | |
404 | }; | |
405 | ||
406 | /* SysMMU v7: VM capable register layout */ | |
0892c498 SP |
407 | static const struct sysmmu_variant sysmmu_v7_vm_variant = { |
408 | .pt_base = 0x800c, | |
409 | .flush_all = 0x8010, | |
410 | .flush_entry = 0x8014, | |
411 | .flush_range = 0x8018, | |
412 | .flush_start = 0x8020, | |
413 | .flush_end = 0x8024, | |
414 | .int_status = 0x60, | |
415 | .int_clear = 0x64, | |
2f599c3f SP |
416 | .fault_va = 0x1000, |
417 | .fault_info = 0x1004, | |
c64074bf | 418 | |
2f599c3f | 419 | .get_fault_info = exynos_sysmmu_v7_get_fault_info, |
2a96536e KC |
420 | }; |
421 | ||
e1fd1eaa JR |
422 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
423 | { | |
424 | return container_of(dom, struct exynos_iommu_domain, domain); | |
425 | } | |
426 | ||
02cdc365 | 427 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 428 | { |
84bd0428 | 429 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
430 | } |
431 | ||
02cdc365 | 432 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
433 | { |
434 | int i = 120; | |
435 | ||
84bd0428 MS |
436 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
437 | while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
438 | --i; |
439 | ||
84bd0428 | 440 | if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
02cdc365 | 441 | sysmmu_unblock(data); |
2a96536e KC |
442 | return false; |
443 | } | |
444 | ||
445 | return true; | |
446 | } | |
447 | ||
02cdc365 | 448 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 449 | { |
2125afbe | 450 | writel(0x1, SYSMMU_REG(data, flush_all)); |
2a96536e KC |
451 | } |
452 | ||
02cdc365 | 453 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 454 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 455 | { |
3ad6b7f3 | 456 | unsigned int i; |
365409db | 457 | |
2125afbe | 458 | if (MMU_MAJ_VER(data->version) < 5 || num_inv == 1) { |
d5bf739d | 459 | for (i = 0; i < num_inv; i++) { |
84bd0428 | 460 | writel((iova & SPAGE_MASK) | 1, |
2125afbe | 461 | SYSMMU_REG(data, flush_entry)); |
d5bf739d MS |
462 | iova += SPAGE_SIZE; |
463 | } | |
464 | } else { | |
2125afbe SP |
465 | writel(iova & SPAGE_MASK, SYSMMU_REG(data, flush_start)); |
466 | writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, | |
467 | SYSMMU_REG(data, flush_end)); | |
468 | writel(0x1, SYSMMU_REG(data, flush_range)); | |
3ad6b7f3 | 469 | } |
2a96536e KC |
470 | } |
471 | ||
02cdc365 | 472 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 473 | { |
2125afbe SP |
474 | u32 pt_base; |
475 | ||
740a01ee | 476 | if (MMU_MAJ_VER(data->version) < 5) |
2125afbe | 477 | pt_base = pgd; |
740a01ee | 478 | else |
2125afbe | 479 | pt_base = pgd >> SPAGE_ORDER; |
2a96536e | 480 | |
2125afbe | 481 | writel(pt_base, SYSMMU_REG(data, pt_base)); |
02cdc365 | 482 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
483 | } |
484 | ||
fecc49db MS |
485 | static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) |
486 | { | |
487 | BUG_ON(clk_prepare_enable(data->clk_master)); | |
488 | BUG_ON(clk_prepare_enable(data->clk)); | |
489 | BUG_ON(clk_prepare_enable(data->pclk)); | |
490 | BUG_ON(clk_prepare_enable(data->aclk)); | |
491 | } | |
492 | ||
493 | static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) | |
494 | { | |
495 | clk_disable_unprepare(data->aclk); | |
496 | clk_disable_unprepare(data->pclk); | |
497 | clk_disable_unprepare(data->clk); | |
498 | clk_disable_unprepare(data->clk_master); | |
499 | } | |
500 | ||
0892c498 SP |
501 | static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) |
502 | { | |
503 | u32 capa0 = readl(data->sfrbase + REG_V7_CAPA0); | |
504 | ||
505 | return capa0 & CAPA0_CAPA1_EXIST; | |
506 | } | |
507 | ||
508 | static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) | |
509 | { | |
510 | u32 capa1 = readl(data->sfrbase + REG_V7_CAPA1); | |
511 | ||
512 | data->has_vcr = capa1 & CAPA1_VCR_ENABLED; | |
513 | } | |
514 | ||
850d313e MS |
515 | static void __sysmmu_get_version(struct sysmmu_drvdata *data) |
516 | { | |
517 | u32 ver; | |
518 | ||
fecc49db | 519 | __sysmmu_enable_clocks(data); |
850d313e | 520 | |
84bd0428 | 521 | ver = readl(data->sfrbase + REG_MMU_VERSION); |
850d313e MS |
522 | |
523 | /* controllers on some SoCs don't report proper version */ | |
524 | if (ver == 0x80000001u) | |
525 | data->version = MAKE_MMU_VER(1, 0); | |
526 | else | |
527 | data->version = MMU_RAW_VER(ver); | |
528 | ||
529 | dev_dbg(data->sysmmu, "hardware version: %d.%d\n", | |
530 | MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); | |
531 | ||
0892c498 | 532 | if (MMU_MAJ_VER(data->version) < 5) { |
2125afbe | 533 | data->variant = &sysmmu_v1_variant; |
0892c498 | 534 | } else if (MMU_MAJ_VER(data->version) < 7) { |
2125afbe | 535 | data->variant = &sysmmu_v5_variant; |
0892c498 SP |
536 | } else { |
537 | if (__sysmmu_has_capa1(data)) | |
538 | __sysmmu_get_vcr(data); | |
539 | if (data->has_vcr) | |
540 | data->variant = &sysmmu_v7_vm_variant; | |
541 | else | |
2f599c3f | 542 | data->variant = &sysmmu_v7_variant; |
0892c498 | 543 | } |
2125afbe | 544 | |
fecc49db | 545 | __sysmmu_disable_clocks(data); |
850d313e MS |
546 | } |
547 | ||
d093fc7e | 548 | static void show_fault_information(struct sysmmu_drvdata *data, |
c64074bf | 549 | const struct sysmmu_fault *fault) |
2a96536e | 550 | { |
d09d78fc | 551 | sysmmu_pte_t *ent; |
2a96536e | 552 | |
c64074bf SP |
553 | dev_err(data->sysmmu, "%s: [%s] %s FAULT occurred at %#x\n", |
554 | dev_name(data->master), | |
555 | fault->type == IOMMU_FAULT_READ ? "READ" : "WRITE", | |
556 | fault->name, fault->addr); | |
ec5d241b | 557 | dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); |
c64074bf | 558 | ent = section_entry(phys_to_virt(data->pgtable), fault->addr); |
ec5d241b | 559 | dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); |
2a96536e | 560 | if (lv1ent_page(ent)) { |
c64074bf | 561 | ent = page_entry(ent, fault->addr); |
ec5d241b | 562 | dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 563 | } |
2a96536e KC |
564 | } |
565 | ||
566 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
567 | { | |
2a96536e | 568 | struct sysmmu_drvdata *data = dev_id; |
c64074bf SP |
569 | unsigned int itype; |
570 | struct sysmmu_fault fault; | |
7222e8db | 571 | int ret = -ENOSYS; |
2a96536e | 572 | |
47a574ff | 573 | WARN_ON(!data->active); |
2a96536e | 574 | |
9d4e7a24 | 575 | spin_lock(&data->lock); |
b398af21 | 576 | clk_enable(data->clk_master); |
9d4e7a24 | 577 | |
2125afbe | 578 | itype = __ffs(readl(SYSMMU_REG(data, int_status))); |
c64074bf SP |
579 | ret = data->variant->get_fault_info(data, itype, &fault); |
580 | if (ret) { | |
581 | dev_err(data->sysmmu, "Unhandled interrupt bit %u\n", itype); | |
582 | goto out; | |
583 | } | |
584 | show_fault_information(data, &fault); | |
2a96536e | 585 | |
c64074bf SP |
586 | if (data->domain) { |
587 | ret = report_iommu_fault(&data->domain->domain, data->master, | |
588 | fault.addr, fault.type); | |
589 | } | |
590 | if (ret) | |
591 | panic("Unrecoverable System MMU Fault!"); | |
592 | ||
593 | out: | |
2125afbe | 594 | writel(1 << itype, SYSMMU_REG(data, int_clear)); |
1fab7fa7 | 595 | |
c64074bf | 596 | /* SysMMU is in blocked state when interrupt occurred */ |
02cdc365 | 597 | sysmmu_unblock(data); |
b398af21 | 598 | clk_disable(data->clk_master); |
9d4e7a24 | 599 | spin_unlock(&data->lock); |
2a96536e KC |
600 | |
601 | return IRQ_HANDLED; | |
602 | } | |
603 | ||
47a574ff | 604 | static void __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 605 | { |
47a574ff MS |
606 | unsigned long flags; |
607 | ||
b398af21 | 608 | clk_enable(data->clk_master); |
70605870 | 609 | |
47a574ff | 610 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 MS |
611 | writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
612 | writel(0, data->sfrbase + REG_MMU_CFG); | |
47a574ff | 613 | data->active = false; |
6b21a5db CK |
614 | spin_unlock_irqrestore(&data->lock, flags); |
615 | ||
47a574ff | 616 | __sysmmu_disable_clocks(data); |
6b21a5db | 617 | } |
2a96536e | 618 | |
6b21a5db CK |
619 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
620 | { | |
83addecd MS |
621 | unsigned int cfg; |
622 | ||
83addecd MS |
623 | if (data->version <= MAKE_MMU_VER(3, 1)) |
624 | cfg = CFG_LRU | CFG_QOS(15); | |
625 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
626 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
627 | else | |
628 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db | 629 | |
1a0d8dac MS |
630 | cfg |= CFG_EAP; /* enable access protection bits check */ |
631 | ||
84bd0428 | 632 | writel(cfg, data->sfrbase + REG_MMU_CFG); |
6b21a5db CK |
633 | } |
634 | ||
7fee5d6f SP |
635 | static void __sysmmu_enable_vid(struct sysmmu_drvdata *data) |
636 | { | |
637 | u32 ctrl; | |
638 | ||
639 | if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr) | |
640 | return; | |
641 | ||
642 | ctrl = readl(data->sfrbase + REG_V7_CTRL_VM); | |
643 | ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; | |
644 | writel(ctrl, data->sfrbase + REG_V7_CTRL_VM); | |
645 | } | |
646 | ||
47a574ff | 647 | static void __sysmmu_enable(struct sysmmu_drvdata *data) |
6b21a5db | 648 | { |
47a574ff MS |
649 | unsigned long flags; |
650 | ||
fecc49db | 651 | __sysmmu_enable_clocks(data); |
70605870 | 652 | |
47a574ff | 653 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 | 654 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 655 | __sysmmu_init_config(data); |
02cdc365 | 656 | __sysmmu_set_ptbase(data, data->pgtable); |
7fee5d6f | 657 | __sysmmu_enable_vid(data); |
84bd0428 | 658 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
47a574ff MS |
659 | data->active = true; |
660 | spin_unlock_irqrestore(&data->lock, flags); | |
7222e8db | 661 | |
fecc49db MS |
662 | /* |
663 | * SYSMMU driver keeps master's clock enabled only for the short | |
664 | * time, while accessing the registers. For performing address | |
665 | * translation during DMA transaction it relies on the client | |
666 | * driver to enable it. | |
667 | */ | |
b398af21 | 668 | clk_disable(data->clk_master); |
6b21a5db | 669 | } |
70605870 | 670 | |
469acebe | 671 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
672 | sysmmu_iova_t iova) |
673 | { | |
674 | unsigned long flags; | |
66a7ed84 | 675 | |
66a7ed84 | 676 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 677 | if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { |
01324ab2 | 678 | clk_enable(data->clk_master); |
7d2aa6b8 | 679 | if (sysmmu_block(data)) { |
cd37a296 MS |
680 | if (data->version >= MAKE_MMU_VER(5, 0)) |
681 | __sysmmu_tlb_invalidate(data); | |
682 | else | |
683 | __sysmmu_tlb_invalidate_entry(data, iova, 1); | |
7d2aa6b8 MS |
684 | sysmmu_unblock(data); |
685 | } | |
01324ab2 | 686 | clk_disable(data->clk_master); |
d631ea98 | 687 | } |
66a7ed84 | 688 | spin_unlock_irqrestore(&data->lock, flags); |
66a7ed84 CK |
689 | } |
690 | ||
469acebe MS |
691 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
692 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
693 | { |
694 | unsigned long flags; | |
2a96536e | 695 | |
6b21a5db | 696 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 697 | if (data->active) { |
3ad6b7f3 | 698 | unsigned int num_inv = 1; |
70605870 | 699 | |
b398af21 | 700 | clk_enable(data->clk_master); |
70605870 | 701 | |
3ad6b7f3 CK |
702 | /* |
703 | * L2TLB invalidation required | |
704 | * 4KB page: 1 invalidation | |
f171abab SK |
705 | * 64KB page: 16 invalidations |
706 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
707 | * because it is set-associative TLB |
708 | * with 8-way and 64 sets. | |
709 | * 1MB page can be cached in one of all sets. | |
710 | * 64KB page can be one of 16 consecutive sets. | |
711 | */ | |
512bd0c6 | 712 | if (MMU_MAJ_VER(data->version) == 2) |
bc0d9af2 | 713 | num_inv = min_t(unsigned int, size / SPAGE_SIZE, 64); |
3ad6b7f3 | 714 | |
02cdc365 MS |
715 | if (sysmmu_block(data)) { |
716 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
717 | sysmmu_unblock(data); | |
2a96536e | 718 | } |
b398af21 | 719 | clk_disable(data->clk_master); |
2a96536e | 720 | } |
9d4e7a24 | 721 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
722 | } |
723 | ||
0b9a3694 | 724 | static const struct iommu_ops exynos_iommu_ops; |
96f66557 | 725 | |
7991eb39 | 726 | static int exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 727 | { |
46c16d1e | 728 | int irq, ret; |
7222e8db | 729 | struct device *dev = &pdev->dev; |
2a96536e | 730 | struct sysmmu_drvdata *data; |
7222e8db | 731 | struct resource *res; |
2a96536e | 732 | |
46c16d1e CK |
733 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
734 | if (!data) | |
735 | return -ENOMEM; | |
2a96536e | 736 | |
7222e8db | 737 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
738 | data->sfrbase = devm_ioremap_resource(dev, res); |
739 | if (IS_ERR(data->sfrbase)) | |
740 | return PTR_ERR(data->sfrbase); | |
2a96536e | 741 | |
46c16d1e | 742 | irq = platform_get_irq(pdev, 0); |
086f9efa | 743 | if (irq <= 0) |
46c16d1e | 744 | return irq; |
2a96536e | 745 | |
46c16d1e | 746 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
747 | dev_name(dev), data); |
748 | if (ret) { | |
46c16d1e CK |
749 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
750 | return ret; | |
2a96536e KC |
751 | } |
752 | ||
5e799a7c CJ |
753 | data->clk = devm_clk_get_optional(dev, "sysmmu"); |
754 | if (IS_ERR(data->clk)) | |
0c2b063f | 755 | return PTR_ERR(data->clk); |
740a01ee | 756 | |
5e799a7c CJ |
757 | data->aclk = devm_clk_get_optional(dev, "aclk"); |
758 | if (IS_ERR(data->aclk)) | |
0c2b063f | 759 | return PTR_ERR(data->aclk); |
740a01ee | 760 | |
5e799a7c CJ |
761 | data->pclk = devm_clk_get_optional(dev, "pclk"); |
762 | if (IS_ERR(data->pclk)) | |
0c2b063f | 763 | return PTR_ERR(data->pclk); |
740a01ee MS |
764 | |
765 | if (!data->clk && (!data->aclk || !data->pclk)) { | |
766 | dev_err(dev, "Failed to get device clock(s)!\n"); | |
767 | return -ENOSYS; | |
2a96536e KC |
768 | } |
769 | ||
5e799a7c CJ |
770 | data->clk_master = devm_clk_get_optional(dev, "master"); |
771 | if (IS_ERR(data->clk_master)) | |
0c2b063f | 772 | return PTR_ERR(data->clk_master); |
70605870 | 773 | |
2a96536e | 774 | data->sysmmu = dev; |
9d4e7a24 | 775 | spin_lock_init(&data->lock); |
2a96536e | 776 | |
2125afbe SP |
777 | __sysmmu_get_version(data); |
778 | ||
d2c302b6 JR |
779 | ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, |
780 | dev_name(data->sysmmu)); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
7222e8db CK |
784 | platform_set_drvdata(pdev, data); |
785 | ||
740a01ee | 786 | if (PG_ENT_SHIFT < 0) { |
1a0d8dac | 787 | if (MMU_MAJ_VER(data->version) < 5) { |
740a01ee | 788 | PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; |
1a0d8dac MS |
789 | LV1_PROT = SYSMMU_LV1_PROT; |
790 | LV2_PROT = SYSMMU_LV2_PROT; | |
791 | } else { | |
740a01ee | 792 | PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; |
1a0d8dac MS |
793 | LV1_PROT = SYSMMU_V5_LV1_PROT; |
794 | LV2_PROT = SYSMMU_V5_LV2_PROT; | |
795 | } | |
740a01ee MS |
796 | } |
797 | ||
5f26ad58 SP |
798 | if (MMU_MAJ_VER(data->version) >= 5) { |
799 | ret = dma_set_mask(dev, DMA_BIT_MASK(36)); | |
800 | if (ret) { | |
801 | dev_err(dev, "Unable to set DMA mask: %d\n", ret); | |
802 | goto err_dma_set_mask; | |
803 | } | |
804 | } | |
805 | ||
928055a0 MS |
806 | /* |
807 | * use the first registered sysmmu device for performing | |
808 | * dma mapping operations on iommu page tables (cpu cache flush) | |
809 | */ | |
810 | if (!dma_dev) | |
811 | dma_dev = &pdev->dev; | |
812 | ||
f4723ec1 | 813 | pm_runtime_enable(dev); |
2a96536e | 814 | |
bbc4d205 MS |
815 | ret = iommu_device_register(&data->iommu, &exynos_iommu_ops, dev); |
816 | if (ret) | |
817 | goto err_dma_set_mask; | |
818 | ||
2a96536e | 819 | return 0; |
fce398d2 | 820 | |
5f26ad58 | 821 | err_dma_set_mask: |
fce398d2 SP |
822 | iommu_device_sysfs_remove(&data->iommu); |
823 | return ret; | |
2a96536e KC |
824 | } |
825 | ||
9b265536 | 826 | static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) |
622015e4 MS |
827 | { |
828 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 829 | struct device *master = data->master; |
622015e4 | 830 | |
47a574ff | 831 | if (master) { |
0f45b04d | 832 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); |
9b265536 MS |
833 | |
834 | mutex_lock(&owner->rpm_lock); | |
b3d14960 | 835 | if (&data->domain->domain != &exynos_identity_domain) { |
92798b45 MS |
836 | dev_dbg(data->sysmmu, "saving state\n"); |
837 | __sysmmu_disable(data); | |
838 | } | |
9b265536 | 839 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
840 | } |
841 | return 0; | |
842 | } | |
843 | ||
9b265536 | 844 | static int __maybe_unused exynos_sysmmu_resume(struct device *dev) |
622015e4 MS |
845 | { |
846 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 847 | struct device *master = data->master; |
622015e4 | 848 | |
47a574ff | 849 | if (master) { |
0f45b04d | 850 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); |
9b265536 MS |
851 | |
852 | mutex_lock(&owner->rpm_lock); | |
b3d14960 | 853 | if (&data->domain->domain != &exynos_identity_domain) { |
92798b45 MS |
854 | dev_dbg(data->sysmmu, "restoring state\n"); |
855 | __sysmmu_enable(data); | |
856 | } | |
9b265536 | 857 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
858 | } |
859 | return 0; | |
860 | } | |
622015e4 MS |
861 | |
862 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
9b265536 | 863 | SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) |
2f5f44f2 MS |
864 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
865 | pm_runtime_force_resume) | |
622015e4 MS |
866 | }; |
867 | ||
9d25e3cc | 868 | static const struct of_device_id sysmmu_of_match[] = { |
6b21a5db CK |
869 | { .compatible = "samsung,exynos-sysmmu", }, |
870 | { }, | |
871 | }; | |
872 | ||
873 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
874 | .probe = exynos_sysmmu_probe, | |
875 | .driver = { | |
2a96536e | 876 | .name = "exynos-sysmmu", |
6b21a5db | 877 | .of_match_table = sysmmu_of_match, |
622015e4 | 878 | .pm = &sysmmu_pm_ops, |
b54b874f | 879 | .suppress_bind_attrs = true, |
2a96536e KC |
880 | } |
881 | }; | |
882 | ||
9314006d | 883 | static inline void exynos_iommu_set_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 884 | { |
5e3435eb MS |
885 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
886 | DMA_TO_DEVICE); | |
6ae5343c | 887 | *ent = cpu_to_le32(val); |
5e3435eb MS |
888 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), |
889 | DMA_TO_DEVICE); | |
2a96536e KC |
890 | } |
891 | ||
3529375e | 892 | static struct iommu_domain *exynos_iommu_domain_alloc_paging(struct device *dev) |
2a96536e | 893 | { |
bfa00489 | 894 | struct exynos_iommu_domain *domain; |
5e3435eb | 895 | dma_addr_t handle; |
66a7ed84 | 896 | int i; |
2a96536e | 897 | |
740a01ee MS |
898 | /* Check if correct PTE offsets are initialized */ |
899 | BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); | |
e1fd1eaa | 900 | |
bfa00489 MS |
901 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
902 | if (!domain) | |
e1fd1eaa | 903 | return NULL; |
2a96536e | 904 | |
fe046f1b | 905 | domain->pgtable = iommu_alloc_pages(GFP_KERNEL, 2); |
bfa00489 | 906 | if (!domain->pgtable) |
4a376d4a | 907 | goto err_pgtable; |
2a96536e | 908 | |
fe046f1b | 909 | domain->lv2entcnt = iommu_alloc_pages(GFP_KERNEL, 1); |
bfa00489 | 910 | if (!domain->lv2entcnt) |
2a96536e KC |
911 | goto err_counter; |
912 | ||
f171abab | 913 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
e7527663 MS |
914 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
915 | domain->pgtable[i] = ZERO_LV2LINK; | |
66a7ed84 | 916 | |
5e3435eb MS |
917 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
918 | DMA_TO_DEVICE); | |
919 | /* For mapping page table entries we rely on dma == phys */ | |
920 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
0d6d3da4 MS |
921 | if (dma_mapping_error(dma_dev, handle)) |
922 | goto err_lv2ent; | |
2a96536e | 923 | |
bfa00489 MS |
924 | spin_lock_init(&domain->lock); |
925 | spin_lock_init(&domain->pgtablelock); | |
926 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 927 | |
bfa00489 MS |
928 | domain->domain.geometry.aperture_start = 0; |
929 | domain->domain.geometry.aperture_end = ~0UL; | |
930 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 931 | |
bfa00489 | 932 | return &domain->domain; |
2a96536e | 933 | |
0d6d3da4 | 934 | err_lv2ent: |
fe046f1b | 935 | iommu_free_pages(domain->lv2entcnt, 1); |
2a96536e | 936 | err_counter: |
fe046f1b | 937 | iommu_free_pages(domain->pgtable, 2); |
2a96536e | 938 | err_pgtable: |
bfa00489 | 939 | kfree(domain); |
e1fd1eaa | 940 | return NULL; |
2a96536e KC |
941 | } |
942 | ||
bfa00489 | 943 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 944 | { |
bfa00489 | 945 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 946 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
947 | unsigned long flags; |
948 | int i; | |
949 | ||
bfa00489 | 950 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 951 | |
bfa00489 | 952 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 953 | |
bfa00489 | 954 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
e1172300 | 955 | spin_lock(&data->lock); |
b0d4c861 | 956 | __sysmmu_disable(data); |
47a574ff MS |
957 | data->pgtable = 0; |
958 | data->domain = NULL; | |
469acebe | 959 | list_del_init(&data->domain_node); |
e1172300 | 960 | spin_unlock(&data->lock); |
2a96536e KC |
961 | } |
962 | ||
bfa00489 | 963 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 964 | |
5e3435eb MS |
965 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
966 | DMA_TO_DEVICE); | |
967 | ||
2a96536e | 968 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
969 | if (lv1ent_page(domain->pgtable + i)) { |
970 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
971 | ||
972 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
973 | DMA_TO_DEVICE); | |
734c3c73 | 974 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
975 | phys_to_virt(base)); |
976 | } | |
2a96536e | 977 | |
fe046f1b PT |
978 | iommu_free_pages(domain->pgtable, 2); |
979 | iommu_free_pages(domain->lv2entcnt, 1); | |
bfa00489 | 980 | kfree(domain); |
2a96536e KC |
981 | } |
982 | ||
b3d14960 JG |
983 | static int exynos_iommu_identity_attach(struct iommu_domain *identity_domain, |
984 | struct device *dev) | |
5fa61cbf | 985 | { |
0f45b04d | 986 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
b3d14960 JG |
987 | struct exynos_iommu_domain *domain; |
988 | phys_addr_t pagetable; | |
5fa61cbf MS |
989 | struct sysmmu_drvdata *data, *next; |
990 | unsigned long flags; | |
5fa61cbf | 991 | |
b3d14960 JG |
992 | if (owner->domain == identity_domain) |
993 | return 0; | |
994 | ||
995 | domain = to_exynos_domain(owner->domain); | |
996 | pagetable = virt_to_phys(domain->pgtable); | |
5fa61cbf | 997 | |
9b265536 MS |
998 | mutex_lock(&owner->rpm_lock); |
999 | ||
1000 | list_for_each_entry(data, &owner->controllers, owner_node) { | |
1001 | pm_runtime_get_noresume(data->sysmmu); | |
1002 | if (pm_runtime_active(data->sysmmu)) | |
1003 | __sysmmu_disable(data); | |
e1172300 MS |
1004 | pm_runtime_put(data->sysmmu); |
1005 | } | |
1006 | ||
5fa61cbf MS |
1007 | spin_lock_irqsave(&domain->lock, flags); |
1008 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { | |
e1172300 | 1009 | spin_lock(&data->lock); |
47a574ff MS |
1010 | data->pgtable = 0; |
1011 | data->domain = NULL; | |
b0d4c861 | 1012 | list_del_init(&data->domain_node); |
e1172300 | 1013 | spin_unlock(&data->lock); |
5fa61cbf | 1014 | } |
b3d14960 | 1015 | owner->domain = identity_domain; |
5fa61cbf MS |
1016 | spin_unlock_irqrestore(&domain->lock, flags); |
1017 | ||
9b265536 | 1018 | mutex_unlock(&owner->rpm_lock); |
5fa61cbf | 1019 | |
b3d14960 JG |
1020 | dev_dbg(dev, "%s: Restored IOMMU to IDENTITY from pgtable %pa\n", |
1021 | __func__, &pagetable); | |
1022 | return 0; | |
5fa61cbf MS |
1023 | } |
1024 | ||
b3d14960 JG |
1025 | static struct iommu_domain_ops exynos_identity_ops = { |
1026 | .attach_dev = exynos_iommu_identity_attach, | |
1027 | }; | |
1028 | ||
1029 | static struct iommu_domain exynos_identity_domain = { | |
1030 | .type = IOMMU_DOMAIN_IDENTITY, | |
1031 | .ops = &exynos_identity_ops, | |
1032 | }; | |
1033 | ||
bfa00489 | 1034 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
1035 | struct device *dev) |
1036 | { | |
bfa00489 | 1037 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
0f45b04d | 1038 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
469acebe | 1039 | struct sysmmu_drvdata *data; |
bfa00489 | 1040 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 1041 | unsigned long flags; |
b3d14960 | 1042 | int err; |
2a96536e | 1043 | |
b3d14960 JG |
1044 | err = exynos_iommu_identity_attach(&exynos_identity_domain, dev); |
1045 | if (err) | |
1046 | return err; | |
5fa61cbf | 1047 | |
9b265536 MS |
1048 | mutex_lock(&owner->rpm_lock); |
1049 | ||
e1172300 | 1050 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 1051 | list_for_each_entry(data, &owner->controllers, owner_node) { |
e1172300 | 1052 | spin_lock(&data->lock); |
47a574ff MS |
1053 | data->pgtable = pagetable; |
1054 | data->domain = domain; | |
e1172300 MS |
1055 | list_add_tail(&data->domain_node, &domain->clients); |
1056 | spin_unlock(&data->lock); | |
1057 | } | |
1058 | owner->domain = iommu_domain; | |
1059 | spin_unlock_irqrestore(&domain->lock, flags); | |
1060 | ||
9b265536 MS |
1061 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1062 | pm_runtime_get_noresume(data->sysmmu); | |
1063 | if (pm_runtime_active(data->sysmmu)) | |
1064 | __sysmmu_enable(data); | |
1065 | pm_runtime_put(data->sysmmu); | |
1066 | } | |
1067 | ||
1068 | mutex_unlock(&owner->rpm_lock); | |
1069 | ||
b0d4c861 MS |
1070 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, |
1071 | &pagetable); | |
7222e8db | 1072 | |
b0d4c861 | 1073 | return 0; |
2a96536e KC |
1074 | } |
1075 | ||
bfa00489 | 1076 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 1077 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 1078 | { |
61128f08 | 1079 | if (lv1ent_section(sent)) { |
d09d78fc | 1080 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
1081 | return ERR_PTR(-EADDRINUSE); |
1082 | } | |
1083 | ||
2a96536e | 1084 | if (lv1ent_fault(sent)) { |
0d6d3da4 | 1085 | dma_addr_t handle; |
d09d78fc | 1086 | sysmmu_pte_t *pent; |
66a7ed84 | 1087 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 1088 | |
734c3c73 | 1089 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
dbf6c6ef | 1090 | BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 1091 | if (!pent) |
61128f08 | 1092 | return ERR_PTR(-ENOMEM); |
2a96536e | 1093 | |
9314006d | 1094 | exynos_iommu_set_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 1095 | kmemleak_ignore(pent); |
2a96536e | 1096 | *pgcounter = NUM_LV2ENTRIES; |
0d6d3da4 MS |
1097 | handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, |
1098 | DMA_TO_DEVICE); | |
1099 | if (dma_mapping_error(dma_dev, handle)) { | |
1100 | kmem_cache_free(lv2table_kmem_cache, pent); | |
1101 | return ERR_PTR(-EADDRINUSE); | |
1102 | } | |
66a7ed84 CK |
1103 | |
1104 | /* | |
f171abab SK |
1105 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
1106 | * FLPD cache may cache the address of zero_l2_table. This | |
1107 | * function replaces the zero_l2_table with new L2 page table | |
1108 | * to write valid mappings. | |
66a7ed84 | 1109 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
1110 | * cache may still cache zero_l2_table for the valid area |
1111 | * instead of new L2 page table that has the mapping | |
1112 | * information of the valid area. | |
66a7ed84 CK |
1113 | * Thus any replacement of zero_l2_table with other valid L2 |
1114 | * page table must involve FLPD cache invalidation for System | |
1115 | * MMU v3.3. | |
1116 | * FLPD cache invalidation is performed with TLB invalidation | |
1117 | * by VPN without blocking. It is safe to invalidate TLB without | |
1118 | * blocking because the target address of TLB invalidation is | |
1119 | * not currently mapped. | |
1120 | */ | |
1121 | if (need_flush_flpd_cache) { | |
469acebe | 1122 | struct sysmmu_drvdata *data; |
365409db | 1123 | |
bfa00489 MS |
1124 | spin_lock(&domain->lock); |
1125 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 1126 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 1127 | spin_unlock(&domain->lock); |
66a7ed84 | 1128 | } |
2a96536e KC |
1129 | } |
1130 | ||
1131 | return page_entry(sent, iova); | |
1132 | } | |
1133 | ||
bfa00489 | 1134 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 1135 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
1a0d8dac | 1136 | phys_addr_t paddr, int prot, short *pgcnt) |
2a96536e | 1137 | { |
61128f08 | 1138 | if (lv1ent_section(sent)) { |
d09d78fc | 1139 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 1140 | iova); |
2a96536e | 1141 | return -EADDRINUSE; |
61128f08 | 1142 | } |
2a96536e KC |
1143 | |
1144 | if (lv1ent_page(sent)) { | |
61128f08 | 1145 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 1146 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 1147 | iova); |
2a96536e | 1148 | return -EADDRINUSE; |
61128f08 | 1149 | } |
2a96536e | 1150 | |
734c3c73 | 1151 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
1152 | *pgcnt = 0; |
1153 | } | |
1154 | ||
9314006d | 1155 | exynos_iommu_set_pte(sent, mk_lv1ent_sect(paddr, prot)); |
2a96536e | 1156 | |
bfa00489 | 1157 | spin_lock(&domain->lock); |
66a7ed84 | 1158 | if (lv1ent_page_zero(sent)) { |
469acebe | 1159 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1160 | /* |
1161 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
1162 | * entry by speculative prefetch of SLPD which has no mapping. | |
1163 | */ | |
bfa00489 | 1164 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1165 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 1166 | } |
bfa00489 | 1167 | spin_unlock(&domain->lock); |
66a7ed84 | 1168 | |
2a96536e KC |
1169 | return 0; |
1170 | } | |
1171 | ||
d09d78fc | 1172 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
1a0d8dac | 1173 | int prot, short *pgcnt) |
2a96536e KC |
1174 | { |
1175 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 1176 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
1177 | return -EADDRINUSE; |
1178 | ||
9314006d | 1179 | exynos_iommu_set_pte(pent, mk_lv2ent_spage(paddr, prot)); |
2a96536e KC |
1180 | *pgcnt -= 1; |
1181 | } else { /* size == LPAGE_SIZE */ | |
1182 | int i; | |
5e3435eb | 1183 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 1184 | |
5e3435eb MS |
1185 | dma_sync_single_for_cpu(dma_dev, pent_base, |
1186 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1187 | DMA_TO_DEVICE); | |
2a96536e | 1188 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 1189 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
1190 | if (i > 0) |
1191 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
1192 | return -EADDRINUSE; |
1193 | } | |
1194 | ||
1a0d8dac | 1195 | *pent = mk_lv2ent_lpage(paddr, prot); |
2a96536e | 1196 | } |
5e3435eb MS |
1197 | dma_sync_single_for_device(dma_dev, pent_base, |
1198 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1199 | DMA_TO_DEVICE); | |
2a96536e KC |
1200 | *pgcnt -= SPAGES_PER_LPAGE; |
1201 | } | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
66a7ed84 CK |
1206 | /* |
1207 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
1208 | * | |
f171abab | 1209 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 1210 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
1211 | * However, the logic has a bug that while caching faulty page table entries, |
1212 | * System MMU reports page fault if the cached fault entry is hit even though | |
1213 | * the fault entry is updated to a valid entry after the entry is cached. | |
1214 | * To prevent caching faulty page table entries which may be updated to valid | |
1215 | * entries later, the virtual memory manager should care about the workaround | |
1216 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
1217 | * |
1218 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 1219 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 1220 | * |
f171abab | 1221 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
1222 | * the following sizes for System MMU v3.1 and v3.2. |
1223 | * System MMU v3.1: 128KiB | |
1224 | * System MMU v3.2: 256KiB | |
1225 | * | |
1226 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
1227 | * more workarounds. |
1228 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
1229 | * than or equal to 128KiB. | |
66a7ed84 CK |
1230 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
1231 | */ | |
bfa00489 MS |
1232 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
1233 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
983efefa | 1234 | size_t count, int prot, gfp_t gfp, size_t *mapped) |
2a96536e | 1235 | { |
bfa00489 | 1236 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1237 | sysmmu_pte_t *entry; |
1238 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
1239 | unsigned long flags; |
1240 | int ret = -ENOMEM; | |
1241 | ||
bfa00489 | 1242 | BUG_ON(domain->pgtable == NULL); |
1a0d8dac | 1243 | prot &= SYSMMU_SUPPORTED_PROT_BITS; |
2a96536e | 1244 | |
bfa00489 | 1245 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1246 | |
bfa00489 | 1247 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1248 | |
1249 | if (size == SECT_SIZE) { | |
1a0d8dac | 1250 | ret = lv1set_section(domain, entry, iova, paddr, prot, |
bfa00489 | 1251 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e | 1252 | } else { |
d09d78fc | 1253 | sysmmu_pte_t *pent; |
2a96536e | 1254 | |
bfa00489 MS |
1255 | pent = alloc_lv2entry(domain, entry, iova, |
1256 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 1257 | |
61128f08 CK |
1258 | if (IS_ERR(pent)) |
1259 | ret = PTR_ERR(pent); | |
2a96536e | 1260 | else |
1a0d8dac | 1261 | ret = lv2set_page(pent, paddr, size, prot, |
bfa00489 | 1262 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1263 | } |
1264 | ||
61128f08 | 1265 | if (ret) |
0bf4e54d CK |
1266 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1267 | __func__, ret, size, iova); | |
983efefa RM |
1268 | else |
1269 | *mapped = size; | |
2a96536e | 1270 | |
bfa00489 | 1271 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1272 | |
1273 | return ret; | |
1274 | } | |
1275 | ||
bfa00489 MS |
1276 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1277 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1278 | { |
469acebe | 1279 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1280 | unsigned long flags; |
1281 | ||
bfa00489 | 1282 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1283 | |
bfa00489 | 1284 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1285 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1286 | |
bfa00489 | 1287 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1288 | } |
1289 | ||
bfa00489 | 1290 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
983efefa | 1291 | unsigned long l_iova, size_t size, size_t count, |
56f8af5e | 1292 | struct iommu_iotlb_gather *gather) |
2a96536e | 1293 | { |
bfa00489 | 1294 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1295 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1296 | sysmmu_pte_t *ent; | |
61128f08 | 1297 | size_t err_pgsize; |
d09d78fc | 1298 | unsigned long flags; |
2a96536e | 1299 | |
bfa00489 | 1300 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1301 | |
bfa00489 | 1302 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1303 | |
bfa00489 | 1304 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1305 | |
1306 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1307 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1308 | err_pgsize = SECT_SIZE; |
1309 | goto err; | |
1310 | } | |
2a96536e | 1311 | |
f171abab | 1312 | /* workaround for h/w bug in System MMU v3.3 */ |
9314006d | 1313 | exynos_iommu_set_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1314 | size = SECT_SIZE; |
1315 | goto done; | |
1316 | } | |
1317 | ||
1318 | if (unlikely(lv1ent_fault(ent))) { | |
1319 | if (size > SECT_SIZE) | |
1320 | size = SECT_SIZE; | |
1321 | goto done; | |
1322 | } | |
1323 | ||
1324 | /* lv1ent_page(sent) == true here */ | |
1325 | ||
1326 | ent = page_entry(ent, iova); | |
1327 | ||
1328 | if (unlikely(lv2ent_fault(ent))) { | |
1329 | size = SPAGE_SIZE; | |
1330 | goto done; | |
1331 | } | |
1332 | ||
1333 | if (lv2ent_small(ent)) { | |
9314006d | 1334 | exynos_iommu_set_pte(ent, 0); |
2a96536e | 1335 | size = SPAGE_SIZE; |
bfa00489 | 1336 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1337 | goto done; |
1338 | } | |
1339 | ||
1340 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1341 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1342 | err_pgsize = LPAGE_SIZE; |
1343 | goto err; | |
1344 | } | |
2a96536e | 1345 | |
5e3435eb MS |
1346 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1347 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1348 | DMA_TO_DEVICE); | |
2a96536e | 1349 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1350 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1351 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1352 | DMA_TO_DEVICE); | |
2a96536e | 1353 | size = LPAGE_SIZE; |
bfa00489 | 1354 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1355 | done: |
bfa00489 | 1356 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1357 | |
bfa00489 | 1358 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1359 | |
2a96536e | 1360 | return size; |
61128f08 | 1361 | err: |
bfa00489 | 1362 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1363 | |
0bf4e54d CK |
1364 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1365 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1366 | |
1367 | return 0; | |
2a96536e KC |
1368 | } |
1369 | ||
bfa00489 | 1370 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1371 | dma_addr_t iova) |
2a96536e | 1372 | { |
bfa00489 | 1373 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1374 | sysmmu_pte_t *entry; |
2a96536e KC |
1375 | unsigned long flags; |
1376 | phys_addr_t phys = 0; | |
1377 | ||
bfa00489 | 1378 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1379 | |
bfa00489 | 1380 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1381 | |
1382 | if (lv1ent_section(entry)) { | |
1383 | phys = section_phys(entry) + section_offs(iova); | |
1384 | } else if (lv1ent_page(entry)) { | |
1385 | entry = page_entry(entry, iova); | |
1386 | ||
1387 | if (lv2ent_large(entry)) | |
1388 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1389 | else if (lv2ent_small(entry)) | |
1390 | phys = spage_phys(entry) + spage_offs(iova); | |
1391 | } | |
1392 | ||
bfa00489 | 1393 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1394 | |
1395 | return phys; | |
1396 | } | |
1397 | ||
3c51c054 | 1398 | static struct iommu_device *exynos_iommu_probe_device(struct device *dev) |
bf4a1c92 | 1399 | { |
0f45b04d | 1400 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
7a974b29 | 1401 | struct sysmmu_drvdata *data; |
bf4a1c92 | 1402 | |
06801db0 | 1403 | if (!has_sysmmu(dev)) |
3c51c054 | 1404 | return ERR_PTR(-ENODEV); |
bf4a1c92 | 1405 | |
7a974b29 MS |
1406 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1407 | /* | |
1408 | * SYSMMU will be runtime activated via device link | |
1409 | * (dependency) to its master device, so there are no | |
1410 | * direct calls to pm_runtime_get/put in this driver. | |
1411 | */ | |
1412 | data->link = device_link_add(dev, data->sysmmu, | |
ea4f6400 | 1413 | DL_FLAG_STATELESS | |
7a974b29 MS |
1414 | DL_FLAG_PM_RUNTIME); |
1415 | } | |
bf4a1c92 | 1416 | |
66ae88e7 JR |
1417 | /* There is always at least one entry, see exynos_iommu_of_xlate() */ |
1418 | data = list_first_entry(&owner->controllers, | |
1419 | struct sysmmu_drvdata, owner_node); | |
66ae88e7 | 1420 | |
3c51c054 | 1421 | return &data->iommu; |
bf4a1c92 AM |
1422 | } |
1423 | ||
f91bf327 MS |
1424 | static void exynos_iommu_release_device(struct device *dev) |
1425 | { | |
1426 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); | |
1427 | struct sysmmu_drvdata *data; | |
1428 | ||
b3d14960 | 1429 | WARN_ON(exynos_iommu_identity_attach(&exynos_identity_domain, dev)); |
7a974b29 MS |
1430 | |
1431 | list_for_each_entry(data, &owner->controllers, owner_node) | |
1432 | device_link_del(data->link); | |
bf4a1c92 AM |
1433 | } |
1434 | ||
aa759fd3 | 1435 | static int exynos_iommu_of_xlate(struct device *dev, |
b42a905b | 1436 | const struct of_phandle_args *spec) |
aa759fd3 | 1437 | { |
aa759fd3 | 1438 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); |
0f45b04d | 1439 | struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); |
0bd5a0c7 | 1440 | struct sysmmu_drvdata *data, *entry; |
aa759fd3 MS |
1441 | |
1442 | if (!sysmmu) | |
1443 | return -ENODEV; | |
1444 | ||
1445 | data = platform_get_drvdata(sysmmu); | |
1a260449 YK |
1446 | if (!data) { |
1447 | put_device(&sysmmu->dev); | |
aa759fd3 | 1448 | return -ENODEV; |
1a260449 | 1449 | } |
aa759fd3 MS |
1450 | |
1451 | if (!owner) { | |
1452 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1a260449 YK |
1453 | if (!owner) { |
1454 | put_device(&sysmmu->dev); | |
aa759fd3 | 1455 | return -ENOMEM; |
1a260449 | 1456 | } |
aa759fd3 MS |
1457 | |
1458 | INIT_LIST_HEAD(&owner->controllers); | |
9b265536 | 1459 | mutex_init(&owner->rpm_lock); |
b3d14960 | 1460 | owner->domain = &exynos_identity_domain; |
0f45b04d | 1461 | dev_iommu_priv_set(dev, owner); |
aa759fd3 MS |
1462 | } |
1463 | ||
0bd5a0c7 MS |
1464 | list_for_each_entry(entry, &owner->controllers, owner_node) |
1465 | if (entry == data) | |
1466 | return 0; | |
1467 | ||
aa759fd3 | 1468 | list_add_tail(&data->owner_node, &owner->controllers); |
92798b45 | 1469 | data->master = dev; |
2f5f44f2 | 1470 | |
aa759fd3 MS |
1471 | return 0; |
1472 | } | |
1473 | ||
0b9a3694 | 1474 | static const struct iommu_ops exynos_iommu_ops = { |
b3d14960 | 1475 | .identity_domain = &exynos_identity_domain, |
3529375e | 1476 | .domain_alloc_paging = exynos_iommu_domain_alloc_paging, |
6d7cf02a | 1477 | .device_group = generic_device_group, |
3c51c054 JR |
1478 | .probe_device = exynos_iommu_probe_device, |
1479 | .release_device = exynos_iommu_release_device, | |
2a96536e | 1480 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1481 | .of_xlate = exynos_iommu_of_xlate, |
9a630a4b LB |
1482 | .default_domain_ops = &(const struct iommu_domain_ops) { |
1483 | .attach_dev = exynos_iommu_attach_device, | |
983efefa RM |
1484 | .map_pages = exynos_iommu_map, |
1485 | .unmap_pages = exynos_iommu_unmap, | |
9a630a4b LB |
1486 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1487 | .free = exynos_iommu_domain_free, | |
1488 | } | |
2a96536e KC |
1489 | }; |
1490 | ||
1491 | static int __init exynos_iommu_init(void) | |
1492 | { | |
dc98b848 | 1493 | struct device_node *np; |
2a96536e KC |
1494 | int ret; |
1495 | ||
dc98b848 RM |
1496 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1497 | if (!np) | |
1498 | return 0; | |
1499 | ||
1500 | of_node_put(np); | |
1501 | ||
734c3c73 CK |
1502 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1503 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1504 | if (!lv2table_kmem_cache) { | |
1505 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1506 | return -ENOMEM; | |
1507 | } | |
1508 | ||
66a7ed84 CK |
1509 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1510 | if (zero_lv2_table == NULL) { | |
1511 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1512 | __func__); | |
1513 | ret = -ENOMEM; | |
1514 | goto err_zero_lv2; | |
1515 | } | |
1516 | ||
bbc4d205 MS |
1517 | ret = platform_driver_register(&exynos_sysmmu_driver); |
1518 | if (ret) { | |
1519 | pr_err("%s: Failed to register driver\n", __func__); | |
1520 | goto err_reg_driver; | |
1521 | } | |
1522 | ||
734c3c73 | 1523 | return 0; |
734c3c73 | 1524 | err_reg_driver: |
53719876 | 1525 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
bbc4d205 | 1526 | err_zero_lv2: |
734c3c73 | 1527 | kmem_cache_destroy(lv2table_kmem_cache); |
2a96536e KC |
1528 | return ret; |
1529 | } | |
928055a0 | 1530 | core_initcall(exynos_iommu_init); |