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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
d09d78fc CK |
32 | typedef u32 sysmmu_iova_t; |
33 | typedef u32 sysmmu_pte_t; | |
34 | ||
f171abab | 35 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
36 | #define SECT_ORDER 20 |
37 | #define LPAGE_ORDER 16 | |
38 | #define SPAGE_ORDER 12 | |
39 | ||
40 | #define SECT_SIZE (1 << SECT_ORDER) | |
41 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
42 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
43 | ||
44 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
45 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
46 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
47 | ||
66a7ed84 CK |
48 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
49 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
50 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
51 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
52 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
53 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
54 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
55 | ||
56 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
57 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
58 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
59 | ||
d09d78fc CK |
60 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
61 | { | |
62 | return iova & (size - 1); | |
63 | } | |
64 | ||
2a96536e | 65 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 66 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 67 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 68 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 69 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 70 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
71 | |
72 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 73 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 74 | |
d09d78fc CK |
75 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
76 | { | |
77 | return iova >> SECT_ORDER; | |
78 | } | |
79 | ||
80 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
81 | { | |
82 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
83 | } | |
84 | ||
85 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
86 | |
87 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
88 | ||
89 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
90 | ||
91 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
92 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
93 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
94 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
95 | ||
96 | #define CTRL_ENABLE 0x5 | |
97 | #define CTRL_BLOCK 0x7 | |
98 | #define CTRL_DISABLE 0x0 | |
99 | ||
eeb5184b CK |
100 | #define CFG_LRU 0x1 |
101 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
102 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
103 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
104 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
105 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
106 | ||
2a96536e KC |
107 | #define REG_MMU_CTRL 0x000 |
108 | #define REG_MMU_CFG 0x004 | |
109 | #define REG_MMU_STATUS 0x008 | |
110 | #define REG_MMU_FLUSH 0x00C | |
111 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
112 | #define REG_PT_BASE_ADDR 0x014 | |
113 | #define REG_INT_STATUS 0x018 | |
114 | #define REG_INT_CLEAR 0x01C | |
115 | ||
116 | #define REG_PAGE_FAULT_ADDR 0x024 | |
117 | #define REG_AW_FAULT_ADDR 0x028 | |
118 | #define REG_AR_FAULT_ADDR 0x02C | |
119 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
120 | ||
121 | #define REG_MMU_VERSION 0x034 | |
122 | ||
eeb5184b CK |
123 | #define MMU_MAJ_VER(val) ((val) >> 7) |
124 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
125 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
126 | ||
127 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
128 | ||
2a96536e KC |
129 | #define REG_PB0_SADDR 0x04C |
130 | #define REG_PB0_EADDR 0x050 | |
131 | #define REG_PB1_SADDR 0x054 | |
132 | #define REG_PB1_EADDR 0x058 | |
133 | ||
6b21a5db CK |
134 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
135 | ||
734c3c73 | 136 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
137 | static sysmmu_pte_t *zero_lv2_table; |
138 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 139 | |
d09d78fc | 140 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
141 | { |
142 | return pgtable + lv1ent_offset(iova); | |
143 | } | |
144 | ||
d09d78fc | 145 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 146 | { |
d09d78fc | 147 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 148 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
149 | } |
150 | ||
151 | enum exynos_sysmmu_inttype { | |
152 | SYSMMU_PAGEFAULT, | |
153 | SYSMMU_AR_MULTIHIT, | |
154 | SYSMMU_AW_MULTIHIT, | |
155 | SYSMMU_BUSERROR, | |
156 | SYSMMU_AR_SECURITY, | |
157 | SYSMMU_AR_ACCESS, | |
158 | SYSMMU_AW_SECURITY, | |
159 | SYSMMU_AW_PROTECTION, /* 7 */ | |
160 | SYSMMU_FAULT_UNKNOWN, | |
161 | SYSMMU_FAULTS_NUM | |
162 | }; | |
163 | ||
2a96536e KC |
164 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
165 | REG_PAGE_FAULT_ADDR, | |
166 | REG_AR_FAULT_ADDR, | |
167 | REG_AW_FAULT_ADDR, | |
168 | REG_DEFAULT_SLAVE_ADDR, | |
169 | REG_AR_FAULT_ADDR, | |
170 | REG_AR_FAULT_ADDR, | |
171 | REG_AW_FAULT_ADDR, | |
172 | REG_AW_FAULT_ADDR | |
173 | }; | |
174 | ||
175 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
176 | "PAGE FAULT", | |
177 | "AR MULTI-HIT FAULT", | |
178 | "AW MULTI-HIT FAULT", | |
179 | "BUS ERROR", | |
180 | "AR SECURITY PROTECTION FAULT", | |
181 | "AR ACCESS PROTECTION FAULT", | |
182 | "AW SECURITY PROTECTION FAULT", | |
183 | "AW ACCESS PROTECTION FAULT", | |
184 | "UNKNOWN FAULT" | |
185 | }; | |
186 | ||
6b21a5db CK |
187 | /* attached to dev.archdata.iommu of the master device */ |
188 | struct exynos_iommu_owner { | |
189 | struct list_head client; /* entry of exynos_iommu_domain.clients */ | |
190 | struct device *dev; | |
191 | struct device *sysmmu; | |
6b21a5db CK |
192 | }; |
193 | ||
2a96536e KC |
194 | struct exynos_iommu_domain { |
195 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
d09d78fc | 196 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ |
2a96536e KC |
197 | short *lv2entcnt; /* free lv2 entry counter for each section */ |
198 | spinlock_t lock; /* lock for this structure */ | |
199 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 200 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
201 | }; |
202 | ||
203 | struct sysmmu_drvdata { | |
2a96536e | 204 | struct device *sysmmu; /* System MMU's device descriptor */ |
6b21a5db | 205 | struct device *master; /* Owner of system MMU */ |
7222e8db CK |
206 | void __iomem *sfrbase; |
207 | struct clk *clk; | |
70605870 | 208 | struct clk *clk_master; |
2a96536e | 209 | int activations; |
9d4e7a24 | 210 | spinlock_t lock; |
2a96536e | 211 | struct iommu_domain *domain; |
7222e8db | 212 | phys_addr_t pgtable; |
512bd0c6 | 213 | unsigned int version; |
2a96536e KC |
214 | }; |
215 | ||
e1fd1eaa JR |
216 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
217 | { | |
218 | return container_of(dom, struct exynos_iommu_domain, domain); | |
219 | } | |
220 | ||
2a96536e KC |
221 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
222 | { | |
223 | /* return true if the System MMU was not active previously | |
224 | and it needs to be initialized */ | |
225 | return ++data->activations == 1; | |
226 | } | |
227 | ||
228 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
229 | { | |
230 | /* return true if the System MMU is needed to be disabled */ | |
231 | BUG_ON(data->activations < 1); | |
232 | return --data->activations == 0; | |
233 | } | |
234 | ||
235 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
236 | { | |
237 | return data->activations > 0; | |
238 | } | |
239 | ||
240 | static void sysmmu_unblock(void __iomem *sfrbase) | |
241 | { | |
242 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
243 | } | |
244 | ||
245 | static bool sysmmu_block(void __iomem *sfrbase) | |
246 | { | |
247 | int i = 120; | |
248 | ||
249 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
250 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
251 | --i; | |
252 | ||
253 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
254 | sysmmu_unblock(sfrbase); | |
255 | return false; | |
256 | } | |
257 | ||
258 | return true; | |
259 | } | |
260 | ||
261 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
262 | { | |
263 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
264 | } | |
265 | ||
266 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 267 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 268 | { |
3ad6b7f3 | 269 | unsigned int i; |
365409db | 270 | |
3ad6b7f3 CK |
271 | for (i = 0; i < num_inv; i++) { |
272 | __raw_writel((iova & SPAGE_MASK) | 1, | |
273 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
274 | iova += SPAGE_SIZE; | |
275 | } | |
2a96536e KC |
276 | } |
277 | ||
278 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 279 | phys_addr_t pgd) |
2a96536e | 280 | { |
2a96536e KC |
281 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
282 | ||
283 | __sysmmu_tlb_invalidate(sfrbase); | |
284 | } | |
285 | ||
1fab7fa7 CK |
286 | static void show_fault_information(const char *name, |
287 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 288 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 289 | { |
d09d78fc | 290 | sysmmu_pte_t *ent; |
2a96536e KC |
291 | |
292 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
293 | itype = SYSMMU_FAULT_UNKNOWN; | |
294 | ||
d09d78fc | 295 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 296 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 297 | |
7222e8db | 298 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 299 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
300 | |
301 | if (lv1ent_page(ent)) { | |
302 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 303 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 304 | } |
2a96536e KC |
305 | } |
306 | ||
307 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
308 | { | |
f171abab | 309 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 310 | struct sysmmu_drvdata *data = dev_id; |
2a96536e | 311 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 312 | sysmmu_iova_t addr = -1; |
7222e8db | 313 | int ret = -ENOSYS; |
2a96536e | 314 | |
2a96536e KC |
315 | WARN_ON(!is_sysmmu_active(data)); |
316 | ||
9d4e7a24 CK |
317 | spin_lock(&data->lock); |
318 | ||
70605870 CK |
319 | if (!IS_ERR(data->clk_master)) |
320 | clk_enable(data->clk_master); | |
9d4e7a24 | 321 | |
7222e8db CK |
322 | itype = (enum exynos_sysmmu_inttype) |
323 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
324 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 325 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
326 | else |
327 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 328 | |
1fab7fa7 CK |
329 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
330 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
331 | __func__, dev_name(data->sysmmu)); | |
332 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
333 | __func__); | |
334 | BUG(); | |
335 | } else { | |
d09d78fc | 336 | unsigned int base = |
1fab7fa7 CK |
337 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
338 | show_fault_information(dev_name(data->sysmmu), | |
339 | itype, base, addr); | |
340 | if (data->domain) | |
341 | ret = report_iommu_fault(data->domain, | |
6b21a5db | 342 | data->master, addr, itype); |
2a96536e KC |
343 | } |
344 | ||
1fab7fa7 CK |
345 | /* fault is not recovered by fault handler */ |
346 | BUG_ON(ret != 0); | |
2a96536e | 347 | |
1fab7fa7 CK |
348 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
349 | ||
350 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 351 | |
70605870 CK |
352 | if (!IS_ERR(data->clk_master)) |
353 | clk_disable(data->clk_master); | |
354 | ||
9d4e7a24 | 355 | spin_unlock(&data->lock); |
2a96536e KC |
356 | |
357 | return IRQ_HANDLED; | |
358 | } | |
359 | ||
6b21a5db | 360 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 361 | { |
70605870 CK |
362 | if (!IS_ERR(data->clk_master)) |
363 | clk_enable(data->clk_master); | |
364 | ||
7222e8db | 365 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 366 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 367 | |
46c16d1e | 368 | clk_disable(data->clk); |
70605870 CK |
369 | if (!IS_ERR(data->clk_master)) |
370 | clk_disable(data->clk_master); | |
2a96536e KC |
371 | } |
372 | ||
6b21a5db | 373 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 374 | { |
6b21a5db | 375 | bool disabled; |
2a96536e KC |
376 | unsigned long flags; |
377 | ||
9d4e7a24 | 378 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 379 | |
6b21a5db CK |
380 | disabled = set_sysmmu_inactive(data); |
381 | ||
382 | if (disabled) { | |
383 | data->pgtable = 0; | |
384 | data->domain = NULL; | |
385 | ||
386 | __sysmmu_disable_nocount(data); | |
2a96536e | 387 | |
6b21a5db CK |
388 | dev_dbg(data->sysmmu, "Disabled\n"); |
389 | } else { | |
390 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
391 | data->activations); | |
2a96536e KC |
392 | } |
393 | ||
6b21a5db CK |
394 | spin_unlock_irqrestore(&data->lock, flags); |
395 | ||
396 | return disabled; | |
397 | } | |
2a96536e | 398 | |
6b21a5db CK |
399 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
400 | { | |
eeb5184b CK |
401 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
402 | unsigned int ver; | |
403 | ||
512bd0c6 | 404 | ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); |
eeb5184b CK |
405 | if (MMU_MAJ_VER(ver) == 3) { |
406 | if (MMU_MIN_VER(ver) >= 2) { | |
407 | cfg |= CFG_FLPDCACHE; | |
408 | if (MMU_MIN_VER(ver) == 3) { | |
409 | cfg |= CFG_ACGEN; | |
410 | cfg &= ~CFG_LRU; | |
411 | } else { | |
412 | cfg |= CFG_SYSSEL; | |
413 | } | |
414 | } | |
415 | } | |
6b21a5db CK |
416 | |
417 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
512bd0c6 | 418 | data->version = ver; |
6b21a5db CK |
419 | } |
420 | ||
421 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
422 | { | |
70605870 CK |
423 | if (!IS_ERR(data->clk_master)) |
424 | clk_enable(data->clk_master); | |
425 | clk_enable(data->clk); | |
426 | ||
6b21a5db CK |
427 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
428 | ||
429 | __sysmmu_init_config(data); | |
430 | ||
431 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 432 | |
7222e8db CK |
433 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
434 | ||
70605870 CK |
435 | if (!IS_ERR(data->clk_master)) |
436 | clk_disable(data->clk_master); | |
6b21a5db | 437 | } |
70605870 | 438 | |
6b21a5db CK |
439 | static int __sysmmu_enable(struct sysmmu_drvdata *data, |
440 | phys_addr_t pgtable, struct iommu_domain *domain) | |
441 | { | |
442 | int ret = 0; | |
443 | unsigned long flags; | |
444 | ||
445 | spin_lock_irqsave(&data->lock, flags); | |
446 | if (set_sysmmu_active(data)) { | |
447 | data->pgtable = pgtable; | |
448 | data->domain = domain; | |
449 | ||
450 | __sysmmu_enable_nocount(data); | |
451 | ||
452 | dev_dbg(data->sysmmu, "Enabled\n"); | |
453 | } else { | |
454 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
455 | ||
456 | dev_dbg(data->sysmmu, "already enabled\n"); | |
457 | } | |
458 | ||
459 | if (WARN_ON(ret < 0)) | |
460 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 461 | |
9d4e7a24 | 462 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
463 | |
464 | return ret; | |
465 | } | |
466 | ||
6b21a5db CK |
467 | /* __exynos_sysmmu_enable: Enables System MMU |
468 | * | |
469 | * returns -error if an error occurred and System MMU is not enabled, | |
470 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
471 | * enabled before. | |
472 | */ | |
473 | static int __exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable, | |
474 | struct iommu_domain *domain) | |
2a96536e | 475 | { |
6b21a5db | 476 | int ret = 0; |
6b21a5db CK |
477 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
478 | struct sysmmu_drvdata *data; | |
2a96536e | 479 | |
6b21a5db | 480 | BUG_ON(!has_sysmmu(dev)); |
2a96536e | 481 | |
6b21a5db CK |
482 | data = dev_get_drvdata(owner->sysmmu); |
483 | ||
484 | ret = __sysmmu_enable(data, pgtable, domain); | |
485 | if (ret >= 0) | |
486 | data->master = dev; | |
487 | ||
2a96536e KC |
488 | return ret; |
489 | } | |
490 | ||
77e38350 | 491 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e | 492 | { |
6b21a5db CK |
493 | bool disabled = true; |
494 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
495 | struct sysmmu_drvdata *data; | |
496 | ||
497 | BUG_ON(!has_sysmmu(dev)); | |
2a96536e | 498 | |
6b21a5db CK |
499 | data = dev_get_drvdata(owner->sysmmu); |
500 | ||
501 | disabled = __sysmmu_disable(data); | |
502 | if (disabled) | |
503 | data->master = NULL; | |
504 | ||
2a96536e KC |
505 | return disabled; |
506 | } | |
507 | ||
66a7ed84 CK |
508 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
509 | sysmmu_iova_t iova) | |
510 | { | |
512bd0c6 | 511 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
512 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
513 | } | |
514 | ||
515 | static void sysmmu_tlb_invalidate_flpdcache(struct device *dev, | |
516 | sysmmu_iova_t iova) | |
517 | { | |
518 | unsigned long flags; | |
519 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
520 | struct sysmmu_drvdata *data = dev_get_drvdata(owner->sysmmu); | |
521 | ||
522 | if (!IS_ERR(data->clk_master)) | |
523 | clk_enable(data->clk_master); | |
524 | ||
525 | spin_lock_irqsave(&data->lock, flags); | |
526 | if (is_sysmmu_active(data)) | |
527 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
528 | spin_unlock_irqrestore(&data->lock, flags); | |
529 | ||
530 | if (!IS_ERR(data->clk_master)) | |
531 | clk_disable(data->clk_master); | |
532 | } | |
533 | ||
d09d78fc | 534 | static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova, |
3ad6b7f3 | 535 | size_t size) |
2a96536e | 536 | { |
6b21a5db | 537 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
2a96536e | 538 | unsigned long flags; |
6b21a5db | 539 | struct sysmmu_drvdata *data; |
2a96536e | 540 | |
6b21a5db | 541 | data = dev_get_drvdata(owner->sysmmu); |
2a96536e | 542 | |
6b21a5db | 543 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 544 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 545 | unsigned int num_inv = 1; |
70605870 CK |
546 | |
547 | if (!IS_ERR(data->clk_master)) | |
548 | clk_enable(data->clk_master); | |
549 | ||
3ad6b7f3 CK |
550 | /* |
551 | * L2TLB invalidation required | |
552 | * 4KB page: 1 invalidation | |
f171abab SK |
553 | * 64KB page: 16 invalidations |
554 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
555 | * because it is set-associative TLB |
556 | * with 8-way and 64 sets. | |
557 | * 1MB page can be cached in one of all sets. | |
558 | * 64KB page can be one of 16 consecutive sets. | |
559 | */ | |
512bd0c6 | 560 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
561 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
562 | ||
7222e8db CK |
563 | if (sysmmu_block(data->sfrbase)) { |
564 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 565 | data->sfrbase, iova, num_inv); |
7222e8db | 566 | sysmmu_unblock(data->sfrbase); |
2a96536e | 567 | } |
70605870 CK |
568 | if (!IS_ERR(data->clk_master)) |
569 | clk_disable(data->clk_master); | |
2a96536e | 570 | } else { |
6b21a5db CK |
571 | dev_dbg(dev, "disabled. Skipping TLB invalidation @ %#x\n", |
572 | iova); | |
2a96536e | 573 | } |
9d4e7a24 | 574 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
575 | } |
576 | ||
6b21a5db | 577 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 578 | { |
46c16d1e | 579 | int irq, ret; |
7222e8db | 580 | struct device *dev = &pdev->dev; |
2a96536e | 581 | struct sysmmu_drvdata *data; |
7222e8db | 582 | struct resource *res; |
2a96536e | 583 | |
46c16d1e CK |
584 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
585 | if (!data) | |
586 | return -ENOMEM; | |
2a96536e | 587 | |
7222e8db | 588 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
589 | data->sfrbase = devm_ioremap_resource(dev, res); |
590 | if (IS_ERR(data->sfrbase)) | |
591 | return PTR_ERR(data->sfrbase); | |
2a96536e | 592 | |
46c16d1e CK |
593 | irq = platform_get_irq(pdev, 0); |
594 | if (irq <= 0) { | |
0bf4e54d | 595 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 596 | return irq; |
2a96536e KC |
597 | } |
598 | ||
46c16d1e | 599 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
600 | dev_name(dev), data); |
601 | if (ret) { | |
46c16d1e CK |
602 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
603 | return ret; | |
2a96536e KC |
604 | } |
605 | ||
46c16d1e CK |
606 | data->clk = devm_clk_get(dev, "sysmmu"); |
607 | if (IS_ERR(data->clk)) { | |
608 | dev_err(dev, "Failed to get clock!\n"); | |
609 | return PTR_ERR(data->clk); | |
610 | } else { | |
611 | ret = clk_prepare(data->clk); | |
612 | if (ret) { | |
613 | dev_err(dev, "Failed to prepare clk\n"); | |
614 | return ret; | |
615 | } | |
2a96536e KC |
616 | } |
617 | ||
70605870 CK |
618 | data->clk_master = devm_clk_get(dev, "master"); |
619 | if (!IS_ERR(data->clk_master)) { | |
620 | ret = clk_prepare(data->clk_master); | |
621 | if (ret) { | |
622 | clk_unprepare(data->clk); | |
623 | dev_err(dev, "Failed to prepare master's clk\n"); | |
624 | return ret; | |
625 | } | |
626 | } | |
627 | ||
2a96536e | 628 | data->sysmmu = dev; |
9d4e7a24 | 629 | spin_lock_init(&data->lock); |
2a96536e | 630 | |
7222e8db CK |
631 | platform_set_drvdata(pdev, data); |
632 | ||
f4723ec1 | 633 | pm_runtime_enable(dev); |
2a96536e | 634 | |
2a96536e | 635 | return 0; |
2a96536e KC |
636 | } |
637 | ||
6b21a5db CK |
638 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
639 | { .compatible = "samsung,exynos-sysmmu", }, | |
640 | { }, | |
641 | }; | |
642 | ||
643 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
644 | .probe = exynos_sysmmu_probe, | |
645 | .driver = { | |
2a96536e | 646 | .name = "exynos-sysmmu", |
6b21a5db | 647 | .of_match_table = sysmmu_of_match, |
2a96536e KC |
648 | } |
649 | }; | |
650 | ||
651 | static inline void pgtable_flush(void *vastart, void *vaend) | |
652 | { | |
653 | dmac_flush_range(vastart, vaend); | |
654 | outer_flush_range(virt_to_phys(vastart), | |
655 | virt_to_phys(vaend)); | |
656 | } | |
657 | ||
e1fd1eaa | 658 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 659 | { |
e1fd1eaa | 660 | struct exynos_iommu_domain *exynos_domain; |
66a7ed84 | 661 | int i; |
2a96536e | 662 | |
e1fd1eaa JR |
663 | if (type != IOMMU_DOMAIN_UNMANAGED) |
664 | return NULL; | |
665 | ||
666 | exynos_domain = kzalloc(sizeof(*exynos_domain), GFP_KERNEL); | |
667 | if (!exynos_domain) | |
668 | return NULL; | |
2a96536e | 669 | |
e1fd1eaa JR |
670 | exynos_domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
671 | if (!exynos_domain->pgtable) | |
2a96536e KC |
672 | goto err_pgtable; |
673 | ||
e1fd1eaa JR |
674 | exynos_domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
675 | if (!exynos_domain->lv2entcnt) | |
2a96536e KC |
676 | goto err_counter; |
677 | ||
f171abab | 678 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 679 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
e1fd1eaa JR |
680 | exynos_domain->pgtable[i + 0] = ZERO_LV2LINK; |
681 | exynos_domain->pgtable[i + 1] = ZERO_LV2LINK; | |
682 | exynos_domain->pgtable[i + 2] = ZERO_LV2LINK; | |
683 | exynos_domain->pgtable[i + 3] = ZERO_LV2LINK; | |
684 | exynos_domain->pgtable[i + 4] = ZERO_LV2LINK; | |
685 | exynos_domain->pgtable[i + 5] = ZERO_LV2LINK; | |
686 | exynos_domain->pgtable[i + 6] = ZERO_LV2LINK; | |
687 | exynos_domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
688 | } |
689 | ||
e1fd1eaa | 690 | pgtable_flush(exynos_domain->pgtable, exynos_domain->pgtable + NUM_LV1ENTRIES); |
2a96536e | 691 | |
e1fd1eaa JR |
692 | spin_lock_init(&exynos_domain->lock); |
693 | spin_lock_init(&exynos_domain->pgtablelock); | |
694 | INIT_LIST_HEAD(&exynos_domain->clients); | |
2a96536e | 695 | |
e1fd1eaa JR |
696 | exynos_domain->domain.geometry.aperture_start = 0; |
697 | exynos_domain->domain.geometry.aperture_end = ~0UL; | |
698 | exynos_domain->domain.geometry.force_aperture = true; | |
3177bb76 | 699 | |
e1fd1eaa | 700 | return &exynos_domain->domain; |
2a96536e KC |
701 | |
702 | err_counter: | |
e1fd1eaa | 703 | free_pages((unsigned long)exynos_domain->pgtable, 2); |
2a96536e | 704 | err_pgtable: |
e1fd1eaa JR |
705 | kfree(exynos_domain); |
706 | return NULL; | |
2a96536e KC |
707 | } |
708 | ||
e1fd1eaa | 709 | static void exynos_iommu_domain_free(struct iommu_domain *domain) |
2a96536e | 710 | { |
e1fd1eaa | 711 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
6b21a5db | 712 | struct exynos_iommu_owner *owner; |
2a96536e KC |
713 | unsigned long flags; |
714 | int i; | |
715 | ||
716 | WARN_ON(!list_empty(&priv->clients)); | |
717 | ||
718 | spin_lock_irqsave(&priv->lock, flags); | |
719 | ||
6b21a5db CK |
720 | list_for_each_entry(owner, &priv->clients, client) { |
721 | while (!exynos_sysmmu_disable(owner->dev)) | |
2a96536e KC |
722 | ; /* until System MMU is actually disabled */ |
723 | } | |
724 | ||
6b21a5db CK |
725 | while (!list_empty(&priv->clients)) |
726 | list_del_init(priv->clients.next); | |
727 | ||
2a96536e KC |
728 | spin_unlock_irqrestore(&priv->lock, flags); |
729 | ||
730 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
731 | if (lv1ent_page(priv->pgtable + i)) | |
734c3c73 CK |
732 | kmem_cache_free(lv2table_kmem_cache, |
733 | phys_to_virt(lv2table_base(priv->pgtable + i))); | |
2a96536e KC |
734 | |
735 | free_pages((unsigned long)priv->pgtable, 2); | |
736 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
e1fd1eaa | 737 | kfree(priv); |
2a96536e KC |
738 | } |
739 | ||
740 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
741 | struct device *dev) | |
742 | { | |
6b21a5db | 743 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
e1fd1eaa | 744 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
7222e8db | 745 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
746 | unsigned long flags; |
747 | int ret; | |
748 | ||
2a96536e KC |
749 | spin_lock_irqsave(&priv->lock, flags); |
750 | ||
6b21a5db | 751 | ret = __exynos_sysmmu_enable(dev, pagetable, domain); |
73db5698 | 752 | if (ret == 0) |
6b21a5db | 753 | list_add_tail(&owner->client, &priv->clients); |
2a96536e KC |
754 | |
755 | spin_unlock_irqrestore(&priv->lock, flags); | |
756 | ||
757 | if (ret < 0) { | |
7222e8db CK |
758 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
759 | __func__, &pagetable); | |
7222e8db | 760 | return ret; |
2a96536e KC |
761 | } |
762 | ||
7222e8db CK |
763 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
764 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
765 | ||
2a96536e KC |
766 | return ret; |
767 | } | |
768 | ||
769 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
770 | struct device *dev) | |
771 | { | |
6b21a5db | 772 | struct exynos_iommu_owner *owner; |
e1fd1eaa | 773 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
7222e8db | 774 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e | 775 | unsigned long flags; |
2a96536e KC |
776 | |
777 | spin_lock_irqsave(&priv->lock, flags); | |
778 | ||
6b21a5db CK |
779 | list_for_each_entry(owner, &priv->clients, client) { |
780 | if (owner == dev->archdata.iommu) { | |
73db5698 | 781 | if (exynos_sysmmu_disable(dev)) |
6b21a5db | 782 | list_del_init(&owner->client); |
2a96536e KC |
783 | break; |
784 | } | |
785 | } | |
786 | ||
6b21a5db | 787 | spin_unlock_irqrestore(&priv->lock, flags); |
2a96536e | 788 | |
6b21a5db | 789 | if (owner == dev->archdata.iommu) |
7222e8db CK |
790 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
791 | __func__, &pagetable); | |
6b21a5db CK |
792 | else |
793 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
794 | } |
795 | ||
66a7ed84 CK |
796 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *priv, |
797 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) | |
2a96536e | 798 | { |
61128f08 | 799 | if (lv1ent_section(sent)) { |
d09d78fc | 800 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
801 | return ERR_PTR(-EADDRINUSE); |
802 | } | |
803 | ||
2a96536e | 804 | if (lv1ent_fault(sent)) { |
d09d78fc | 805 | sysmmu_pte_t *pent; |
66a7ed84 | 806 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 807 | |
734c3c73 | 808 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 809 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 810 | if (!pent) |
61128f08 | 811 | return ERR_PTR(-ENOMEM); |
2a96536e | 812 | |
7222e8db | 813 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
dc3814f4 | 814 | kmemleak_ignore(pent); |
2a96536e KC |
815 | *pgcounter = NUM_LV2ENTRIES; |
816 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
817 | pgtable_flush(sent, sent + 1); | |
66a7ed84 CK |
818 | |
819 | /* | |
f171abab SK |
820 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
821 | * FLPD cache may cache the address of zero_l2_table. This | |
822 | * function replaces the zero_l2_table with new L2 page table | |
823 | * to write valid mappings. | |
66a7ed84 | 824 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
825 | * cache may still cache zero_l2_table for the valid area |
826 | * instead of new L2 page table that has the mapping | |
827 | * information of the valid area. | |
66a7ed84 CK |
828 | * Thus any replacement of zero_l2_table with other valid L2 |
829 | * page table must involve FLPD cache invalidation for System | |
830 | * MMU v3.3. | |
831 | * FLPD cache invalidation is performed with TLB invalidation | |
832 | * by VPN without blocking. It is safe to invalidate TLB without | |
833 | * blocking because the target address of TLB invalidation is | |
834 | * not currently mapped. | |
835 | */ | |
836 | if (need_flush_flpd_cache) { | |
837 | struct exynos_iommu_owner *owner; | |
365409db | 838 | |
66a7ed84 CK |
839 | spin_lock(&priv->lock); |
840 | list_for_each_entry(owner, &priv->clients, client) | |
841 | sysmmu_tlb_invalidate_flpdcache( | |
842 | owner->dev, iova); | |
843 | spin_unlock(&priv->lock); | |
844 | } | |
2a96536e KC |
845 | } |
846 | ||
847 | return page_entry(sent, iova); | |
848 | } | |
849 | ||
66a7ed84 CK |
850 | static int lv1set_section(struct exynos_iommu_domain *priv, |
851 | sysmmu_pte_t *sent, sysmmu_iova_t iova, | |
61128f08 | 852 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 853 | { |
61128f08 | 854 | if (lv1ent_section(sent)) { |
d09d78fc | 855 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 856 | iova); |
2a96536e | 857 | return -EADDRINUSE; |
61128f08 | 858 | } |
2a96536e KC |
859 | |
860 | if (lv1ent_page(sent)) { | |
61128f08 | 861 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 862 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 863 | iova); |
2a96536e | 864 | return -EADDRINUSE; |
61128f08 | 865 | } |
2a96536e | 866 | |
734c3c73 | 867 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
868 | *pgcnt = 0; |
869 | } | |
870 | ||
871 | *sent = mk_lv1ent_sect(paddr); | |
872 | ||
873 | pgtable_flush(sent, sent + 1); | |
874 | ||
66a7ed84 CK |
875 | spin_lock(&priv->lock); |
876 | if (lv1ent_page_zero(sent)) { | |
877 | struct exynos_iommu_owner *owner; | |
878 | /* | |
879 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
880 | * entry by speculative prefetch of SLPD which has no mapping. | |
881 | */ | |
882 | list_for_each_entry(owner, &priv->clients, client) | |
883 | sysmmu_tlb_invalidate_flpdcache(owner->dev, iova); | |
884 | } | |
885 | spin_unlock(&priv->lock); | |
886 | ||
2a96536e KC |
887 | return 0; |
888 | } | |
889 | ||
d09d78fc | 890 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
891 | short *pgcnt) |
892 | { | |
893 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 894 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
895 | return -EADDRINUSE; |
896 | ||
897 | *pent = mk_lv2ent_spage(paddr); | |
898 | pgtable_flush(pent, pent + 1); | |
899 | *pgcnt -= 1; | |
900 | } else { /* size == LPAGE_SIZE */ | |
901 | int i; | |
365409db | 902 | |
2a96536e | 903 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 904 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
905 | if (i > 0) |
906 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
907 | return -EADDRINUSE; |
908 | } | |
909 | ||
910 | *pent = mk_lv2ent_lpage(paddr); | |
911 | } | |
912 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
913 | *pgcnt -= SPAGES_PER_LPAGE; | |
914 | } | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
66a7ed84 CK |
919 | /* |
920 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
921 | * | |
f171abab | 922 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 923 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
924 | * However, the logic has a bug that while caching faulty page table entries, |
925 | * System MMU reports page fault if the cached fault entry is hit even though | |
926 | * the fault entry is updated to a valid entry after the entry is cached. | |
927 | * To prevent caching faulty page table entries which may be updated to valid | |
928 | * entries later, the virtual memory manager should care about the workaround | |
929 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
930 | * |
931 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 932 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 933 | * |
f171abab | 934 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
935 | * the following sizes for System MMU v3.1 and v3.2. |
936 | * System MMU v3.1: 128KiB | |
937 | * System MMU v3.2: 256KiB | |
938 | * | |
939 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
940 | * more workarounds. |
941 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
942 | * than or equal to 128KiB. | |
66a7ed84 CK |
943 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
944 | */ | |
d09d78fc | 945 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova, |
2a96536e KC |
946 | phys_addr_t paddr, size_t size, int prot) |
947 | { | |
e1fd1eaa | 948 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
d09d78fc CK |
949 | sysmmu_pte_t *entry; |
950 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
951 | unsigned long flags; |
952 | int ret = -ENOMEM; | |
953 | ||
954 | BUG_ON(priv->pgtable == NULL); | |
955 | ||
956 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
957 | ||
958 | entry = section_entry(priv->pgtable, iova); | |
959 | ||
960 | if (size == SECT_SIZE) { | |
66a7ed84 | 961 | ret = lv1set_section(priv, entry, iova, paddr, |
2a96536e KC |
962 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
963 | } else { | |
d09d78fc | 964 | sysmmu_pte_t *pent; |
2a96536e | 965 | |
66a7ed84 | 966 | pent = alloc_lv2entry(priv, entry, iova, |
2a96536e KC |
967 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
968 | ||
61128f08 CK |
969 | if (IS_ERR(pent)) |
970 | ret = PTR_ERR(pent); | |
2a96536e KC |
971 | else |
972 | ret = lv2set_page(pent, paddr, size, | |
973 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
974 | } | |
975 | ||
61128f08 | 976 | if (ret) |
0bf4e54d CK |
977 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
978 | __func__, ret, size, iova); | |
2a96536e KC |
979 | |
980 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
981 | ||
982 | return ret; | |
983 | } | |
984 | ||
66a7ed84 CK |
985 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *priv, |
986 | sysmmu_iova_t iova, size_t size) | |
987 | { | |
988 | struct exynos_iommu_owner *owner; | |
989 | unsigned long flags; | |
990 | ||
991 | spin_lock_irqsave(&priv->lock, flags); | |
992 | ||
993 | list_for_each_entry(owner, &priv->clients, client) | |
994 | sysmmu_tlb_invalidate_entry(owner->dev, iova, size); | |
995 | ||
996 | spin_unlock_irqrestore(&priv->lock, flags); | |
997 | } | |
998 | ||
2a96536e | 999 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, |
d09d78fc | 1000 | unsigned long l_iova, size_t size) |
2a96536e | 1001 | { |
e1fd1eaa | 1002 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
d09d78fc CK |
1003 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1004 | sysmmu_pte_t *ent; | |
61128f08 | 1005 | size_t err_pgsize; |
d09d78fc | 1006 | unsigned long flags; |
2a96536e KC |
1007 | |
1008 | BUG_ON(priv->pgtable == NULL); | |
1009 | ||
1010 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
1011 | ||
1012 | ent = section_entry(priv->pgtable, iova); | |
1013 | ||
1014 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1015 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1016 | err_pgsize = SECT_SIZE; |
1017 | goto err; | |
1018 | } | |
2a96536e | 1019 | |
f171abab SK |
1020 | /* workaround for h/w bug in System MMU v3.3 */ |
1021 | *ent = ZERO_LV2LINK; | |
2a96536e KC |
1022 | pgtable_flush(ent, ent + 1); |
1023 | size = SECT_SIZE; | |
1024 | goto done; | |
1025 | } | |
1026 | ||
1027 | if (unlikely(lv1ent_fault(ent))) { | |
1028 | if (size > SECT_SIZE) | |
1029 | size = SECT_SIZE; | |
1030 | goto done; | |
1031 | } | |
1032 | ||
1033 | /* lv1ent_page(sent) == true here */ | |
1034 | ||
1035 | ent = page_entry(ent, iova); | |
1036 | ||
1037 | if (unlikely(lv2ent_fault(ent))) { | |
1038 | size = SPAGE_SIZE; | |
1039 | goto done; | |
1040 | } | |
1041 | ||
1042 | if (lv2ent_small(ent)) { | |
1043 | *ent = 0; | |
1044 | size = SPAGE_SIZE; | |
6cb47ed7 | 1045 | pgtable_flush(ent, ent + 1); |
2a96536e KC |
1046 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; |
1047 | goto done; | |
1048 | } | |
1049 | ||
1050 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1051 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1052 | err_pgsize = LPAGE_SIZE; |
1053 | goto err; | |
1054 | } | |
2a96536e KC |
1055 | |
1056 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 1057 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
1058 | |
1059 | size = LPAGE_SIZE; | |
1060 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
1061 | done: | |
1062 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
1063 | ||
66a7ed84 | 1064 | exynos_iommu_tlb_invalidate_entry(priv, iova, size); |
2a96536e | 1065 | |
2a96536e | 1066 | return size; |
61128f08 CK |
1067 | err: |
1068 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
1069 | ||
0bf4e54d CK |
1070 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1071 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1072 | |
1073 | return 0; | |
2a96536e KC |
1074 | } |
1075 | ||
1076 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 1077 | dma_addr_t iova) |
2a96536e | 1078 | { |
e1fd1eaa | 1079 | struct exynos_iommu_domain *priv = to_exynos_domain(domain); |
d09d78fc | 1080 | sysmmu_pte_t *entry; |
2a96536e KC |
1081 | unsigned long flags; |
1082 | phys_addr_t phys = 0; | |
1083 | ||
1084 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
1085 | ||
1086 | entry = section_entry(priv->pgtable, iova); | |
1087 | ||
1088 | if (lv1ent_section(entry)) { | |
1089 | phys = section_phys(entry) + section_offs(iova); | |
1090 | } else if (lv1ent_page(entry)) { | |
1091 | entry = page_entry(entry, iova); | |
1092 | ||
1093 | if (lv2ent_large(entry)) | |
1094 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1095 | else if (lv2ent_small(entry)) | |
1096 | phys = spage_phys(entry) + spage_offs(iova); | |
1097 | } | |
1098 | ||
1099 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
1100 | ||
1101 | return phys; | |
1102 | } | |
1103 | ||
bf4a1c92 AM |
1104 | static int exynos_iommu_add_device(struct device *dev) |
1105 | { | |
1106 | struct iommu_group *group; | |
1107 | int ret; | |
1108 | ||
1109 | group = iommu_group_get(dev); | |
1110 | ||
1111 | if (!group) { | |
1112 | group = iommu_group_alloc(); | |
1113 | if (IS_ERR(group)) { | |
1114 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1115 | return PTR_ERR(group); | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | ret = iommu_group_add_device(group, dev); | |
1120 | iommu_group_put(group); | |
1121 | ||
1122 | return ret; | |
1123 | } | |
1124 | ||
1125 | static void exynos_iommu_remove_device(struct device *dev) | |
1126 | { | |
1127 | iommu_group_remove_device(dev); | |
1128 | } | |
1129 | ||
b22f6434 | 1130 | static const struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1131 | .domain_alloc = exynos_iommu_domain_alloc, |
1132 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1133 | .attach_dev = exynos_iommu_attach_device, |
1134 | .detach_dev = exynos_iommu_detach_device, | |
1135 | .map = exynos_iommu_map, | |
1136 | .unmap = exynos_iommu_unmap, | |
315786eb | 1137 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 BH |
1138 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1139 | .add_device = exynos_iommu_add_device, | |
1140 | .remove_device = exynos_iommu_remove_device, | |
2a96536e KC |
1141 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
1142 | }; | |
1143 | ||
1144 | static int __init exynos_iommu_init(void) | |
1145 | { | |
a7b67cd5 | 1146 | struct device_node *np; |
2a96536e KC |
1147 | int ret; |
1148 | ||
a7b67cd5 TR |
1149 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1150 | if (!np) | |
1151 | return 0; | |
1152 | ||
1153 | of_node_put(np); | |
1154 | ||
734c3c73 CK |
1155 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1156 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1157 | if (!lv2table_kmem_cache) { | |
1158 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1159 | return -ENOMEM; | |
1160 | } | |
1161 | ||
2a96536e | 1162 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1163 | if (ret) { |
1164 | pr_err("%s: Failed to register driver\n", __func__); | |
1165 | goto err_reg_driver; | |
1166 | } | |
2a96536e | 1167 | |
66a7ed84 CK |
1168 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1169 | if (zero_lv2_table == NULL) { | |
1170 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1171 | __func__); | |
1172 | ret = -ENOMEM; | |
1173 | goto err_zero_lv2; | |
1174 | } | |
1175 | ||
734c3c73 CK |
1176 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1177 | if (ret) { | |
1178 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1179 | __func__); | |
1180 | goto err_set_iommu; | |
1181 | } | |
2a96536e | 1182 | |
734c3c73 CK |
1183 | return 0; |
1184 | err_set_iommu: | |
66a7ed84 CK |
1185 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1186 | err_zero_lv2: | |
734c3c73 CK |
1187 | platform_driver_unregister(&exynos_sysmmu_driver); |
1188 | err_reg_driver: | |
1189 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1190 | return ret; |
1191 | } | |
1192 | subsys_initcall(exynos_iommu_init); |