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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
2a96536e KC |
32 | /* We does not consider super section mapping (16MB) */ |
33 | #define SECT_ORDER 20 | |
34 | #define LPAGE_ORDER 16 | |
35 | #define SPAGE_ORDER 12 | |
36 | ||
37 | #define SECT_SIZE (1 << SECT_ORDER) | |
38 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
39 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
40 | ||
41 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
42 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
43 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
44 | ||
45 | #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_page(sent) ((*(sent) & 3) == 1) | |
47 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) | |
48 | ||
49 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
50 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
51 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
52 | ||
53 | #define section_phys(sent) (*(sent) & SECT_MASK) | |
54 | #define section_offs(iova) ((iova) & 0xFFFFF) | |
55 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) | |
56 | #define lpage_offs(iova) ((iova) & 0xFFFF) | |
57 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) | |
58 | #define spage_offs(iova) ((iova) & 0xFFF) | |
59 | ||
60 | #define lv1ent_offset(iova) ((iova) >> SECT_ORDER) | |
61 | #define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER) | |
62 | ||
63 | #define NUM_LV1ENTRIES 4096 | |
64 | #define NUM_LV2ENTRIES 256 | |
65 | ||
66 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long)) | |
67 | ||
68 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
69 | ||
70 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
71 | ||
72 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
73 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
74 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
75 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
76 | ||
77 | #define CTRL_ENABLE 0x5 | |
78 | #define CTRL_BLOCK 0x7 | |
79 | #define CTRL_DISABLE 0x0 | |
80 | ||
81 | #define REG_MMU_CTRL 0x000 | |
82 | #define REG_MMU_CFG 0x004 | |
83 | #define REG_MMU_STATUS 0x008 | |
84 | #define REG_MMU_FLUSH 0x00C | |
85 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
86 | #define REG_PT_BASE_ADDR 0x014 | |
87 | #define REG_INT_STATUS 0x018 | |
88 | #define REG_INT_CLEAR 0x01C | |
89 | ||
90 | #define REG_PAGE_FAULT_ADDR 0x024 | |
91 | #define REG_AW_FAULT_ADDR 0x028 | |
92 | #define REG_AR_FAULT_ADDR 0x02C | |
93 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
94 | ||
95 | #define REG_MMU_VERSION 0x034 | |
96 | ||
97 | #define REG_PB0_SADDR 0x04C | |
98 | #define REG_PB0_EADDR 0x050 | |
99 | #define REG_PB1_SADDR 0x054 | |
100 | #define REG_PB1_EADDR 0x058 | |
101 | ||
102 | static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova) | |
103 | { | |
104 | return pgtable + lv1ent_offset(iova); | |
105 | } | |
106 | ||
107 | static unsigned long *page_entry(unsigned long *sent, unsigned long iova) | |
108 | { | |
7222e8db CK |
109 | return (unsigned long *)phys_to_virt( |
110 | lv2table_base(sent)) + lv2ent_offset(iova); | |
2a96536e KC |
111 | } |
112 | ||
113 | enum exynos_sysmmu_inttype { | |
114 | SYSMMU_PAGEFAULT, | |
115 | SYSMMU_AR_MULTIHIT, | |
116 | SYSMMU_AW_MULTIHIT, | |
117 | SYSMMU_BUSERROR, | |
118 | SYSMMU_AR_SECURITY, | |
119 | SYSMMU_AR_ACCESS, | |
120 | SYSMMU_AW_SECURITY, | |
121 | SYSMMU_AW_PROTECTION, /* 7 */ | |
122 | SYSMMU_FAULT_UNKNOWN, | |
123 | SYSMMU_FAULTS_NUM | |
124 | }; | |
125 | ||
126 | /* | |
127 | * @itype: type of fault. | |
128 | * @pgtable_base: the physical address of page table base. This is 0 if @itype | |
129 | * is SYSMMU_BUSERROR. | |
130 | * @fault_addr: the device (virtual) address that the System MMU tried to | |
131 | * translated. This is 0 if @itype is SYSMMU_BUSERROR. | |
132 | */ | |
133 | typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype, | |
7222e8db | 134 | phys_addr_t pgtable_base, unsigned long fault_addr); |
2a96536e KC |
135 | |
136 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { | |
137 | REG_PAGE_FAULT_ADDR, | |
138 | REG_AR_FAULT_ADDR, | |
139 | REG_AW_FAULT_ADDR, | |
140 | REG_DEFAULT_SLAVE_ADDR, | |
141 | REG_AR_FAULT_ADDR, | |
142 | REG_AR_FAULT_ADDR, | |
143 | REG_AW_FAULT_ADDR, | |
144 | REG_AW_FAULT_ADDR | |
145 | }; | |
146 | ||
147 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
148 | "PAGE FAULT", | |
149 | "AR MULTI-HIT FAULT", | |
150 | "AW MULTI-HIT FAULT", | |
151 | "BUS ERROR", | |
152 | "AR SECURITY PROTECTION FAULT", | |
153 | "AR ACCESS PROTECTION FAULT", | |
154 | "AW SECURITY PROTECTION FAULT", | |
155 | "AW ACCESS PROTECTION FAULT", | |
156 | "UNKNOWN FAULT" | |
157 | }; | |
158 | ||
159 | struct exynos_iommu_domain { | |
160 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
161 | unsigned long *pgtable; /* lv1 page table, 16KB */ | |
162 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
163 | spinlock_t lock; /* lock for this structure */ | |
164 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
165 | }; | |
166 | ||
167 | struct sysmmu_drvdata { | |
168 | struct list_head node; /* entry of exynos_iommu_domain.clients */ | |
169 | struct device *sysmmu; /* System MMU's device descriptor */ | |
170 | struct device *dev; /* Owner of system MMU */ | |
171 | char *dbgname; | |
7222e8db CK |
172 | void __iomem *sfrbase; |
173 | struct clk *clk; | |
2a96536e KC |
174 | int activations; |
175 | rwlock_t lock; | |
176 | struct iommu_domain *domain; | |
177 | sysmmu_fault_handler_t fault_handler; | |
7222e8db | 178 | phys_addr_t pgtable; |
2a96536e KC |
179 | }; |
180 | ||
181 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) | |
182 | { | |
183 | /* return true if the System MMU was not active previously | |
184 | and it needs to be initialized */ | |
185 | return ++data->activations == 1; | |
186 | } | |
187 | ||
188 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
189 | { | |
190 | /* return true if the System MMU is needed to be disabled */ | |
191 | BUG_ON(data->activations < 1); | |
192 | return --data->activations == 0; | |
193 | } | |
194 | ||
195 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
196 | { | |
197 | return data->activations > 0; | |
198 | } | |
199 | ||
200 | static void sysmmu_unblock(void __iomem *sfrbase) | |
201 | { | |
202 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
203 | } | |
204 | ||
205 | static bool sysmmu_block(void __iomem *sfrbase) | |
206 | { | |
207 | int i = 120; | |
208 | ||
209 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
210 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
211 | --i; | |
212 | ||
213 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
214 | sysmmu_unblock(sfrbase); | |
215 | return false; | |
216 | } | |
217 | ||
218 | return true; | |
219 | } | |
220 | ||
221 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
222 | { | |
223 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
224 | } | |
225 | ||
226 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
227 | unsigned long iova) | |
228 | { | |
229 | __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY); | |
230 | } | |
231 | ||
232 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
233 | unsigned long pgd) | |
234 | { | |
235 | __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */ | |
236 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); | |
237 | ||
238 | __sysmmu_tlb_invalidate(sfrbase); | |
239 | } | |
240 | ||
241 | static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base, | |
242 | unsigned long size, int idx) | |
243 | { | |
244 | __raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8); | |
245 | __raw_writel(size - 1 + base, sfrbase + REG_PB0_EADDR + idx * 8); | |
246 | } | |
247 | ||
2a96536e KC |
248 | static void __set_fault_handler(struct sysmmu_drvdata *data, |
249 | sysmmu_fault_handler_t handler) | |
250 | { | |
251 | unsigned long flags; | |
252 | ||
253 | write_lock_irqsave(&data->lock, flags); | |
254 | data->fault_handler = handler; | |
255 | write_unlock_irqrestore(&data->lock, flags); | |
256 | } | |
257 | ||
258 | void exynos_sysmmu_set_fault_handler(struct device *dev, | |
259 | sysmmu_fault_handler_t handler) | |
260 | { | |
261 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
262 | ||
263 | __set_fault_handler(data, handler); | |
264 | } | |
265 | ||
266 | static int default_fault_handler(enum exynos_sysmmu_inttype itype, | |
7222e8db | 267 | phys_addr_t pgtable_base, unsigned long fault_addr) |
2a96536e KC |
268 | { |
269 | unsigned long *ent; | |
270 | ||
271 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
272 | itype = SYSMMU_FAULT_UNKNOWN; | |
273 | ||
7222e8db CK |
274 | pr_err("%s occurred at 0x%lx(Page table base: %pa)\n", |
275 | sysmmu_fault_name[itype], fault_addr, &pgtable_base); | |
2a96536e | 276 | |
7222e8db | 277 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
2a96536e KC |
278 | pr_err("\tLv1 entry: 0x%lx\n", *ent); |
279 | ||
280 | if (lv1ent_page(ent)) { | |
281 | ent = page_entry(ent, fault_addr); | |
282 | pr_err("\t Lv2 entry: 0x%lx\n", *ent); | |
283 | } | |
284 | ||
285 | pr_err("Generating Kernel OOPS... because it is unrecoverable.\n"); | |
286 | ||
287 | BUG(); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
293 | { | |
294 | /* SYSMMU is in blocked when interrupt occurred. */ | |
295 | struct sysmmu_drvdata *data = dev_id; | |
2a96536e KC |
296 | enum exynos_sysmmu_inttype itype; |
297 | unsigned long addr = -1; | |
7222e8db | 298 | int ret = -ENOSYS; |
2a96536e KC |
299 | |
300 | read_lock(&data->lock); | |
301 | ||
302 | WARN_ON(!is_sysmmu_active(data)); | |
303 | ||
7222e8db CK |
304 | itype = (enum exynos_sysmmu_inttype) |
305 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
306 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 307 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
308 | else |
309 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e KC |
310 | |
311 | if (data->domain) | |
7222e8db | 312 | ret = report_iommu_fault(data->domain, data->dev, addr, itype); |
2a96536e KC |
313 | |
314 | if ((ret == -ENOSYS) && data->fault_handler) { | |
315 | unsigned long base = data->pgtable; | |
316 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 317 | base = __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
2a96536e KC |
318 | ret = data->fault_handler(itype, base, addr); |
319 | } | |
320 | ||
321 | if (!ret && (itype != SYSMMU_FAULT_UNKNOWN)) | |
7222e8db | 322 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
2a96536e KC |
323 | else |
324 | dev_dbg(data->sysmmu, "(%s) %s is not handled.\n", | |
325 | data->dbgname, sysmmu_fault_name[itype]); | |
326 | ||
327 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 328 | sysmmu_unblock(data->sfrbase); |
2a96536e KC |
329 | |
330 | read_unlock(&data->lock); | |
331 | ||
332 | return IRQ_HANDLED; | |
333 | } | |
334 | ||
335 | static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data) | |
336 | { | |
337 | unsigned long flags; | |
338 | bool disabled = false; | |
2a96536e KC |
339 | |
340 | write_lock_irqsave(&data->lock, flags); | |
341 | ||
342 | if (!set_sysmmu_inactive(data)) | |
343 | goto finish; | |
344 | ||
7222e8db | 345 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e | 346 | |
7222e8db CK |
347 | if (!IS_ERR(data->clk)) |
348 | clk_disable(data->clk); | |
2a96536e KC |
349 | |
350 | disabled = true; | |
351 | data->pgtable = 0; | |
352 | data->domain = NULL; | |
353 | finish: | |
354 | write_unlock_irqrestore(&data->lock, flags); | |
355 | ||
356 | if (disabled) | |
357 | dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname); | |
358 | else | |
359 | dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n", | |
360 | data->dbgname, data->activations); | |
361 | ||
362 | return disabled; | |
363 | } | |
364 | ||
365 | /* __exynos_sysmmu_enable: Enables System MMU | |
366 | * | |
367 | * returns -error if an error occurred and System MMU is not enabled, | |
368 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
369 | * enabled before. | |
370 | */ | |
371 | static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data, | |
372 | unsigned long pgtable, struct iommu_domain *domain) | |
373 | { | |
7222e8db | 374 | int ret = 0; |
2a96536e KC |
375 | unsigned long flags; |
376 | ||
377 | write_lock_irqsave(&data->lock, flags); | |
378 | ||
379 | if (!set_sysmmu_active(data)) { | |
380 | if (WARN_ON(pgtable != data->pgtable)) { | |
381 | ret = -EBUSY; | |
382 | set_sysmmu_inactive(data); | |
383 | } else { | |
384 | ret = 1; | |
385 | } | |
386 | ||
387 | dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname); | |
388 | goto finish; | |
389 | } | |
390 | ||
7222e8db CK |
391 | if (!IS_ERR(data->clk)) |
392 | clk_enable(data->clk); | |
2a96536e KC |
393 | |
394 | data->pgtable = pgtable; | |
395 | ||
7222e8db CK |
396 | __sysmmu_set_ptbase(data->sfrbase, pgtable); |
397 | if ((readl(data->sfrbase + REG_MMU_VERSION) >> 28) == 3) { | |
398 | /* System MMU version is 3.x */ | |
399 | __raw_writel((1 << 12) | (2 << 28), | |
400 | data->sfrbase + REG_MMU_CFG); | |
401 | __sysmmu_set_prefbuf(data->sfrbase, 0, -1, 0); | |
402 | __sysmmu_set_prefbuf(data->sfrbase, 0, -1, 1); | |
2a96536e KC |
403 | } |
404 | ||
7222e8db CK |
405 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
406 | ||
2a96536e KC |
407 | data->domain = domain; |
408 | ||
409 | dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname); | |
410 | finish: | |
411 | write_unlock_irqrestore(&data->lock, flags); | |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
416 | int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable) | |
417 | { | |
418 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
419 | int ret; | |
420 | ||
421 | BUG_ON(!memblock_is_memory(pgtable)); | |
422 | ||
423 | ret = pm_runtime_get_sync(data->sysmmu); | |
424 | if (ret < 0) { | |
425 | dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname); | |
426 | return ret; | |
427 | } | |
428 | ||
429 | ret = __exynos_sysmmu_enable(data, pgtable, NULL); | |
430 | if (WARN_ON(ret < 0)) { | |
431 | pm_runtime_put(data->sysmmu); | |
432 | dev_err(data->sysmmu, | |
7222e8db | 433 | "(%s) Already enabled with page table %#x\n", |
2a96536e KC |
434 | data->dbgname, data->pgtable); |
435 | } else { | |
436 | data->dev = dev; | |
437 | } | |
438 | ||
439 | return ret; | |
440 | } | |
441 | ||
77e38350 | 442 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e KC |
443 | { |
444 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
445 | bool disabled; | |
446 | ||
447 | disabled = __exynos_sysmmu_disable(data); | |
448 | pm_runtime_put(data->sysmmu); | |
449 | ||
450 | return disabled; | |
451 | } | |
452 | ||
453 | static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova) | |
454 | { | |
455 | unsigned long flags; | |
456 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
457 | ||
458 | read_lock_irqsave(&data->lock, flags); | |
459 | ||
460 | if (is_sysmmu_active(data)) { | |
7222e8db CK |
461 | if (sysmmu_block(data->sfrbase)) { |
462 | __sysmmu_tlb_invalidate_entry( | |
463 | data->sfrbase, iova); | |
464 | sysmmu_unblock(data->sfrbase); | |
2a96536e KC |
465 | } |
466 | } else { | |
467 | dev_dbg(data->sysmmu, | |
468 | "(%s) Disabled. Skipping invalidating TLB.\n", | |
469 | data->dbgname); | |
470 | } | |
471 | ||
472 | read_unlock_irqrestore(&data->lock, flags); | |
473 | } | |
474 | ||
475 | void exynos_sysmmu_tlb_invalidate(struct device *dev) | |
476 | { | |
477 | unsigned long flags; | |
478 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
479 | ||
480 | read_lock_irqsave(&data->lock, flags); | |
481 | ||
482 | if (is_sysmmu_active(data)) { | |
7222e8db CK |
483 | if (sysmmu_block(data->sfrbase)) { |
484 | __sysmmu_tlb_invalidate(data->sfrbase); | |
485 | sysmmu_unblock(data->sfrbase); | |
2a96536e KC |
486 | } |
487 | } else { | |
488 | dev_dbg(data->sysmmu, | |
489 | "(%s) Disabled. Skipping invalidating TLB.\n", | |
490 | data->dbgname); | |
491 | } | |
492 | ||
493 | read_unlock_irqrestore(&data->lock, flags); | |
494 | } | |
495 | ||
496 | static int exynos_sysmmu_probe(struct platform_device *pdev) | |
497 | { | |
7222e8db CK |
498 | int ret; |
499 | struct device *dev = &pdev->dev; | |
2a96536e | 500 | struct sysmmu_drvdata *data; |
7222e8db | 501 | struct resource *res; |
2a96536e KC |
502 | |
503 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
504 | if (!data) { | |
505 | dev_dbg(dev, "Not enough memory\n"); | |
506 | ret = -ENOMEM; | |
507 | goto err_alloc; | |
508 | } | |
509 | ||
7222e8db CK |
510 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
511 | if (!res) { | |
512 | dev_dbg(dev, "Unable to find IOMEM region\n"); | |
513 | ret = -ENOENT; | |
2a96536e KC |
514 | goto err_init; |
515 | } | |
516 | ||
7222e8db CK |
517 | data->sfrbase = ioremap(res->start, resource_size(res)); |
518 | if (!data->sfrbase) { | |
519 | dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n", res->start); | |
520 | ret = -ENOENT; | |
521 | goto err_res; | |
2a96536e KC |
522 | } |
523 | ||
7222e8db CK |
524 | ret = platform_get_irq(pdev, 0); |
525 | if (ret <= 0) { | |
526 | dev_dbg(dev, "Unable to find IRQ resource\n"); | |
527 | goto err_irq; | |
2a96536e KC |
528 | } |
529 | ||
7222e8db CK |
530 | ret = request_irq(ret, exynos_sysmmu_irq, 0, |
531 | dev_name(dev), data); | |
532 | if (ret) { | |
533 | dev_dbg(dev, "Unabled to register interrupt handler\n"); | |
534 | goto err_irq; | |
2a96536e KC |
535 | } |
536 | ||
537 | if (dev_get_platdata(dev)) { | |
7222e8db CK |
538 | data->clk = clk_get(dev, "sysmmu"); |
539 | if (IS_ERR(data->clk)) | |
2a96536e | 540 | dev_dbg(dev, "No clock descriptor registered\n"); |
2a96536e KC |
541 | } |
542 | ||
543 | data->sysmmu = dev; | |
544 | rwlock_init(&data->lock); | |
545 | INIT_LIST_HEAD(&data->node); | |
546 | ||
547 | __set_fault_handler(data, &default_fault_handler); | |
548 | ||
7222e8db CK |
549 | platform_set_drvdata(pdev, data); |
550 | ||
2a96536e KC |
551 | if (dev->parent) |
552 | pm_runtime_enable(dev); | |
553 | ||
554 | dev_dbg(dev, "(%s) Initialized\n", data->dbgname); | |
555 | return 0; | |
556 | err_irq: | |
7222e8db | 557 | free_irq(platform_get_irq(pdev, 0), data); |
2a96536e | 558 | err_res: |
7222e8db | 559 | iounmap(data->sfrbase); |
2a96536e KC |
560 | err_init: |
561 | kfree(data); | |
562 | err_alloc: | |
563 | dev_err(dev, "Failed to initialize\n"); | |
564 | return ret; | |
565 | } | |
566 | ||
567 | static struct platform_driver exynos_sysmmu_driver = { | |
568 | .probe = exynos_sysmmu_probe, | |
569 | .driver = { | |
570 | .owner = THIS_MODULE, | |
571 | .name = "exynos-sysmmu", | |
572 | } | |
573 | }; | |
574 | ||
575 | static inline void pgtable_flush(void *vastart, void *vaend) | |
576 | { | |
577 | dmac_flush_range(vastart, vaend); | |
578 | outer_flush_range(virt_to_phys(vastart), | |
579 | virt_to_phys(vaend)); | |
580 | } | |
581 | ||
582 | static int exynos_iommu_domain_init(struct iommu_domain *domain) | |
583 | { | |
584 | struct exynos_iommu_domain *priv; | |
585 | ||
586 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
587 | if (!priv) | |
588 | return -ENOMEM; | |
589 | ||
590 | priv->pgtable = (unsigned long *)__get_free_pages( | |
591 | GFP_KERNEL | __GFP_ZERO, 2); | |
592 | if (!priv->pgtable) | |
593 | goto err_pgtable; | |
594 | ||
595 | priv->lv2entcnt = (short *)__get_free_pages( | |
596 | GFP_KERNEL | __GFP_ZERO, 1); | |
597 | if (!priv->lv2entcnt) | |
598 | goto err_counter; | |
599 | ||
600 | pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES); | |
601 | ||
602 | spin_lock_init(&priv->lock); | |
603 | spin_lock_init(&priv->pgtablelock); | |
604 | INIT_LIST_HEAD(&priv->clients); | |
605 | ||
eb51637b SK |
606 | domain->geometry.aperture_start = 0; |
607 | domain->geometry.aperture_end = ~0UL; | |
608 | domain->geometry.force_aperture = true; | |
3177bb76 | 609 | |
2a96536e KC |
610 | domain->priv = priv; |
611 | return 0; | |
612 | ||
613 | err_counter: | |
614 | free_pages((unsigned long)priv->pgtable, 2); | |
615 | err_pgtable: | |
616 | kfree(priv); | |
617 | return -ENOMEM; | |
618 | } | |
619 | ||
620 | static void exynos_iommu_domain_destroy(struct iommu_domain *domain) | |
621 | { | |
622 | struct exynos_iommu_domain *priv = domain->priv; | |
623 | struct sysmmu_drvdata *data; | |
624 | unsigned long flags; | |
625 | int i; | |
626 | ||
627 | WARN_ON(!list_empty(&priv->clients)); | |
628 | ||
629 | spin_lock_irqsave(&priv->lock, flags); | |
630 | ||
631 | list_for_each_entry(data, &priv->clients, node) { | |
632 | while (!exynos_sysmmu_disable(data->dev)) | |
633 | ; /* until System MMU is actually disabled */ | |
634 | } | |
635 | ||
636 | spin_unlock_irqrestore(&priv->lock, flags); | |
637 | ||
638 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
639 | if (lv1ent_page(priv->pgtable + i)) | |
7222e8db | 640 | kfree(phys_to_virt(lv2table_base(priv->pgtable + i))); |
2a96536e KC |
641 | |
642 | free_pages((unsigned long)priv->pgtable, 2); | |
643 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
644 | kfree(domain->priv); | |
645 | domain->priv = NULL; | |
646 | } | |
647 | ||
648 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
649 | struct device *dev) | |
650 | { | |
651 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
652 | struct exynos_iommu_domain *priv = domain->priv; | |
7222e8db | 653 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
654 | unsigned long flags; |
655 | int ret; | |
656 | ||
657 | ret = pm_runtime_get_sync(data->sysmmu); | |
658 | if (ret < 0) | |
659 | return ret; | |
660 | ||
661 | ret = 0; | |
662 | ||
663 | spin_lock_irqsave(&priv->lock, flags); | |
664 | ||
7222e8db | 665 | ret = __exynos_sysmmu_enable(data, pagetable, domain); |
2a96536e KC |
666 | |
667 | if (ret == 0) { | |
668 | /* 'data->node' must not be appeared in priv->clients */ | |
669 | BUG_ON(!list_empty(&data->node)); | |
670 | data->dev = dev; | |
671 | list_add_tail(&data->node, &priv->clients); | |
672 | } | |
673 | ||
674 | spin_unlock_irqrestore(&priv->lock, flags); | |
675 | ||
676 | if (ret < 0) { | |
7222e8db CK |
677 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
678 | __func__, &pagetable); | |
2a96536e | 679 | pm_runtime_put(data->sysmmu); |
7222e8db | 680 | return ret; |
2a96536e KC |
681 | } |
682 | ||
7222e8db CK |
683 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
684 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
685 | ||
2a96536e KC |
686 | return ret; |
687 | } | |
688 | ||
689 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
690 | struct device *dev) | |
691 | { | |
692 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
693 | struct exynos_iommu_domain *priv = domain->priv; | |
694 | struct list_head *pos; | |
7222e8db | 695 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
696 | unsigned long flags; |
697 | bool found = false; | |
698 | ||
699 | spin_lock_irqsave(&priv->lock, flags); | |
700 | ||
701 | list_for_each(pos, &priv->clients) { | |
702 | if (list_entry(pos, struct sysmmu_drvdata, node) == data) { | |
703 | found = true; | |
704 | break; | |
705 | } | |
706 | } | |
707 | ||
708 | if (!found) | |
709 | goto finish; | |
710 | ||
711 | if (__exynos_sysmmu_disable(data)) { | |
7222e8db CK |
712 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
713 | __func__, &pagetable); | |
f8ffcc92 | 714 | list_del_init(&data->node); |
2a96536e KC |
715 | |
716 | } else { | |
7222e8db CK |
717 | dev_dbg(dev, "%s: Detaching IOMMU with pgtable %pa delayed", |
718 | __func__, &pagetable); | |
2a96536e KC |
719 | } |
720 | ||
721 | finish: | |
722 | spin_unlock_irqrestore(&priv->lock, flags); | |
723 | ||
724 | if (found) | |
725 | pm_runtime_put(data->sysmmu); | |
726 | } | |
727 | ||
728 | static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova, | |
729 | short *pgcounter) | |
730 | { | |
731 | if (lv1ent_fault(sent)) { | |
732 | unsigned long *pent; | |
733 | ||
734 | pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC); | |
735 | BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1)); | |
736 | if (!pent) | |
737 | return NULL; | |
738 | ||
7222e8db | 739 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
2a96536e KC |
740 | *pgcounter = NUM_LV2ENTRIES; |
741 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
742 | pgtable_flush(sent, sent + 1); | |
743 | } | |
744 | ||
745 | return page_entry(sent, iova); | |
746 | } | |
747 | ||
748 | static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt) | |
749 | { | |
750 | if (lv1ent_section(sent)) | |
751 | return -EADDRINUSE; | |
752 | ||
753 | if (lv1ent_page(sent)) { | |
754 | if (*pgcnt != NUM_LV2ENTRIES) | |
755 | return -EADDRINUSE; | |
756 | ||
757 | kfree(page_entry(sent, 0)); | |
758 | ||
759 | *pgcnt = 0; | |
760 | } | |
761 | ||
762 | *sent = mk_lv1ent_sect(paddr); | |
763 | ||
764 | pgtable_flush(sent, sent + 1); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
769 | static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size, | |
770 | short *pgcnt) | |
771 | { | |
772 | if (size == SPAGE_SIZE) { | |
773 | if (!lv2ent_fault(pent)) | |
774 | return -EADDRINUSE; | |
775 | ||
776 | *pent = mk_lv2ent_spage(paddr); | |
777 | pgtable_flush(pent, pent + 1); | |
778 | *pgcnt -= 1; | |
779 | } else { /* size == LPAGE_SIZE */ | |
780 | int i; | |
781 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { | |
782 | if (!lv2ent_fault(pent)) { | |
783 | memset(pent, 0, sizeof(*pent) * i); | |
784 | return -EADDRINUSE; | |
785 | } | |
786 | ||
787 | *pent = mk_lv2ent_lpage(paddr); | |
788 | } | |
789 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
790 | *pgcnt -= SPAGES_PER_LPAGE; | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
797 | phys_addr_t paddr, size_t size, int prot) | |
798 | { | |
799 | struct exynos_iommu_domain *priv = domain->priv; | |
800 | unsigned long *entry; | |
801 | unsigned long flags; | |
802 | int ret = -ENOMEM; | |
803 | ||
804 | BUG_ON(priv->pgtable == NULL); | |
805 | ||
806 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
807 | ||
808 | entry = section_entry(priv->pgtable, iova); | |
809 | ||
810 | if (size == SECT_SIZE) { | |
811 | ret = lv1set_section(entry, paddr, | |
812 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
813 | } else { | |
814 | unsigned long *pent; | |
815 | ||
816 | pent = alloc_lv2entry(entry, iova, | |
817 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
818 | ||
819 | if (!pent) | |
820 | ret = -ENOMEM; | |
821 | else | |
822 | ret = lv2set_page(pent, paddr, size, | |
823 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
824 | } | |
825 | ||
826 | if (ret) { | |
827 | pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n", | |
828 | __func__, iova, size); | |
829 | } | |
830 | ||
831 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
836 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, | |
837 | unsigned long iova, size_t size) | |
838 | { | |
839 | struct exynos_iommu_domain *priv = domain->priv; | |
840 | struct sysmmu_drvdata *data; | |
841 | unsigned long flags; | |
842 | unsigned long *ent; | |
843 | ||
844 | BUG_ON(priv->pgtable == NULL); | |
845 | ||
846 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
847 | ||
848 | ent = section_entry(priv->pgtable, iova); | |
849 | ||
850 | if (lv1ent_section(ent)) { | |
851 | BUG_ON(size < SECT_SIZE); | |
852 | ||
853 | *ent = 0; | |
854 | pgtable_flush(ent, ent + 1); | |
855 | size = SECT_SIZE; | |
856 | goto done; | |
857 | } | |
858 | ||
859 | if (unlikely(lv1ent_fault(ent))) { | |
860 | if (size > SECT_SIZE) | |
861 | size = SECT_SIZE; | |
862 | goto done; | |
863 | } | |
864 | ||
865 | /* lv1ent_page(sent) == true here */ | |
866 | ||
867 | ent = page_entry(ent, iova); | |
868 | ||
869 | if (unlikely(lv2ent_fault(ent))) { | |
870 | size = SPAGE_SIZE; | |
871 | goto done; | |
872 | } | |
873 | ||
874 | if (lv2ent_small(ent)) { | |
875 | *ent = 0; | |
876 | size = SPAGE_SIZE; | |
877 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; | |
878 | goto done; | |
879 | } | |
880 | ||
881 | /* lv1ent_large(ent) == true here */ | |
882 | BUG_ON(size < LPAGE_SIZE); | |
883 | ||
884 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
885 | ||
886 | size = LPAGE_SIZE; | |
887 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
888 | done: | |
889 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
890 | ||
891 | spin_lock_irqsave(&priv->lock, flags); | |
892 | list_for_each_entry(data, &priv->clients, node) | |
893 | sysmmu_tlb_invalidate_entry(data->dev, iova); | |
894 | spin_unlock_irqrestore(&priv->lock, flags); | |
895 | ||
896 | ||
897 | return size; | |
898 | } | |
899 | ||
900 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 901 | dma_addr_t iova) |
2a96536e KC |
902 | { |
903 | struct exynos_iommu_domain *priv = domain->priv; | |
904 | unsigned long *entry; | |
905 | unsigned long flags; | |
906 | phys_addr_t phys = 0; | |
907 | ||
908 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
909 | ||
910 | entry = section_entry(priv->pgtable, iova); | |
911 | ||
912 | if (lv1ent_section(entry)) { | |
913 | phys = section_phys(entry) + section_offs(iova); | |
914 | } else if (lv1ent_page(entry)) { | |
915 | entry = page_entry(entry, iova); | |
916 | ||
917 | if (lv2ent_large(entry)) | |
918 | phys = lpage_phys(entry) + lpage_offs(iova); | |
919 | else if (lv2ent_small(entry)) | |
920 | phys = spage_phys(entry) + spage_offs(iova); | |
921 | } | |
922 | ||
923 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
924 | ||
925 | return phys; | |
926 | } | |
927 | ||
928 | static struct iommu_ops exynos_iommu_ops = { | |
929 | .domain_init = &exynos_iommu_domain_init, | |
930 | .domain_destroy = &exynos_iommu_domain_destroy, | |
931 | .attach_dev = &exynos_iommu_attach_device, | |
932 | .detach_dev = &exynos_iommu_detach_device, | |
933 | .map = &exynos_iommu_map, | |
934 | .unmap = &exynos_iommu_unmap, | |
935 | .iova_to_phys = &exynos_iommu_iova_to_phys, | |
936 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, | |
937 | }; | |
938 | ||
939 | static int __init exynos_iommu_init(void) | |
940 | { | |
941 | int ret; | |
942 | ||
943 | ret = platform_driver_register(&exynos_sysmmu_driver); | |
944 | ||
945 | if (ret == 0) | |
946 | bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); | |
947 | ||
948 | return ret; | |
949 | } | |
950 | subsys_initcall(exynos_iommu_init); |