Commit | Line | Data |
---|---|---|
740a01ee MS |
1 | /* |
2 | * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. | |
2a96536e KC |
3 | * http://www.samsung.com |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
11 | #define DEBUG | |
12 | #endif | |
13 | ||
2a96536e | 14 | #include <linux/clk.h> |
8ed55c81 | 15 | #include <linux/dma-mapping.h> |
2a96536e | 16 | #include <linux/err.h> |
312900c6 | 17 | #include <linux/io.h> |
2a96536e | 18 | #include <linux/iommu.h> |
312900c6 | 19 | #include <linux/interrupt.h> |
514c6032 | 20 | #include <linux/kmemleak.h> |
2a96536e | 21 | #include <linux/list.h> |
8ed55c81 MS |
22 | #include <linux/of.h> |
23 | #include <linux/of_iommu.h> | |
24 | #include <linux/of_platform.h> | |
312900c6 MS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
58c6f6a3 | 28 | #include <linux/dma-iommu.h> |
2a96536e | 29 | |
d09d78fc CK |
30 | typedef u32 sysmmu_iova_t; |
31 | typedef u32 sysmmu_pte_t; | |
32 | ||
f171abab | 33 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
34 | #define SECT_ORDER 20 |
35 | #define LPAGE_ORDER 16 | |
36 | #define SPAGE_ORDER 12 | |
37 | ||
38 | #define SECT_SIZE (1 << SECT_ORDER) | |
39 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
40 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
41 | ||
42 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
43 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
44 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
45 | ||
66a7ed84 CK |
46 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
47 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
48 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
49 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
50 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
51 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
52 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
53 | ||
54 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
55 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
56 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
57 | ||
740a01ee MS |
58 | /* |
59 | * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces | |
60 | * v5.0 introduced support for 36bit physical address space by shifting | |
61 | * all page entry values by 4 bits. | |
62 | * All SYSMMU controllers in the system support the address spaces of the same | |
63 | * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper | |
64 | * value (0 or 4). | |
65 | */ | |
66 | static short PG_ENT_SHIFT = -1; | |
67 | #define SYSMMU_PG_ENT_SHIFT 0 | |
68 | #define SYSMMU_V5_PG_ENT_SHIFT 4 | |
69 | ||
1a0d8dac MS |
70 | static const sysmmu_pte_t *LV1_PROT; |
71 | static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { | |
72 | ((0 << 15) | (0 << 10)), /* no access */ | |
73 | ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ | |
74 | ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ | |
75 | ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ | |
76 | }; | |
77 | static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { | |
78 | (0 << 4), /* no access */ | |
79 | (1 << 4), /* IOMMU_READ only */ | |
80 | (2 << 4), /* IOMMU_WRITE only */ | |
81 | (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ | |
82 | }; | |
83 | ||
84 | static const sysmmu_pte_t *LV2_PROT; | |
85 | static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { | |
86 | ((0 << 9) | (0 << 4)), /* no access */ | |
87 | ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ | |
88 | ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ | |
89 | ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ | |
90 | }; | |
91 | static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { | |
92 | (0 << 2), /* no access */ | |
93 | (1 << 2), /* IOMMU_READ only */ | |
94 | (2 << 2), /* IOMMU_WRITE only */ | |
95 | (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ | |
96 | }; | |
97 | ||
98 | #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) | |
99 | ||
740a01ee MS |
100 | #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) |
101 | #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) | |
102 | #define section_offs(iova) (iova & (SECT_SIZE - 1)) | |
103 | #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) | |
104 | #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) | |
105 | #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) | |
106 | #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) | |
2a96536e KC |
107 | |
108 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 109 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 110 | |
d09d78fc CK |
111 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
112 | { | |
113 | return iova >> SECT_ORDER; | |
114 | } | |
115 | ||
116 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
117 | { | |
118 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
119 | } | |
120 | ||
5e3435eb | 121 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 122 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
123 | |
124 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
740a01ee | 125 | #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) |
2a96536e | 126 | |
1a0d8dac | 127 | #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) |
740a01ee | 128 | #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) |
1a0d8dac MS |
129 | #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) |
130 | #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) | |
2a96536e KC |
131 | |
132 | #define CTRL_ENABLE 0x5 | |
133 | #define CTRL_BLOCK 0x7 | |
134 | #define CTRL_DISABLE 0x0 | |
135 | ||
eeb5184b | 136 | #define CFG_LRU 0x1 |
1a0d8dac | 137 | #define CFG_EAP (1 << 2) |
eeb5184b | 138 | #define CFG_QOS(n) ((n & 0xF) << 7) |
eeb5184b CK |
139 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ |
140 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
141 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
142 | ||
740a01ee | 143 | /* common registers */ |
2a96536e KC |
144 | #define REG_MMU_CTRL 0x000 |
145 | #define REG_MMU_CFG 0x004 | |
146 | #define REG_MMU_STATUS 0x008 | |
740a01ee MS |
147 | #define REG_MMU_VERSION 0x034 |
148 | ||
149 | #define MMU_MAJ_VER(val) ((val) >> 7) | |
150 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
151 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
152 | ||
153 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
154 | ||
155 | /* v1.x - v3.x registers */ | |
2a96536e KC |
156 | #define REG_MMU_FLUSH 0x00C |
157 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
158 | #define REG_PT_BASE_ADDR 0x014 | |
159 | #define REG_INT_STATUS 0x018 | |
160 | #define REG_INT_CLEAR 0x01C | |
161 | ||
162 | #define REG_PAGE_FAULT_ADDR 0x024 | |
163 | #define REG_AW_FAULT_ADDR 0x028 | |
164 | #define REG_AR_FAULT_ADDR 0x02C | |
165 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
166 | ||
740a01ee MS |
167 | /* v5.x registers */ |
168 | #define REG_V5_PT_BASE_PFN 0x00C | |
169 | #define REG_V5_MMU_FLUSH_ALL 0x010 | |
170 | #define REG_V5_MMU_FLUSH_ENTRY 0x014 | |
d5bf739d MS |
171 | #define REG_V5_MMU_FLUSH_RANGE 0x018 |
172 | #define REG_V5_MMU_FLUSH_START 0x020 | |
173 | #define REG_V5_MMU_FLUSH_END 0x024 | |
740a01ee MS |
174 | #define REG_V5_INT_STATUS 0x060 |
175 | #define REG_V5_INT_CLEAR 0x064 | |
176 | #define REG_V5_FAULT_AR_VA 0x070 | |
177 | #define REG_V5_FAULT_AW_VA 0x080 | |
2a96536e | 178 | |
6b21a5db CK |
179 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
180 | ||
5e3435eb | 181 | static struct device *dma_dev; |
734c3c73 | 182 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
183 | static sysmmu_pte_t *zero_lv2_table; |
184 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 185 | |
d09d78fc | 186 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
187 | { |
188 | return pgtable + lv1ent_offset(iova); | |
189 | } | |
190 | ||
d09d78fc | 191 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 192 | { |
d09d78fc | 193 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 194 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
195 | } |
196 | ||
d093fc7e MS |
197 | /* |
198 | * IOMMU fault information register | |
199 | */ | |
200 | struct sysmmu_fault_info { | |
201 | unsigned int bit; /* bit number in STATUS register */ | |
202 | unsigned short addr_reg; /* register to read VA fault address */ | |
203 | const char *name; /* human readable fault name */ | |
204 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
205 | }; |
206 | ||
d093fc7e MS |
207 | static const struct sysmmu_fault_info sysmmu_faults[] = { |
208 | { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
209 | { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
210 | { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
211 | { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
212 | { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
213 | { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
214 | { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
215 | { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
216 | }; |
217 | ||
740a01ee MS |
218 | static const struct sysmmu_fault_info sysmmu_v5_faults[] = { |
219 | { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ }, | |
220 | { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ }, | |
221 | { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
222 | { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
223 | { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
224 | { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE }, | |
225 | { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE }, | |
226 | { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
227 | { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
228 | { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
229 | }; | |
230 | ||
2860af3c MS |
231 | /* |
232 | * This structure is attached to dev.archdata.iommu of the master device | |
233 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
234 | * which are bound to given master device. It is usually referenced by 'owner' | |
235 | * pointer. | |
236 | */ | |
6b21a5db | 237 | struct exynos_iommu_owner { |
1b092054 | 238 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
5fa61cbf | 239 | struct iommu_domain *domain; /* domain this device is attached */ |
9b265536 | 240 | struct mutex rpm_lock; /* for runtime pm of all sysmmus */ |
6b21a5db CK |
241 | }; |
242 | ||
2860af3c MS |
243 | /* |
244 | * This structure exynos specific generalization of struct iommu_domain. | |
245 | * It contains list of SYSMMU controllers from all master devices, which has | |
246 | * been attached to this domain and page tables of IO address space defined by | |
247 | * it. It is usually referenced by 'domain' pointer. | |
248 | */ | |
2a96536e | 249 | struct exynos_iommu_domain { |
2860af3c MS |
250 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
251 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
252 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
253 | spinlock_t lock; /* lock for modyfying list of clients */ | |
254 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 255 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
256 | }; |
257 | ||
2860af3c MS |
258 | /* |
259 | * This structure hold all data of a single SYSMMU controller, this includes | |
260 | * hw resources like registers and clocks, pointers and list nodes to connect | |
261 | * it to all other structures, internal state and parameters read from device | |
262 | * tree. It is usually referenced by 'data' pointer. | |
263 | */ | |
2a96536e | 264 | struct sysmmu_drvdata { |
2860af3c MS |
265 | struct device *sysmmu; /* SYSMMU controller device */ |
266 | struct device *master; /* master device (owner) */ | |
7a974b29 | 267 | struct device_link *link; /* runtime PM link to master */ |
2860af3c MS |
268 | void __iomem *sfrbase; /* our registers */ |
269 | struct clk *clk; /* SYSMMU's clock */ | |
740a01ee MS |
270 | struct clk *aclk; /* SYSMMU's aclk clock */ |
271 | struct clk *pclk; /* SYSMMU's pclk clock */ | |
2860af3c | 272 | struct clk *clk_master; /* master's device clock */ |
2860af3c | 273 | spinlock_t lock; /* lock for modyfying state */ |
47a574ff | 274 | bool active; /* current status */ |
2860af3c MS |
275 | struct exynos_iommu_domain *domain; /* domain we belong to */ |
276 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 277 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
278 | phys_addr_t pgtable; /* assigned page table structure */ |
279 | unsigned int version; /* our version */ | |
d2c302b6 JR |
280 | |
281 | struct iommu_device iommu; /* IOMMU core handle */ | |
2a96536e KC |
282 | }; |
283 | ||
e1fd1eaa JR |
284 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
285 | { | |
286 | return container_of(dom, struct exynos_iommu_domain, domain); | |
287 | } | |
288 | ||
02cdc365 | 289 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 290 | { |
84bd0428 | 291 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
292 | } |
293 | ||
02cdc365 | 294 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
295 | { |
296 | int i = 120; | |
297 | ||
84bd0428 MS |
298 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
299 | while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
300 | --i; |
301 | ||
84bd0428 | 302 | if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
02cdc365 | 303 | sysmmu_unblock(data); |
2a96536e KC |
304 | return false; |
305 | } | |
306 | ||
307 | return true; | |
308 | } | |
309 | ||
02cdc365 | 310 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 311 | { |
740a01ee | 312 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 313 | writel(0x1, data->sfrbase + REG_MMU_FLUSH); |
740a01ee | 314 | else |
84bd0428 | 315 | writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); |
2a96536e KC |
316 | } |
317 | ||
02cdc365 | 318 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 319 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 320 | { |
3ad6b7f3 | 321 | unsigned int i; |
365409db | 322 | |
d5bf739d MS |
323 | if (MMU_MAJ_VER(data->version) < 5) { |
324 | for (i = 0; i < num_inv; i++) { | |
84bd0428 | 325 | writel((iova & SPAGE_MASK) | 1, |
740a01ee | 326 | data->sfrbase + REG_MMU_FLUSH_ENTRY); |
d5bf739d MS |
327 | iova += SPAGE_SIZE; |
328 | } | |
329 | } else { | |
330 | if (num_inv == 1) { | |
84bd0428 | 331 | writel((iova & SPAGE_MASK) | 1, |
740a01ee | 332 | data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); |
d5bf739d MS |
333 | } else { |
334 | writel((iova & SPAGE_MASK), | |
335 | data->sfrbase + REG_V5_MMU_FLUSH_START); | |
336 | writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, | |
337 | data->sfrbase + REG_V5_MMU_FLUSH_END); | |
338 | writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); | |
339 | } | |
3ad6b7f3 | 340 | } |
2a96536e KC |
341 | } |
342 | ||
02cdc365 | 343 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 344 | { |
740a01ee | 345 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 346 | writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); |
740a01ee | 347 | else |
84bd0428 | 348 | writel(pgd >> PAGE_SHIFT, |
740a01ee | 349 | data->sfrbase + REG_V5_PT_BASE_PFN); |
2a96536e | 350 | |
02cdc365 | 351 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
352 | } |
353 | ||
fecc49db MS |
354 | static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) |
355 | { | |
356 | BUG_ON(clk_prepare_enable(data->clk_master)); | |
357 | BUG_ON(clk_prepare_enable(data->clk)); | |
358 | BUG_ON(clk_prepare_enable(data->pclk)); | |
359 | BUG_ON(clk_prepare_enable(data->aclk)); | |
360 | } | |
361 | ||
362 | static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) | |
363 | { | |
364 | clk_disable_unprepare(data->aclk); | |
365 | clk_disable_unprepare(data->pclk); | |
366 | clk_disable_unprepare(data->clk); | |
367 | clk_disable_unprepare(data->clk_master); | |
368 | } | |
369 | ||
850d313e MS |
370 | static void __sysmmu_get_version(struct sysmmu_drvdata *data) |
371 | { | |
372 | u32 ver; | |
373 | ||
fecc49db | 374 | __sysmmu_enable_clocks(data); |
850d313e | 375 | |
84bd0428 | 376 | ver = readl(data->sfrbase + REG_MMU_VERSION); |
850d313e MS |
377 | |
378 | /* controllers on some SoCs don't report proper version */ | |
379 | if (ver == 0x80000001u) | |
380 | data->version = MAKE_MMU_VER(1, 0); | |
381 | else | |
382 | data->version = MMU_RAW_VER(ver); | |
383 | ||
384 | dev_dbg(data->sysmmu, "hardware version: %d.%d\n", | |
385 | MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); | |
386 | ||
fecc49db | 387 | __sysmmu_disable_clocks(data); |
850d313e MS |
388 | } |
389 | ||
d093fc7e MS |
390 | static void show_fault_information(struct sysmmu_drvdata *data, |
391 | const struct sysmmu_fault_info *finfo, | |
392 | sysmmu_iova_t fault_addr) | |
2a96536e | 393 | { |
d09d78fc | 394 | sysmmu_pte_t *ent; |
2a96536e | 395 | |
ec5d241b MS |
396 | dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n", |
397 | dev_name(data->master), finfo->name, fault_addr); | |
398 | dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); | |
d093fc7e | 399 | ent = section_entry(phys_to_virt(data->pgtable), fault_addr); |
ec5d241b | 400 | dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
401 | if (lv1ent_page(ent)) { |
402 | ent = page_entry(ent, fault_addr); | |
ec5d241b | 403 | dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 404 | } |
2a96536e KC |
405 | } |
406 | ||
407 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
408 | { | |
f171abab | 409 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 410 | struct sysmmu_drvdata *data = dev_id; |
740a01ee MS |
411 | const struct sysmmu_fault_info *finfo; |
412 | unsigned int i, n, itype; | |
d093fc7e | 413 | sysmmu_iova_t fault_addr = -1; |
740a01ee | 414 | unsigned short reg_status, reg_clear; |
7222e8db | 415 | int ret = -ENOSYS; |
2a96536e | 416 | |
47a574ff | 417 | WARN_ON(!data->active); |
2a96536e | 418 | |
740a01ee MS |
419 | if (MMU_MAJ_VER(data->version) < 5) { |
420 | reg_status = REG_INT_STATUS; | |
421 | reg_clear = REG_INT_CLEAR; | |
422 | finfo = sysmmu_faults; | |
423 | n = ARRAY_SIZE(sysmmu_faults); | |
424 | } else { | |
425 | reg_status = REG_V5_INT_STATUS; | |
426 | reg_clear = REG_V5_INT_CLEAR; | |
427 | finfo = sysmmu_v5_faults; | |
428 | n = ARRAY_SIZE(sysmmu_v5_faults); | |
429 | } | |
430 | ||
9d4e7a24 CK |
431 | spin_lock(&data->lock); |
432 | ||
b398af21 | 433 | clk_enable(data->clk_master); |
9d4e7a24 | 434 | |
84bd0428 | 435 | itype = __ffs(readl(data->sfrbase + reg_status)); |
d093fc7e MS |
436 | for (i = 0; i < n; i++, finfo++) |
437 | if (finfo->bit == itype) | |
438 | break; | |
439 | /* unknown/unsupported fault */ | |
440 | BUG_ON(i == n); | |
441 | ||
442 | /* print debug message */ | |
84bd0428 | 443 | fault_addr = readl(data->sfrbase + finfo->addr_reg); |
d093fc7e | 444 | show_fault_information(data, finfo, fault_addr); |
2a96536e | 445 | |
d093fc7e MS |
446 | if (data->domain) |
447 | ret = report_iommu_fault(&data->domain->domain, | |
448 | data->master, fault_addr, finfo->type); | |
1fab7fa7 CK |
449 | /* fault is not recovered by fault handler */ |
450 | BUG_ON(ret != 0); | |
2a96536e | 451 | |
84bd0428 | 452 | writel(1 << itype, data->sfrbase + reg_clear); |
1fab7fa7 | 453 | |
02cdc365 | 454 | sysmmu_unblock(data); |
2a96536e | 455 | |
b398af21 | 456 | clk_disable(data->clk_master); |
70605870 | 457 | |
9d4e7a24 | 458 | spin_unlock(&data->lock); |
2a96536e KC |
459 | |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | ||
47a574ff | 463 | static void __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 464 | { |
47a574ff MS |
465 | unsigned long flags; |
466 | ||
b398af21 | 467 | clk_enable(data->clk_master); |
70605870 | 468 | |
47a574ff | 469 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 MS |
470 | writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
471 | writel(0, data->sfrbase + REG_MMU_CFG); | |
47a574ff | 472 | data->active = false; |
6b21a5db CK |
473 | spin_unlock_irqrestore(&data->lock, flags); |
474 | ||
47a574ff | 475 | __sysmmu_disable_clocks(data); |
6b21a5db | 476 | } |
2a96536e | 477 | |
6b21a5db CK |
478 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
479 | { | |
83addecd MS |
480 | unsigned int cfg; |
481 | ||
83addecd MS |
482 | if (data->version <= MAKE_MMU_VER(3, 1)) |
483 | cfg = CFG_LRU | CFG_QOS(15); | |
484 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
485 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
486 | else | |
487 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db | 488 | |
1a0d8dac MS |
489 | cfg |= CFG_EAP; /* enable access protection bits check */ |
490 | ||
84bd0428 | 491 | writel(cfg, data->sfrbase + REG_MMU_CFG); |
6b21a5db CK |
492 | } |
493 | ||
47a574ff | 494 | static void __sysmmu_enable(struct sysmmu_drvdata *data) |
6b21a5db | 495 | { |
47a574ff MS |
496 | unsigned long flags; |
497 | ||
fecc49db | 498 | __sysmmu_enable_clocks(data); |
70605870 | 499 | |
47a574ff | 500 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 | 501 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 502 | __sysmmu_init_config(data); |
02cdc365 | 503 | __sysmmu_set_ptbase(data, data->pgtable); |
84bd0428 | 504 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
47a574ff MS |
505 | data->active = true; |
506 | spin_unlock_irqrestore(&data->lock, flags); | |
7222e8db | 507 | |
fecc49db MS |
508 | /* |
509 | * SYSMMU driver keeps master's clock enabled only for the short | |
510 | * time, while accessing the registers. For performing address | |
511 | * translation during DMA transaction it relies on the client | |
512 | * driver to enable it. | |
513 | */ | |
b398af21 | 514 | clk_disable(data->clk_master); |
6b21a5db | 515 | } |
70605870 | 516 | |
469acebe | 517 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
518 | sysmmu_iova_t iova) |
519 | { | |
520 | unsigned long flags; | |
66a7ed84 | 521 | |
66a7ed84 | 522 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 523 | if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { |
01324ab2 | 524 | clk_enable(data->clk_master); |
7d2aa6b8 | 525 | if (sysmmu_block(data)) { |
cd37a296 MS |
526 | if (data->version >= MAKE_MMU_VER(5, 0)) |
527 | __sysmmu_tlb_invalidate(data); | |
528 | else | |
529 | __sysmmu_tlb_invalidate_entry(data, iova, 1); | |
7d2aa6b8 MS |
530 | sysmmu_unblock(data); |
531 | } | |
01324ab2 | 532 | clk_disable(data->clk_master); |
d631ea98 | 533 | } |
66a7ed84 | 534 | spin_unlock_irqrestore(&data->lock, flags); |
66a7ed84 CK |
535 | } |
536 | ||
469acebe MS |
537 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
538 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
539 | { |
540 | unsigned long flags; | |
2a96536e | 541 | |
6b21a5db | 542 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 543 | if (data->active) { |
3ad6b7f3 | 544 | unsigned int num_inv = 1; |
70605870 | 545 | |
b398af21 | 546 | clk_enable(data->clk_master); |
70605870 | 547 | |
3ad6b7f3 CK |
548 | /* |
549 | * L2TLB invalidation required | |
550 | * 4KB page: 1 invalidation | |
f171abab SK |
551 | * 64KB page: 16 invalidations |
552 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
553 | * because it is set-associative TLB |
554 | * with 8-way and 64 sets. | |
555 | * 1MB page can be cached in one of all sets. | |
556 | * 64KB page can be one of 16 consecutive sets. | |
557 | */ | |
512bd0c6 | 558 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
559 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
560 | ||
02cdc365 MS |
561 | if (sysmmu_block(data)) { |
562 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
563 | sysmmu_unblock(data); | |
2a96536e | 564 | } |
b398af21 | 565 | clk_disable(data->clk_master); |
2a96536e | 566 | } |
9d4e7a24 | 567 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
568 | } |
569 | ||
0b9a3694 | 570 | static const struct iommu_ops exynos_iommu_ops; |
96f66557 | 571 | |
6b21a5db | 572 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 573 | { |
46c16d1e | 574 | int irq, ret; |
7222e8db | 575 | struct device *dev = &pdev->dev; |
2a96536e | 576 | struct sysmmu_drvdata *data; |
7222e8db | 577 | struct resource *res; |
2a96536e | 578 | |
46c16d1e CK |
579 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
580 | if (!data) | |
581 | return -ENOMEM; | |
2a96536e | 582 | |
7222e8db | 583 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
584 | data->sfrbase = devm_ioremap_resource(dev, res); |
585 | if (IS_ERR(data->sfrbase)) | |
586 | return PTR_ERR(data->sfrbase); | |
2a96536e | 587 | |
46c16d1e CK |
588 | irq = platform_get_irq(pdev, 0); |
589 | if (irq <= 0) { | |
0bf4e54d | 590 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 591 | return irq; |
2a96536e KC |
592 | } |
593 | ||
46c16d1e | 594 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
595 | dev_name(dev), data); |
596 | if (ret) { | |
46c16d1e CK |
597 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
598 | return ret; | |
2a96536e KC |
599 | } |
600 | ||
46c16d1e | 601 | data->clk = devm_clk_get(dev, "sysmmu"); |
0c2b063f | 602 | if (PTR_ERR(data->clk) == -ENOENT) |
740a01ee | 603 | data->clk = NULL; |
0c2b063f MS |
604 | else if (IS_ERR(data->clk)) |
605 | return PTR_ERR(data->clk); | |
740a01ee MS |
606 | |
607 | data->aclk = devm_clk_get(dev, "aclk"); | |
0c2b063f | 608 | if (PTR_ERR(data->aclk) == -ENOENT) |
740a01ee | 609 | data->aclk = NULL; |
0c2b063f MS |
610 | else if (IS_ERR(data->aclk)) |
611 | return PTR_ERR(data->aclk); | |
740a01ee MS |
612 | |
613 | data->pclk = devm_clk_get(dev, "pclk"); | |
0c2b063f | 614 | if (PTR_ERR(data->pclk) == -ENOENT) |
740a01ee | 615 | data->pclk = NULL; |
0c2b063f MS |
616 | else if (IS_ERR(data->pclk)) |
617 | return PTR_ERR(data->pclk); | |
740a01ee MS |
618 | |
619 | if (!data->clk && (!data->aclk || !data->pclk)) { | |
620 | dev_err(dev, "Failed to get device clock(s)!\n"); | |
621 | return -ENOSYS; | |
2a96536e KC |
622 | } |
623 | ||
70605870 | 624 | data->clk_master = devm_clk_get(dev, "master"); |
0c2b063f | 625 | if (PTR_ERR(data->clk_master) == -ENOENT) |
b398af21 | 626 | data->clk_master = NULL; |
0c2b063f MS |
627 | else if (IS_ERR(data->clk_master)) |
628 | return PTR_ERR(data->clk_master); | |
70605870 | 629 | |
2a96536e | 630 | data->sysmmu = dev; |
9d4e7a24 | 631 | spin_lock_init(&data->lock); |
2a96536e | 632 | |
d2c302b6 JR |
633 | ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, |
634 | dev_name(data->sysmmu)); | |
635 | if (ret) | |
636 | return ret; | |
637 | ||
638 | iommu_device_set_ops(&data->iommu, &exynos_iommu_ops); | |
639 | iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode); | |
640 | ||
641 | ret = iommu_device_register(&data->iommu); | |
642 | if (ret) | |
643 | return ret; | |
644 | ||
7222e8db CK |
645 | platform_set_drvdata(pdev, data); |
646 | ||
850d313e | 647 | __sysmmu_get_version(data); |
740a01ee | 648 | if (PG_ENT_SHIFT < 0) { |
1a0d8dac | 649 | if (MMU_MAJ_VER(data->version) < 5) { |
740a01ee | 650 | PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; |
1a0d8dac MS |
651 | LV1_PROT = SYSMMU_LV1_PROT; |
652 | LV2_PROT = SYSMMU_LV2_PROT; | |
653 | } else { | |
740a01ee | 654 | PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; |
1a0d8dac MS |
655 | LV1_PROT = SYSMMU_V5_LV1_PROT; |
656 | LV2_PROT = SYSMMU_V5_LV2_PROT; | |
657 | } | |
740a01ee MS |
658 | } |
659 | ||
928055a0 MS |
660 | /* |
661 | * use the first registered sysmmu device for performing | |
662 | * dma mapping operations on iommu page tables (cpu cache flush) | |
663 | */ | |
664 | if (!dma_dev) | |
665 | dma_dev = &pdev->dev; | |
666 | ||
f4723ec1 | 667 | pm_runtime_enable(dev); |
2a96536e | 668 | |
2a96536e | 669 | return 0; |
2a96536e KC |
670 | } |
671 | ||
9b265536 | 672 | static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) |
622015e4 MS |
673 | { |
674 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 675 | struct device *master = data->master; |
622015e4 | 676 | |
47a574ff | 677 | if (master) { |
9b265536 MS |
678 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
679 | ||
680 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
681 | if (data->domain) { |
682 | dev_dbg(data->sysmmu, "saving state\n"); | |
683 | __sysmmu_disable(data); | |
684 | } | |
9b265536 | 685 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
686 | } |
687 | return 0; | |
688 | } | |
689 | ||
9b265536 | 690 | static int __maybe_unused exynos_sysmmu_resume(struct device *dev) |
622015e4 MS |
691 | { |
692 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 693 | struct device *master = data->master; |
622015e4 | 694 | |
47a574ff | 695 | if (master) { |
9b265536 MS |
696 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
697 | ||
698 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
699 | if (data->domain) { |
700 | dev_dbg(data->sysmmu, "restoring state\n"); | |
701 | __sysmmu_enable(data); | |
702 | } | |
9b265536 | 703 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
704 | } |
705 | return 0; | |
706 | } | |
622015e4 MS |
707 | |
708 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
9b265536 | 709 | SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) |
2f5f44f2 MS |
710 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
711 | pm_runtime_force_resume) | |
622015e4 MS |
712 | }; |
713 | ||
9d25e3cc | 714 | static const struct of_device_id sysmmu_of_match[] = { |
6b21a5db CK |
715 | { .compatible = "samsung,exynos-sysmmu", }, |
716 | { }, | |
717 | }; | |
718 | ||
719 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
720 | .probe = exynos_sysmmu_probe, | |
721 | .driver = { | |
2a96536e | 722 | .name = "exynos-sysmmu", |
6b21a5db | 723 | .of_match_table = sysmmu_of_match, |
622015e4 | 724 | .pm = &sysmmu_pm_ops, |
b54b874f | 725 | .suppress_bind_attrs = true, |
2a96536e KC |
726 | } |
727 | }; | |
728 | ||
5e3435eb | 729 | static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 730 | { |
5e3435eb MS |
731 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
732 | DMA_TO_DEVICE); | |
6ae5343c | 733 | *ent = cpu_to_le32(val); |
5e3435eb MS |
734 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), |
735 | DMA_TO_DEVICE); | |
2a96536e KC |
736 | } |
737 | ||
e1fd1eaa | 738 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 739 | { |
bfa00489 | 740 | struct exynos_iommu_domain *domain; |
5e3435eb | 741 | dma_addr_t handle; |
66a7ed84 | 742 | int i; |
2a96536e | 743 | |
740a01ee MS |
744 | /* Check if correct PTE offsets are initialized */ |
745 | BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); | |
e1fd1eaa | 746 | |
bfa00489 MS |
747 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
748 | if (!domain) | |
e1fd1eaa | 749 | return NULL; |
2a96536e | 750 | |
58c6f6a3 MS |
751 | if (type == IOMMU_DOMAIN_DMA) { |
752 | if (iommu_get_dma_cookie(&domain->domain) != 0) | |
753 | goto err_pgtable; | |
754 | } else if (type != IOMMU_DOMAIN_UNMANAGED) { | |
755 | goto err_pgtable; | |
756 | } | |
757 | ||
bfa00489 MS |
758 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
759 | if (!domain->pgtable) | |
58c6f6a3 | 760 | goto err_dma_cookie; |
2a96536e | 761 | |
bfa00489 MS |
762 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
763 | if (!domain->lv2entcnt) | |
2a96536e KC |
764 | goto err_counter; |
765 | ||
f171abab | 766 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
e7527663 MS |
767 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
768 | domain->pgtable[i] = ZERO_LV2LINK; | |
66a7ed84 | 769 | |
5e3435eb MS |
770 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
771 | DMA_TO_DEVICE); | |
772 | /* For mapping page table entries we rely on dma == phys */ | |
773 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
0d6d3da4 MS |
774 | if (dma_mapping_error(dma_dev, handle)) |
775 | goto err_lv2ent; | |
2a96536e | 776 | |
bfa00489 MS |
777 | spin_lock_init(&domain->lock); |
778 | spin_lock_init(&domain->pgtablelock); | |
779 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 780 | |
bfa00489 MS |
781 | domain->domain.geometry.aperture_start = 0; |
782 | domain->domain.geometry.aperture_end = ~0UL; | |
783 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 784 | |
bfa00489 | 785 | return &domain->domain; |
2a96536e | 786 | |
0d6d3da4 MS |
787 | err_lv2ent: |
788 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
2a96536e | 789 | err_counter: |
bfa00489 | 790 | free_pages((unsigned long)domain->pgtable, 2); |
58c6f6a3 MS |
791 | err_dma_cookie: |
792 | if (type == IOMMU_DOMAIN_DMA) | |
793 | iommu_put_dma_cookie(&domain->domain); | |
2a96536e | 794 | err_pgtable: |
bfa00489 | 795 | kfree(domain); |
e1fd1eaa | 796 | return NULL; |
2a96536e KC |
797 | } |
798 | ||
bfa00489 | 799 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 800 | { |
bfa00489 | 801 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 802 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
803 | unsigned long flags; |
804 | int i; | |
805 | ||
bfa00489 | 806 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 807 | |
bfa00489 | 808 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 809 | |
bfa00489 | 810 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
e1172300 | 811 | spin_lock(&data->lock); |
b0d4c861 | 812 | __sysmmu_disable(data); |
47a574ff MS |
813 | data->pgtable = 0; |
814 | data->domain = NULL; | |
469acebe | 815 | list_del_init(&data->domain_node); |
e1172300 | 816 | spin_unlock(&data->lock); |
2a96536e KC |
817 | } |
818 | ||
bfa00489 | 819 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 820 | |
58c6f6a3 MS |
821 | if (iommu_domain->type == IOMMU_DOMAIN_DMA) |
822 | iommu_put_dma_cookie(iommu_domain); | |
823 | ||
5e3435eb MS |
824 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
825 | DMA_TO_DEVICE); | |
826 | ||
2a96536e | 827 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
828 | if (lv1ent_page(domain->pgtable + i)) { |
829 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
830 | ||
831 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
832 | DMA_TO_DEVICE); | |
734c3c73 | 833 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
834 | phys_to_virt(base)); |
835 | } | |
2a96536e | 836 | |
bfa00489 MS |
837 | free_pages((unsigned long)domain->pgtable, 2); |
838 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
839 | kfree(domain); | |
2a96536e KC |
840 | } |
841 | ||
5fa61cbf MS |
842 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
843 | struct device *dev) | |
844 | { | |
845 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
846 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); | |
847 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
848 | struct sysmmu_drvdata *data, *next; | |
849 | unsigned long flags; | |
5fa61cbf MS |
850 | |
851 | if (!has_sysmmu(dev) || owner->domain != iommu_domain) | |
852 | return; | |
853 | ||
9b265536 MS |
854 | mutex_lock(&owner->rpm_lock); |
855 | ||
856 | list_for_each_entry(data, &owner->controllers, owner_node) { | |
857 | pm_runtime_get_noresume(data->sysmmu); | |
858 | if (pm_runtime_active(data->sysmmu)) | |
859 | __sysmmu_disable(data); | |
e1172300 MS |
860 | pm_runtime_put(data->sysmmu); |
861 | } | |
862 | ||
5fa61cbf MS |
863 | spin_lock_irqsave(&domain->lock, flags); |
864 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { | |
e1172300 | 865 | spin_lock(&data->lock); |
47a574ff MS |
866 | data->pgtable = 0; |
867 | data->domain = NULL; | |
b0d4c861 | 868 | list_del_init(&data->domain_node); |
e1172300 | 869 | spin_unlock(&data->lock); |
5fa61cbf | 870 | } |
e1172300 | 871 | owner->domain = NULL; |
5fa61cbf MS |
872 | spin_unlock_irqrestore(&domain->lock, flags); |
873 | ||
9b265536 | 874 | mutex_unlock(&owner->rpm_lock); |
5fa61cbf | 875 | |
b0d4c861 MS |
876 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, |
877 | &pagetable); | |
5fa61cbf MS |
878 | } |
879 | ||
bfa00489 | 880 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
881 | struct device *dev) |
882 | { | |
6b21a5db | 883 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 884 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 885 | struct sysmmu_drvdata *data; |
bfa00489 | 886 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 887 | unsigned long flags; |
2a96536e | 888 | |
469acebe MS |
889 | if (!has_sysmmu(dev)) |
890 | return -ENODEV; | |
2a96536e | 891 | |
5fa61cbf MS |
892 | if (owner->domain) |
893 | exynos_iommu_detach_device(owner->domain, dev); | |
894 | ||
9b265536 MS |
895 | mutex_lock(&owner->rpm_lock); |
896 | ||
e1172300 | 897 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 898 | list_for_each_entry(data, &owner->controllers, owner_node) { |
e1172300 | 899 | spin_lock(&data->lock); |
47a574ff MS |
900 | data->pgtable = pagetable; |
901 | data->domain = domain; | |
e1172300 MS |
902 | list_add_tail(&data->domain_node, &domain->clients); |
903 | spin_unlock(&data->lock); | |
904 | } | |
905 | owner->domain = iommu_domain; | |
906 | spin_unlock_irqrestore(&domain->lock, flags); | |
907 | ||
9b265536 MS |
908 | list_for_each_entry(data, &owner->controllers, owner_node) { |
909 | pm_runtime_get_noresume(data->sysmmu); | |
910 | if (pm_runtime_active(data->sysmmu)) | |
911 | __sysmmu_enable(data); | |
912 | pm_runtime_put(data->sysmmu); | |
913 | } | |
914 | ||
915 | mutex_unlock(&owner->rpm_lock); | |
916 | ||
b0d4c861 MS |
917 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, |
918 | &pagetable); | |
7222e8db | 919 | |
b0d4c861 | 920 | return 0; |
2a96536e KC |
921 | } |
922 | ||
bfa00489 | 923 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 924 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 925 | { |
61128f08 | 926 | if (lv1ent_section(sent)) { |
d09d78fc | 927 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
928 | return ERR_PTR(-EADDRINUSE); |
929 | } | |
930 | ||
2a96536e | 931 | if (lv1ent_fault(sent)) { |
0d6d3da4 | 932 | dma_addr_t handle; |
d09d78fc | 933 | sysmmu_pte_t *pent; |
66a7ed84 | 934 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 935 | |
734c3c73 | 936 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
dbf6c6ef | 937 | BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 938 | if (!pent) |
61128f08 | 939 | return ERR_PTR(-ENOMEM); |
2a96536e | 940 | |
5e3435eb | 941 | update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 942 | kmemleak_ignore(pent); |
2a96536e | 943 | *pgcounter = NUM_LV2ENTRIES; |
0d6d3da4 MS |
944 | handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, |
945 | DMA_TO_DEVICE); | |
946 | if (dma_mapping_error(dma_dev, handle)) { | |
947 | kmem_cache_free(lv2table_kmem_cache, pent); | |
948 | return ERR_PTR(-EADDRINUSE); | |
949 | } | |
66a7ed84 CK |
950 | |
951 | /* | |
f171abab SK |
952 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
953 | * FLPD cache may cache the address of zero_l2_table. This | |
954 | * function replaces the zero_l2_table with new L2 page table | |
955 | * to write valid mappings. | |
66a7ed84 | 956 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
957 | * cache may still cache zero_l2_table for the valid area |
958 | * instead of new L2 page table that has the mapping | |
959 | * information of the valid area. | |
66a7ed84 CK |
960 | * Thus any replacement of zero_l2_table with other valid L2 |
961 | * page table must involve FLPD cache invalidation for System | |
962 | * MMU v3.3. | |
963 | * FLPD cache invalidation is performed with TLB invalidation | |
964 | * by VPN without blocking. It is safe to invalidate TLB without | |
965 | * blocking because the target address of TLB invalidation is | |
966 | * not currently mapped. | |
967 | */ | |
968 | if (need_flush_flpd_cache) { | |
469acebe | 969 | struct sysmmu_drvdata *data; |
365409db | 970 | |
bfa00489 MS |
971 | spin_lock(&domain->lock); |
972 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 973 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 974 | spin_unlock(&domain->lock); |
66a7ed84 | 975 | } |
2a96536e KC |
976 | } |
977 | ||
978 | return page_entry(sent, iova); | |
979 | } | |
980 | ||
bfa00489 | 981 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 982 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
1a0d8dac | 983 | phys_addr_t paddr, int prot, short *pgcnt) |
2a96536e | 984 | { |
61128f08 | 985 | if (lv1ent_section(sent)) { |
d09d78fc | 986 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 987 | iova); |
2a96536e | 988 | return -EADDRINUSE; |
61128f08 | 989 | } |
2a96536e KC |
990 | |
991 | if (lv1ent_page(sent)) { | |
61128f08 | 992 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 993 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 994 | iova); |
2a96536e | 995 | return -EADDRINUSE; |
61128f08 | 996 | } |
2a96536e | 997 | |
734c3c73 | 998 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
999 | *pgcnt = 0; |
1000 | } | |
1001 | ||
1a0d8dac | 1002 | update_pte(sent, mk_lv1ent_sect(paddr, prot)); |
2a96536e | 1003 | |
bfa00489 | 1004 | spin_lock(&domain->lock); |
66a7ed84 | 1005 | if (lv1ent_page_zero(sent)) { |
469acebe | 1006 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1007 | /* |
1008 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
1009 | * entry by speculative prefetch of SLPD which has no mapping. | |
1010 | */ | |
bfa00489 | 1011 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1012 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 1013 | } |
bfa00489 | 1014 | spin_unlock(&domain->lock); |
66a7ed84 | 1015 | |
2a96536e KC |
1016 | return 0; |
1017 | } | |
1018 | ||
d09d78fc | 1019 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
1a0d8dac | 1020 | int prot, short *pgcnt) |
2a96536e KC |
1021 | { |
1022 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 1023 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
1024 | return -EADDRINUSE; |
1025 | ||
1a0d8dac | 1026 | update_pte(pent, mk_lv2ent_spage(paddr, prot)); |
2a96536e KC |
1027 | *pgcnt -= 1; |
1028 | } else { /* size == LPAGE_SIZE */ | |
1029 | int i; | |
5e3435eb | 1030 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 1031 | |
5e3435eb MS |
1032 | dma_sync_single_for_cpu(dma_dev, pent_base, |
1033 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1034 | DMA_TO_DEVICE); | |
2a96536e | 1035 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 1036 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
1037 | if (i > 0) |
1038 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
1039 | return -EADDRINUSE; |
1040 | } | |
1041 | ||
1a0d8dac | 1042 | *pent = mk_lv2ent_lpage(paddr, prot); |
2a96536e | 1043 | } |
5e3435eb MS |
1044 | dma_sync_single_for_device(dma_dev, pent_base, |
1045 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1046 | DMA_TO_DEVICE); | |
2a96536e KC |
1047 | *pgcnt -= SPAGES_PER_LPAGE; |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
66a7ed84 CK |
1053 | /* |
1054 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
1055 | * | |
f171abab | 1056 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 1057 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
1058 | * However, the logic has a bug that while caching faulty page table entries, |
1059 | * System MMU reports page fault if the cached fault entry is hit even though | |
1060 | * the fault entry is updated to a valid entry after the entry is cached. | |
1061 | * To prevent caching faulty page table entries which may be updated to valid | |
1062 | * entries later, the virtual memory manager should care about the workaround | |
1063 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
1064 | * |
1065 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 1066 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 1067 | * |
f171abab | 1068 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
1069 | * the following sizes for System MMU v3.1 and v3.2. |
1070 | * System MMU v3.1: 128KiB | |
1071 | * System MMU v3.2: 256KiB | |
1072 | * | |
1073 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
1074 | * more workarounds. |
1075 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
1076 | * than or equal to 128KiB. | |
66a7ed84 CK |
1077 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
1078 | */ | |
bfa00489 MS |
1079 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
1080 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
1081 | int prot) | |
2a96536e | 1082 | { |
bfa00489 | 1083 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1084 | sysmmu_pte_t *entry; |
1085 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
1086 | unsigned long flags; |
1087 | int ret = -ENOMEM; | |
1088 | ||
bfa00489 | 1089 | BUG_ON(domain->pgtable == NULL); |
1a0d8dac | 1090 | prot &= SYSMMU_SUPPORTED_PROT_BITS; |
2a96536e | 1091 | |
bfa00489 | 1092 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1093 | |
bfa00489 | 1094 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1095 | |
1096 | if (size == SECT_SIZE) { | |
1a0d8dac | 1097 | ret = lv1set_section(domain, entry, iova, paddr, prot, |
bfa00489 | 1098 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e | 1099 | } else { |
d09d78fc | 1100 | sysmmu_pte_t *pent; |
2a96536e | 1101 | |
bfa00489 MS |
1102 | pent = alloc_lv2entry(domain, entry, iova, |
1103 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 1104 | |
61128f08 CK |
1105 | if (IS_ERR(pent)) |
1106 | ret = PTR_ERR(pent); | |
2a96536e | 1107 | else |
1a0d8dac | 1108 | ret = lv2set_page(pent, paddr, size, prot, |
bfa00489 | 1109 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1110 | } |
1111 | ||
61128f08 | 1112 | if (ret) |
0bf4e54d CK |
1113 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1114 | __func__, ret, size, iova); | |
2a96536e | 1115 | |
bfa00489 | 1116 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1117 | |
1118 | return ret; | |
1119 | } | |
1120 | ||
bfa00489 MS |
1121 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1122 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1123 | { |
469acebe | 1124 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1125 | unsigned long flags; |
1126 | ||
bfa00489 | 1127 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1128 | |
bfa00489 | 1129 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1130 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1131 | |
bfa00489 | 1132 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1133 | } |
1134 | ||
bfa00489 MS |
1135 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1136 | unsigned long l_iova, size_t size) | |
2a96536e | 1137 | { |
bfa00489 | 1138 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1139 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1140 | sysmmu_pte_t *ent; | |
61128f08 | 1141 | size_t err_pgsize; |
d09d78fc | 1142 | unsigned long flags; |
2a96536e | 1143 | |
bfa00489 | 1144 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1145 | |
bfa00489 | 1146 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1147 | |
bfa00489 | 1148 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1149 | |
1150 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1151 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1152 | err_pgsize = SECT_SIZE; |
1153 | goto err; | |
1154 | } | |
2a96536e | 1155 | |
f171abab | 1156 | /* workaround for h/w bug in System MMU v3.3 */ |
5e3435eb | 1157 | update_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1158 | size = SECT_SIZE; |
1159 | goto done; | |
1160 | } | |
1161 | ||
1162 | if (unlikely(lv1ent_fault(ent))) { | |
1163 | if (size > SECT_SIZE) | |
1164 | size = SECT_SIZE; | |
1165 | goto done; | |
1166 | } | |
1167 | ||
1168 | /* lv1ent_page(sent) == true here */ | |
1169 | ||
1170 | ent = page_entry(ent, iova); | |
1171 | ||
1172 | if (unlikely(lv2ent_fault(ent))) { | |
1173 | size = SPAGE_SIZE; | |
1174 | goto done; | |
1175 | } | |
1176 | ||
1177 | if (lv2ent_small(ent)) { | |
5e3435eb | 1178 | update_pte(ent, 0); |
2a96536e | 1179 | size = SPAGE_SIZE; |
bfa00489 | 1180 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1181 | goto done; |
1182 | } | |
1183 | ||
1184 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1185 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1186 | err_pgsize = LPAGE_SIZE; |
1187 | goto err; | |
1188 | } | |
2a96536e | 1189 | |
5e3435eb MS |
1190 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1191 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1192 | DMA_TO_DEVICE); | |
2a96536e | 1193 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1194 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1195 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1196 | DMA_TO_DEVICE); | |
2a96536e | 1197 | size = LPAGE_SIZE; |
bfa00489 | 1198 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1199 | done: |
bfa00489 | 1200 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1201 | |
bfa00489 | 1202 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1203 | |
2a96536e | 1204 | return size; |
61128f08 | 1205 | err: |
bfa00489 | 1206 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1207 | |
0bf4e54d CK |
1208 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1209 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1210 | |
1211 | return 0; | |
2a96536e KC |
1212 | } |
1213 | ||
bfa00489 | 1214 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1215 | dma_addr_t iova) |
2a96536e | 1216 | { |
bfa00489 | 1217 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1218 | sysmmu_pte_t *entry; |
2a96536e KC |
1219 | unsigned long flags; |
1220 | phys_addr_t phys = 0; | |
1221 | ||
bfa00489 | 1222 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1223 | |
bfa00489 | 1224 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1225 | |
1226 | if (lv1ent_section(entry)) { | |
1227 | phys = section_phys(entry) + section_offs(iova); | |
1228 | } else if (lv1ent_page(entry)) { | |
1229 | entry = page_entry(entry, iova); | |
1230 | ||
1231 | if (lv2ent_large(entry)) | |
1232 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1233 | else if (lv2ent_small(entry)) | |
1234 | phys = spage_phys(entry) + spage_offs(iova); | |
1235 | } | |
1236 | ||
bfa00489 | 1237 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1238 | |
1239 | return phys; | |
1240 | } | |
1241 | ||
6c2ae7e2 MS |
1242 | static struct iommu_group *get_device_iommu_group(struct device *dev) |
1243 | { | |
1244 | struct iommu_group *group; | |
1245 | ||
1246 | group = iommu_group_get(dev); | |
1247 | if (!group) | |
1248 | group = iommu_group_alloc(); | |
1249 | ||
1250 | return group; | |
1251 | } | |
1252 | ||
bf4a1c92 AM |
1253 | static int exynos_iommu_add_device(struct device *dev) |
1254 | { | |
7a974b29 MS |
1255 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
1256 | struct sysmmu_drvdata *data; | |
bf4a1c92 | 1257 | struct iommu_group *group; |
bf4a1c92 | 1258 | |
06801db0 MS |
1259 | if (!has_sysmmu(dev)) |
1260 | return -ENODEV; | |
1261 | ||
6c2ae7e2 | 1262 | group = iommu_group_get_for_dev(dev); |
bf4a1c92 | 1263 | |
6c2ae7e2 MS |
1264 | if (IS_ERR(group)) |
1265 | return PTR_ERR(group); | |
bf4a1c92 | 1266 | |
7a974b29 MS |
1267 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1268 | /* | |
1269 | * SYSMMU will be runtime activated via device link | |
1270 | * (dependency) to its master device, so there are no | |
1271 | * direct calls to pm_runtime_get/put in this driver. | |
1272 | */ | |
1273 | data->link = device_link_add(dev, data->sysmmu, | |
1274 | DL_FLAG_PM_RUNTIME); | |
1275 | } | |
bf4a1c92 AM |
1276 | iommu_group_put(group); |
1277 | ||
6c2ae7e2 | 1278 | return 0; |
bf4a1c92 AM |
1279 | } |
1280 | ||
1281 | static void exynos_iommu_remove_device(struct device *dev) | |
1282 | { | |
fff2fd1a | 1283 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
7a974b29 | 1284 | struct sysmmu_drvdata *data; |
fff2fd1a | 1285 | |
06801db0 MS |
1286 | if (!has_sysmmu(dev)) |
1287 | return; | |
1288 | ||
fff2fd1a MS |
1289 | if (owner->domain) { |
1290 | struct iommu_group *group = iommu_group_get(dev); | |
1291 | ||
1292 | if (group) { | |
1293 | WARN_ON(owner->domain != | |
1294 | iommu_group_default_domain(group)); | |
1295 | exynos_iommu_detach_device(owner->domain, dev); | |
1296 | iommu_group_put(group); | |
1297 | } | |
1298 | } | |
bf4a1c92 | 1299 | iommu_group_remove_device(dev); |
7a974b29 MS |
1300 | |
1301 | list_for_each_entry(data, &owner->controllers, owner_node) | |
1302 | device_link_del(data->link); | |
bf4a1c92 AM |
1303 | } |
1304 | ||
aa759fd3 MS |
1305 | static int exynos_iommu_of_xlate(struct device *dev, |
1306 | struct of_phandle_args *spec) | |
1307 | { | |
1308 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1309 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
0bd5a0c7 | 1310 | struct sysmmu_drvdata *data, *entry; |
aa759fd3 MS |
1311 | |
1312 | if (!sysmmu) | |
1313 | return -ENODEV; | |
1314 | ||
1315 | data = platform_get_drvdata(sysmmu); | |
1316 | if (!data) | |
1317 | return -ENODEV; | |
1318 | ||
1319 | if (!owner) { | |
1320 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1321 | if (!owner) | |
1322 | return -ENOMEM; | |
1323 | ||
1324 | INIT_LIST_HEAD(&owner->controllers); | |
9b265536 | 1325 | mutex_init(&owner->rpm_lock); |
aa759fd3 MS |
1326 | dev->archdata.iommu = owner; |
1327 | } | |
1328 | ||
0bd5a0c7 MS |
1329 | list_for_each_entry(entry, &owner->controllers, owner_node) |
1330 | if (entry == data) | |
1331 | return 0; | |
1332 | ||
aa759fd3 | 1333 | list_add_tail(&data->owner_node, &owner->controllers); |
92798b45 | 1334 | data->master = dev; |
2f5f44f2 | 1335 | |
aa759fd3 MS |
1336 | return 0; |
1337 | } | |
1338 | ||
0b9a3694 | 1339 | static const struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1340 | .domain_alloc = exynos_iommu_domain_alloc, |
1341 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1342 | .attach_dev = exynos_iommu_attach_device, |
1343 | .detach_dev = exynos_iommu_detach_device, | |
1344 | .map = exynos_iommu_map, | |
1345 | .unmap = exynos_iommu_unmap, | |
315786eb | 1346 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 | 1347 | .iova_to_phys = exynos_iommu_iova_to_phys, |
6c2ae7e2 | 1348 | .device_group = get_device_iommu_group, |
ba5fa6f6 BH |
1349 | .add_device = exynos_iommu_add_device, |
1350 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1351 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1352 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1353 | }; |
1354 | ||
1355 | static int __init exynos_iommu_init(void) | |
1356 | { | |
dc98b848 | 1357 | struct device_node *np; |
2a96536e KC |
1358 | int ret; |
1359 | ||
dc98b848 RM |
1360 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1361 | if (!np) | |
1362 | return 0; | |
1363 | ||
1364 | of_node_put(np); | |
1365 | ||
734c3c73 CK |
1366 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1367 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1368 | if (!lv2table_kmem_cache) { | |
1369 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1370 | return -ENOMEM; | |
1371 | } | |
1372 | ||
2a96536e | 1373 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1374 | if (ret) { |
1375 | pr_err("%s: Failed to register driver\n", __func__); | |
1376 | goto err_reg_driver; | |
1377 | } | |
2a96536e | 1378 | |
66a7ed84 CK |
1379 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1380 | if (zero_lv2_table == NULL) { | |
1381 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1382 | __func__); | |
1383 | ret = -ENOMEM; | |
1384 | goto err_zero_lv2; | |
1385 | } | |
1386 | ||
734c3c73 CK |
1387 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1388 | if (ret) { | |
1389 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1390 | __func__); | |
1391 | goto err_set_iommu; | |
1392 | } | |
2a96536e | 1393 | |
734c3c73 CK |
1394 | return 0; |
1395 | err_set_iommu: | |
66a7ed84 CK |
1396 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1397 | err_zero_lv2: | |
734c3c73 CK |
1398 | platform_driver_unregister(&exynos_sysmmu_driver); |
1399 | err_reg_driver: | |
1400 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1401 | return ret; |
1402 | } | |
928055a0 | 1403 | core_initcall(exynos_iommu_init); |
8ed55c81 | 1404 | |
b0c560f7 | 1405 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu"); |